* [U-Boot] [PATCHv3 0/6] dm: cache: add dm cache driver
@ 2019-03-25 15:19 Dinh Nguyen
2019-03-25 15:19 ` [U-Boot] [PATCHv3 1/6] Documentation: dts: Add pl310 cache controller dts documentation Dinh Nguyen
` (5 more replies)
0 siblings, 6 replies; 8+ messages in thread
From: Dinh Nguyen @ 2019-03-25 15:19 UTC (permalink / raw
To: u-boot
Hi,
This is V3 of the series to add a UCLASS_CACHE dm driver to handling
the configuration of cache settings. Place this new driver under
/drivers/cache. In this initial revision, the driver is only configuring
what I think are essential cache settings. The more comprehensive cache
settings can be done in the OS.
Diffs from v2:
- Add cache_get_info() to check for non-zero value
- Add comments to cache_info struct
- Fix up nits from Simon Glass
Dinh Nguyen (6):
Documentation: dts: Add pl310 cache controller dts documentation
ARM: pl310: Add macro's for handling tag and data latency mask
dm: cache: Create a uclass for cache
dm: cache: add the pl310 cache controller driver
ARM: socfpga: use the pl310 driver to configure the cache
configs: socfpga: add imply pl310 cache controller
.../devicetree/bindings/arm/l2c2x0.txt | 114 ++++++++++++++++++
arch/arm/Kconfig | 1 +
arch/arm/include/asm/pl310.h | 3 +
arch/arm/mach-socfpga/misc.c | 16 +--
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/cache/Kconfig | 25 ++++
drivers/cache/Makefile | 4 +
drivers/cache/cache-l2x0.c | 76 ++++++++++++
drivers/cache/cache-uclass.c | 24 ++++
drivers/cache/sandbox_cache.c | 34 ++++++
include/cache.h | 38 ++++++
include/dm/uclass-id.h | 1 +
test/dm/cache.c | 20 +++
14 files changed, 346 insertions(+), 13 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt
create mode 100644 drivers/cache/Kconfig
create mode 100644 drivers/cache/Makefile
create mode 100644 drivers/cache/cache-l2x0.c
create mode 100644 drivers/cache/cache-uclass.c
create mode 100644 drivers/cache/sandbox_cache.c
create mode 100644 include/cache.h
create mode 100644 test/dm/cache.c
--
2.20.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCHv3 1/6] Documentation: dts: Add pl310 cache controller dts documentation
2019-03-25 15:19 [U-Boot] [PATCHv3 0/6] dm: cache: add dm cache driver Dinh Nguyen
@ 2019-03-25 15:19 ` Dinh Nguyen
2019-03-25 15:19 ` [U-Boot] [PATCHv3 2/6] ARM: pl310: Add macro's for handling tag and data latency mask Dinh Nguyen
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Dinh Nguyen @ 2019-03-25 15:19 UTC (permalink / raw
To: u-boot
Linux commit 8ecd7f5970c5 ("ARM: 8483/1: Documentation: l2c: Rename
l2cc to l2c2x0")
Linux docs:
Documentation/devicetree/bindings/arm/l2c2x0.txt
Copied from Linux kernel v5.0.
"The documentation in the l2cc.txt is specific to the L2 cache
controllers L2C210/L2C220/L2C310 (also known as PL210/PL220/PL310
and variants) and not generic as the file name implies. It's not
valid for integrated L2 controllers as found in e.g.
Cortex-A15/A7/A57/A53."
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
.../devicetree/bindings/arm/l2c2x0.txt | 114 ++++++++++++++++++
1 file changed, 114 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt
diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt
new file mode 100644
index 0000000000..fbe6cb21f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
@@ -0,0 +1,114 @@
+* ARM L2 Cache Controller
+
+ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/
+PL310 and variants) based level 2 cache controller. All these various implementations
+of the L2 cache controller have compatible programming models (Note 1).
+Some of the properties that are just prefixed "cache-*" are taken from section
+3.7.3 of the Devicetree Specification which can be found at:
+https://www.devicetree.org/specifications/
+
+The ARM L2 cache representation in the device tree should be done as follows:
+
+Required properties:
+
+- compatible : should be one of:
+ "arm,pl310-cache"
+ "arm,l220-cache"
+ "arm,l210-cache"
+ "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+ "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+ offset needs to be added to the address before passing down to the L2
+ cache controller
+ "marvell,aurora-system-cache": Marvell Controller designed to be
+ compatible with the ARM one, with system cache mode (meaning
+ maintenance operations on L1 are broadcasted to the L2 and L2
+ performs the same operation).
+ "marvell,aurora-outer-cache": Marvell Controller designed to be
+ compatible with the ARM one with outer cache mode.
+ "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
+ with arm,pl310-cache controller.
+- cache-unified : Specifies the cache is a unified cache.
+- cache-level : Should be set to 2 for a level 2 cache.
+- reg : Physical base address and size of cache controller's memory mapped
+ registers.
+
+Optional properties:
+
+- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
+ read, write and setup latencies. Minimum valid values are 1. Controllers
+ without setup latency control should use a value of 0.
+- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
+ read, write and setup latencies. Controllers without setup latency control
+ should use 0. Controllers without separate read and write Tag RAM latency
+ values should only use the first cell.
+- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
+- arm,filter-ranges : <start length> Starting address and length of window to
+ filter. Addresses in the filter window are directed to the M1 port. Other
+ addresses will go to the M0 port.
+- arm,io-coherent : indicates that the system is operating in an hardware
+ I/O coherent mode. Valid only when the arm,pl310-cache compatible
+ string is used.
+- interrupts : 1 combined interrupt.
+- cache-size : specifies the size in bytes of the cache
+- cache-sets : specifies the number of associativity sets of the cache
+- cache-block-size : specifies the size in bytes of a cache block
+- cache-line-size : specifies the size in bytes of a line in the cache,
+ if this is not specified, the line size is assumed to be equal to the
+ cache block size
+- cache-id-part: cache id part number to be used if it is not present
+ on hardware
+- wt-override: If present then L2 is forced to Write through mode
+- arm,double-linefill : Override double linefill enable setting. Enable if
+ non-zero, disable if zero.
+- arm,double-linefill-incr : Override double linefill on INCR read. Enable
+ if non-zero, disable if zero.
+- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
+ if non-zero, disable if zero.
+- arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero,
+ disable if zero.
+- arm,prefetch-offset : Override prefetch offset value. Valid values are
+ 0-7, 15, 23, and 31.
+- arm,shared-override : The default behavior of the L220 or PL310 cache
+ controllers with respect to the shareable attribute is to transform "normal
+ memory non-cacheable transactions" into "cacheable no allocate" (for reads)
+ or "write through no write allocate" (for writes).
+ On systems where this may cause DMA buffer corruption, this property must be
+ specified to indicate that such transforms are precluded.
+- arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310).
+- arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310).
+- arm,outer-sync-disable : disable the outer sync operation on the L2 cache.
+ Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
+ will randomly hang unless outer sync operations are disabled.
+- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1>
+ (forcibly enable), property absent (retain settings set by firmware)
+- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
+ <1> (forcibly enable), property absent (retain settings set by
+ firmware)
+- arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly
+ disable), <1> (forcibly enable), property absent (OS specific behavior,
+ preferably retain firmware settings)
+- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
+ <1> (forcibly enable), property absent (OS specific behavior,
+ preferably retain firmware settings)
+- arm,early-bresp-disable : Disable the CA9 optimization Early BRESP (PL310)
+- arm,full-line-zero-disable : Disable the CA9 optimization Full line of zero
+ write (PL310)
+
+Example:
+
+L2: cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0xfff12000 0x1000>;
+ arm,data-latency = <1 1 1>;
+ arm,tag-latency = <2 2 2>;
+ arm,filter-ranges = <0x80000000 0x8000000>;
+ cache-unified;
+ cache-level = <2>;
+ interrupts = <45>;
+};
+
+Note 1: The description in this document doesn't apply to integrated L2
+ cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
+ integrated L2 controllers are assumed to be all preconfigured by
+ early secure boot code. Thus no need to deal with their configuration
+ in the kernel at all.
--
2.20.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCHv3 2/6] ARM: pl310: Add macro's for handling tag and data latency mask
2019-03-25 15:19 [U-Boot] [PATCHv3 0/6] dm: cache: add dm cache driver Dinh Nguyen
2019-03-25 15:19 ` [U-Boot] [PATCHv3 1/6] Documentation: dts: Add pl310 cache controller dts documentation Dinh Nguyen
@ 2019-03-25 15:19 ` Dinh Nguyen
2019-03-25 15:19 ` [U-Boot] [PATCHv3 3/6] dm: cache: Create a uclass for cache Dinh Nguyen
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Dinh Nguyen @ 2019-03-25 15:19 UTC (permalink / raw
To: u-boot
Add the PL310 macros for latency control setup, read and write bits.
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/include/asm/pl310.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index b83978b1cc..f69e9e45f8 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -18,6 +18,9 @@
#define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22)
#define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28)
#define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29)
+#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
+#define L310_LATENCY_CTRL_RD(n) ((n) << 4)
+#define L310_LATENCY_CTRL_WR(n) ((n) << 8)
#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
#define L2X0_CACHE_ID_PART_L310 (3 << 6)
--
2.20.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCHv3 3/6] dm: cache: Create a uclass for cache
2019-03-25 15:19 [U-Boot] [PATCHv3 0/6] dm: cache: add dm cache driver Dinh Nguyen
2019-03-25 15:19 ` [U-Boot] [PATCHv3 1/6] Documentation: dts: Add pl310 cache controller dts documentation Dinh Nguyen
2019-03-25 15:19 ` [U-Boot] [PATCHv3 2/6] ARM: pl310: Add macro's for handling tag and data latency mask Dinh Nguyen
@ 2019-03-25 15:19 ` Dinh Nguyen
2019-03-30 21:18 ` Simon Glass
2019-03-25 15:19 ` [U-Boot] [PATCHv3 4/6] dm: cache: add the pl310 cache controller driver Dinh Nguyen
` (2 subsequent siblings)
5 siblings, 1 reply; 8+ messages in thread
From: Dinh Nguyen @ 2019-03-25 15:19 UTC (permalink / raw
To: u-boot
The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.
Add a uclass and a test for cache.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v3: Add cache_get_info() to check for non-zero value
Add comments to cache_info struct
v2: separate out uclass patch from driver and add test
---
drivers/Kconfig | 2 ++
drivers/Makefile | 1 +
drivers/cache/Kconfig | 16 +++++++++++++++
drivers/cache/Makefile | 3 +++
drivers/cache/cache-uclass.c | 24 ++++++++++++++++++++++
drivers/cache/sandbox_cache.c | 34 +++++++++++++++++++++++++++++++
include/cache.h | 38 +++++++++++++++++++++++++++++++++++
include/dm/uclass-id.h | 1 +
test/dm/cache.c | 20 ++++++++++++++++++
9 files changed, 139 insertions(+)
create mode 100644 drivers/cache/Kconfig
create mode 100644 drivers/cache/Makefile
create mode 100644 drivers/cache/cache-uclass.c
create mode 100644 drivers/cache/sandbox_cache.c
create mode 100644 include/cache.h
create mode 100644 test/dm/cache.c
diff --git a/drivers/Kconfig b/drivers/Kconfig
index f24351ac4f..842201b753 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/block/Kconfig"
source "drivers/bootcount/Kconfig"
+source "drivers/cache/Kconfig"
+
source "drivers/clk/Kconfig"
source "drivers/cpu/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index a7bba3ed56..0a00096332 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_BIOSEMU) += bios_emulator/
obj-y += block/
obj-y += board/
obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
+obj-y += cache/
obj-$(CONFIG_CPU) += cpu/
obj-y += crypto/
obj-$(CONFIG_FASTBOOT) += fastboot/
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
new file mode 100644
index 0000000000..8b7c9c7f9f
--- /dev/null
+++ b/drivers/cache/Kconfig
@@ -0,0 +1,16 @@
+#
+# Cache controllers
+#
+
+menu "Cache Controller drivers"
+
+config CACHE
+ bool "Enable Driver Model for Cache controllers"
+ depends on DM
+ help
+ Enable driver model for cache controllers that are found on
+ most CPU's. Cache is memory that the CPU can access directly and
+ is usually located on the same chip. This uclass can be used for
+ configuring settings that be found from a device tree file.
+
+endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
new file mode 100644
index 0000000000..2ba68060c1
--- /dev/null
+++ b/drivers/cache/Makefile
@@ -0,0 +1,3 @@
+
+obj-$(CONFIG_CACHE) += cache-uclass.o
+obj-$(CONFIG_SANDBOX) += sandbox_cache.o
diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
new file mode 100644
index 0000000000..97ce0249a4
--- /dev/null
+++ b/drivers/cache/cache-uclass.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <cache.h>
+#include <dm.h>
+
+int cache_get_info(struct udevice *dev, struct cache_info *info)
+{
+ struct cache_ops *ops = cache_get_ops(dev);
+
+ if (!ops->get_info)
+ return -ENOSYS;
+
+ return ops->get_info(dev, info);
+}
+
+UCLASS_DRIVER(cache) = {
+ .id = UCLASS_CACHE,
+ .name = "cache",
+ .post_bind = dm_scan_fdt_dev,
+};
diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c
new file mode 100644
index 0000000000..b67ce31218
--- /dev/null
+++ b/drivers/cache/sandbox_cache.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <cache.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_get_info(struct udevice *dev, struct cache_info *info)
+{
+ info->base = 0;
+
+ return 0;
+}
+
+static const struct cache_ops sandbox_cache_ops = {
+ .get_info = sandbox_get_info,
+};
+
+static const struct udevice_id sandbox_cache_ids[] = {
+ { .compatible = "sandbox,cache" },
+ { }
+};
+
+U_BOOT_DRIVER(cache_sandbox) = {
+ .name = "cache_sandbox",
+ .id = UCLASS_CACHE,
+ .of_match = sandbox_cache_ids,
+ .ops = &sandbox_cache_ops,
+};
diff --git a/include/cache.h b/include/cache.h
new file mode 100644
index 0000000000..c6334ca27f
--- /dev/null
+++ b/include/cache.h
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+/*
+ * Structure for the cache controller
+ */
+struct cache_info {
+ phys_addr_t base; /* Base physical address of cache device. */
+};
+
+struct cache_ops {
+ /**
+ * get_info() - Get basic cache info
+ *
+ * @dev: Device to check (UCLASS_CACHE)
+ * @info: Place to put info
+ * @return 0 if OK, -ve on error
+ */
+ int (*get_info)(struct udevice *dev, struct cache_info *info);
+};
+
+#define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops)
+
+/**
+ * cache_get_info() - Get information about a cache controller
+ *
+ * @dev: Device to check (UCLASS_CACHE)
+ * @info: Returns cache info
+ * @return 0 if OK, -ve on error
+ */
+int cache_get_info(struct udevice *dev, struct cache_info *info);
+
+#endif
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 86e59781b0..09e0ad5391 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -34,6 +34,7 @@ enum uclass_id {
UCLASS_BLK, /* Block device */
UCLASS_BOARD, /* Device information from hardware */
UCLASS_BOOTCOUNT, /* Bootcount backing store */
+ UCLASS_CACHE, /* Cache controller */
UCLASS_CLK, /* Clock source, e.g. used by peripherals */
UCLASS_CPU, /* CPU, typically part of an SoC */
UCLASS_CROS_EC, /* Chrome OS EC */
diff --git a/test/dm/cache.c b/test/dm/cache.c
new file mode 100644
index 0000000000..d4144aab76
--- /dev/null
+++ b/test/dm/cache.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+
+static int dm_test_reset(struct unit_test_state *uts)
+{
+ struct udevice *dev_cache;
+ struct cache_info;
+
+ ut_assertok(uclass_get_device(UCLASS_CACHE, 0, &dev_cache));
+ ut_assertok(cache_get_info(dev, &info));
+
+ return 0;
+}
+DM_TEST(dm_test_reset, DM_TESTF_SCAN_FDT);
--
2.20.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCHv3 4/6] dm: cache: add the pl310 cache controller driver
2019-03-25 15:19 [U-Boot] [PATCHv3 0/6] dm: cache: add dm cache driver Dinh Nguyen
` (2 preceding siblings ...)
2019-03-25 15:19 ` [U-Boot] [PATCHv3 3/6] dm: cache: Create a uclass for cache Dinh Nguyen
@ 2019-03-25 15:19 ` Dinh Nguyen
2019-03-25 15:19 ` [U-Boot] [PATCHv3 5/6] ARM: socfpga: use the pl310 driver to configure the cache Dinh Nguyen
2019-03-25 15:19 ` [U-Boot] [PATCHv3 6/6] configs: socfpga: add imply pl310 cache controller Dinh Nguyen
5 siblings, 0 replies; 8+ messages in thread
From: Dinh Nguyen @ 2019-03-25 15:19 UTC (permalink / raw
To: u-boot
Add a PL310 cache controller driver that is usually found on
ARMv7(32-bit) devices. The driver configures the cache settings that can
be found in the device tree files.
This initial revision only configures basic settings(data & instruction
prefetch, shared-override, data & tag latency). I believe these are the
settings that affect performance the most. Comprehensive settings can be
done by the OS.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v3: Add Reviewed-by and fix nits
v2: split out patch and address comments from Simon Glass
---
drivers/cache/Kconfig | 9 +++++
drivers/cache/Makefile | 1 +
drivers/cache/cache-l2x0.c | 76 ++++++++++++++++++++++++++++++++++++++
3 files changed, 86 insertions(+)
create mode 100644 drivers/cache/cache-l2x0.c
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 8b7c9c7f9f..24def7ac0f 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -13,4 +13,13 @@ config CACHE
is usually located on the same chip. This uclass can be used for
configuring settings that be found from a device tree file.
+config L2X0_CACHE
+ tristate "PL310 cache driver"
+ select CACHE
+ depends on ARM
+ help
+ This driver is for the PL310 cache controller commonly found on
+ ARMv7(32-bit) devices. The driver configures the cache settings
+ found in the device tree.
+
endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 2ba68060c1..9deb961d91 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_CACHE) += cache-uclass.o
obj-$(CONFIG_SANDBOX) += sandbox_cache.o
+obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c
new file mode 100644
index 0000000000..67c752d076
--- /dev/null
+++ b/drivers/cache/cache-l2x0.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+
+#include <asm/io.h>
+#include <asm/pl310.h>
+
+static void l2c310_of_parse_and_init(struct udevice *dev)
+{
+ u32 tag[3] = { 0, 0, 0 };
+ u32 saved_reg, prefetch;
+ struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev);
+
+ /* Disable the L2 Cache */
+ clrbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN);
+
+ saved_reg = readl(®s->pl310_aux_ctrl);
+ if (!dev_read_u32(dev, "prefetch-data", &prefetch)) {
+ if (prefetch)
+ saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
+ else
+ saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK;
+ }
+
+ if (!dev_read_u32(dev, "prefetch-instr", &prefetch)) {
+ if (prefetch)
+ saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
+ else
+ saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
+ }
+
+ saved_reg |= dev_read_bool(dev, "arm,shared-override");
+ writel(saved_reg, ®s->pl310_aux_ctrl);
+
+ saved_reg = readl(®s->pl310_tag_latency_ctrl);
+ if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))
+ saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+ L310_LATENCY_CTRL_WR(tag[1] - 1) |
+ L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+ writel(saved_reg, ®s->pl310_tag_latency_ctrl);
+
+ saved_reg = readl(®s->pl310_data_latency_ctrl);
+ if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3))
+ saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+ L310_LATENCY_CTRL_WR(tag[1] - 1) |
+ L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+ writel(saved_reg, ®s->pl310_data_latency_ctrl);
+
+ /* Enable the L2 cache */
+ setbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+static int l2x0_probe(struct udevice *dev)
+{
+ l2c310_of_parse_and_init(dev);
+
+ return 0;
+}
+
+
+static const struct udevice_id l2x0_ids[] = {
+ { .compatible = "arm,pl310-cache" },
+ {}
+};
+
+U_BOOT_DRIVER(pl310_cache) = {
+ .name = "pl310_cache",
+ .id = UCLASS_CACHE,
+ .of_match = l2x0_ids,
+ .probe = l2x0_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.20.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCHv3 5/6] ARM: socfpga: use the pl310 driver to configure the cache
2019-03-25 15:19 [U-Boot] [PATCHv3 0/6] dm: cache: add dm cache driver Dinh Nguyen
` (3 preceding siblings ...)
2019-03-25 15:19 ` [U-Boot] [PATCHv3 4/6] dm: cache: add the pl310 cache controller driver Dinh Nguyen
@ 2019-03-25 15:19 ` Dinh Nguyen
2019-03-25 15:19 ` [U-Boot] [PATCHv3 6/6] configs: socfpga: add imply pl310 cache controller Dinh Nguyen
5 siblings, 0 replies; 8+ messages in thread
From: Dinh Nguyen @ 2019-03-25 15:19 UTC (permalink / raw
To: u-boot
Find the UCLASS_CACHE driver to configure the cache controller's
settings.
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/mach-socfpga/misc.c | 16 +++-------------
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ec8339e045..34d8c4c51b 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -59,20 +59,10 @@ void enable_caches(void)
#ifdef CONFIG_SYS_L2_PL310
void v7_outer_cache_enable(void)
{
- /* Disable the L2 cache */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
- writel(0x0, &pl310->pl310_tag_latency_ctrl);
- writel(0x10, &pl310->pl310_data_latency_ctrl);
-
- /* enable BRESP, instruction and data prefetch, full line of zeroes */
- setbits_le32(&pl310->pl310_aux_ctrl,
- L310_AUX_CTRL_DATA_PREFETCH_MASK |
- L310_AUX_CTRL_INST_PREFETCH_MASK |
- L310_SHARED_ATT_OVERRIDE_ENABLE);
+ struct udevice *dev;
- /* Enable the L2 cache */
- setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+ if (uclass_get_device(UCLASS_CACHE, 0, &dev))
+ pr_err("cache controller driver NOT found!\n");
}
void v7_outer_cache_disable(void)
--
2.20.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCHv3 6/6] configs: socfpga: add imply pl310 cache controller
2019-03-25 15:19 [U-Boot] [PATCHv3 0/6] dm: cache: add dm cache driver Dinh Nguyen
` (4 preceding siblings ...)
2019-03-25 15:19 ` [U-Boot] [PATCHv3 5/6] ARM: socfpga: use the pl310 driver to configure the cache Dinh Nguyen
@ 2019-03-25 15:19 ` Dinh Nguyen
5 siblings, 0 replies; 8+ messages in thread
From: Dinh Nguyen @ 2019-03-25 15:19 UTC (permalink / raw
To: u-boot
Select the PL310 UCLASS_CACHE driver for SoCFPGA.
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f42eccef80..f4c6262bb0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -845,6 +845,7 @@ config ARCH_SOCFPGA
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
imply SPL_SPI_FLASH_SUPPORT
imply SPL_SPI_SUPPORT
+ imply L2X0_CACHE
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
--
2.20.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCHv3 3/6] dm: cache: Create a uclass for cache
2019-03-25 15:19 ` [U-Boot] [PATCHv3 3/6] dm: cache: Create a uclass for cache Dinh Nguyen
@ 2019-03-30 21:18 ` Simon Glass
0 siblings, 0 replies; 8+ messages in thread
From: Simon Glass @ 2019-03-30 21:18 UTC (permalink / raw
To: u-boot
Hi Dinh,
On Mon, 25 Mar 2019 at 09:20, Dinh Nguyen <dinguyen@kernel.org> wrote:
>
> The cache UCLASS will be used for configure settings that can be found
> in a CPU's L2 cache controller.
>
> Add a uclass and a test for cache.
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> v3: Add cache_get_info() to check for non-zero value
> Add comments to cache_info struct
> v2: separate out uclass patch from driver and add test
> ---
> drivers/Kconfig | 2 ++
> drivers/Makefile | 1 +
> drivers/cache/Kconfig | 16 +++++++++++++++
> drivers/cache/Makefile | 3 +++
> drivers/cache/cache-uclass.c | 24 ++++++++++++++++++++++
> drivers/cache/sandbox_cache.c | 34 +++++++++++++++++++++++++++++++
> include/cache.h | 38 +++++++++++++++++++++++++++++++++++
> include/dm/uclass-id.h | 1 +
> test/dm/cache.c | 20 ++++++++++++++++++
> 9 files changed, 139 insertions(+)
> create mode 100644 drivers/cache/Kconfig
> create mode 100644 drivers/cache/Makefile
> create mode 100644 drivers/cache/cache-uclass.c
> create mode 100644 drivers/cache/sandbox_cache.c
> create mode 100644 include/cache.h
> create mode 100644 test/dm/cache.c
Reviewed-by: Simon Glass <sjg@chromium.org>
One nit - make sure that cache.h becomes before dm.h in the include order.
Regards,
Simon
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-03-30 21:18 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-03-25 15:19 [U-Boot] [PATCHv3 0/6] dm: cache: add dm cache driver Dinh Nguyen
2019-03-25 15:19 ` [U-Boot] [PATCHv3 1/6] Documentation: dts: Add pl310 cache controller dts documentation Dinh Nguyen
2019-03-25 15:19 ` [U-Boot] [PATCHv3 2/6] ARM: pl310: Add macro's for handling tag and data latency mask Dinh Nguyen
2019-03-25 15:19 ` [U-Boot] [PATCHv3 3/6] dm: cache: Create a uclass for cache Dinh Nguyen
2019-03-30 21:18 ` Simon Glass
2019-03-25 15:19 ` [U-Boot] [PATCHv3 4/6] dm: cache: add the pl310 cache controller driver Dinh Nguyen
2019-03-25 15:19 ` [U-Boot] [PATCHv3 5/6] ARM: socfpga: use the pl310 driver to configure the cache Dinh Nguyen
2019-03-25 15:19 ` [U-Boot] [PATCHv3 6/6] configs: socfpga: add imply pl310 cache controller Dinh Nguyen
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.