From mboxrd@z Thu Jan 1 00:00:00 1970 From: Hou Zhiqiang Date: Tue, 23 Jul 2019 21:09:08 +0800 Subject: [U-Boot] [PATCH 17/47] t104x: dts: Added PCIe DT nodes In-Reply-To: <20190723130938.47805-1-Zhiqiang.Hou@nxp.com> References: <20190723130938.47805-1-Zhiqiang.Hou@nxp.com> Message-ID: <20190723130938.47805-18-Zhiqiang.Hou@nxp.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: quoted-printable To: u-boot@lists.denx.de T104x integrated 4 PCIe controllers, which is compatible with the PCI Express=E2=84=A2 Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang --- arch/powerpc/dts/t104x.dtsi | 48 +++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 48 insertions(+) diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi index ff0da93..5998967 100644 --- a/arch/powerpc/dts/t104x.dtsi +++ b/arch/powerpc/dts/t104x.dtsi @@ -59,4 +59,52 @@ clock-frequency =3D <0x0>; }; }; + + pcie at ffe240000 { + compatible =3D "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq"; + reg =3D <0xf 0xfe240000 0x0 0x1000>; /* registers */ + law_trgt_if =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + bus-range =3D <0x0 0xff>; + ranges =3D <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /*= downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-pref= etchable memory */ + }; + + pcie at ffe250000 { + compatible =3D "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq"; + reg =3D <0xf 0xfe250000 0x0 0x1000>; /* registers */ + law_trgt_if =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + bus-range =3D <0x0 0xff>; + ranges =3D <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /*= downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-pref= etchable memory */ + }; + + pcie at ffe260000 { + compatible =3D "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq"; + reg =3D <0xf 0xfe260000 0x0 0x1000>; /* registers */ + law_trgt_if =3D <2>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + bus-range =3D <0x0 0xff>; + ranges =3D <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /*= downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-pref= etchable memory */ + }; + + pcie at ffe270000 { + compatible =3D "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq"; + reg =3D <0xf 0xfe270000 0x0 0x1000>; /* registers */ + law_trgt_if =3D <3>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + bus-range =3D <0x0 0xff>; + ranges =3D <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /*= downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-pref= etchable memory */ + }; }; --=20 2.9.5