From mboxrd@z Thu Jan 1 00:00:00 1970 From: Hou Zhiqiang Date: Tue, 23 Jul 2019 21:09:36 +0800 Subject: [U-Boot] [PATCH 45/47] MPC8548: dts: Added PCIe DT node In-Reply-To: <20190723130938.47805-1-Zhiqiang.Hou@nxp.com> References: <20190723130938.47805-1-Zhiqiang.Hou@nxp.com> Message-ID: <20190723130938.47805-46-Zhiqiang.Hou@nxp.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: quoted-printable To: u-boot@lists.denx.de MPC8548 integrated a PCIe controllers, which is compatible with the PCI Express=E2=84=A2 Base Specification, Revision 1.0a, and this patch is to add DT node for the PCIe controller. Signed-off-by: Hou Zhiqiang --- arch/powerpc/dts/mpc8548-post.dtsi | 9 +++++++++ arch/powerpc/dts/mpc8548cds.dts | 6 ++++++ arch/powerpc/dts/mpc8548cds_36b.dts | 6 ++++++ 3 files changed, 21 insertions(+) diff --git a/arch/powerpc/dts/mpc8548-post.dtsi b/arch/powerpc/dts/mpc8548-= post.dtsi index 5533a4b..2206f2d 100644 --- a/arch/powerpc/dts/mpc8548-post.dtsi +++ b/arch/powerpc/dts/mpc8548-post.dtsi @@ -25,3 +25,12 @@ last-interrupt-source =3D <255>; }; }; + +&pcie { + compatible =3D "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq"; + law_trgt_if =3D <2>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + bus-range =3D <0x0 0xff>; +}; diff --git a/arch/powerpc/dts/mpc8548cds.dts b/arch/powerpc/dts/mpc8548cds.= dts index cceea34..3b927bd 100644 --- a/arch/powerpc/dts/mpc8548cds.dts +++ b/arch/powerpc/dts/mpc8548cds.dts @@ -18,6 +18,12 @@ soc: soc8548 at e0000000 { ranges =3D <0x0 0x0 0xe0000000 0x100000>; }; + + pcie: pcie at e000a000 { + reg =3D <0x0 0xe000a000 0x0 0x1000>; /* registers */ + ranges =3D <0x01000000 0x0 0x00000000 0x0 0xe3000000 0x0 0x00100000 /*= downstream I/O */ + 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-pref= etchable memory */ + }; }; =20 /include/ "mpc8548-post.dtsi" diff --git a/arch/powerpc/dts/mpc8548cds_36b.dts b/arch/powerpc/dts/mpc8548= cds_36b.dts index faff35c..98d7c24 100644 --- a/arch/powerpc/dts/mpc8548cds_36b.dts +++ b/arch/powerpc/dts/mpc8548cds_36b.dts @@ -18,6 +18,12 @@ soc: soc8548 at fe0000000 { ranges =3D <0x0 0xf 0xe0000000 0x100000>; }; + + pcie: pcie at fe000a000 { + reg =3D <0xf 0xe000a000 0x0 0x1000>; /* registers */ + ranges =3D <0x01000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x00100000 /*= downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-pref= etchable memory */ + }; }; =20 /include/ "mpc8548-post.dtsi" --=20 2.9.5