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* [sashal-linux-stable:queue-5.4 166/234] arch/powerpc/lib/sstep.c:1339:3: error: label 'unknown_opcode' used but not defined
@ 2021-03-01  6:24 kernel test robot
  0 siblings, 0 replies; only message in thread
From: kernel test robot @ 2021-03-01  6:24 UTC (permalink / raw
  To: kbuild-all

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tree:   https://git.kernel.org/pub/scm/linux/kernel/git/sashal/linux-stable.git queue-5.4
head:   a3ca607df36fef4ecb3566ada39c01dc99c858ab
commit: 1dcc60e976b6f4c9ccf0f3939c43b3ec0057f8f2 [166/234] powerpc/sstep: Fix incorrect return from analyze_instr()
config: powerpc64-randconfig-s032-20210301 (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # apt-get install sparse
        # sparse version: v0.6.3-241-geaceeafa-dirty
        # https://git.kernel.org/pub/scm/linux/kernel/git/sashal/linux-stable.git/commit/?id=1dcc60e976b6f4c9ccf0f3939c43b3ec0057f8f2
        git remote add sashal-linux-stable https://git.kernel.org/pub/scm/linux/kernel/git/sashal/linux-stable.git
        git fetch --no-tags sashal-linux-stable queue-5.4
        git checkout 1dcc60e976b6f4c9ccf0f3939c43b3ec0057f8f2
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=powerpc64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   arch/powerpc/lib/sstep.c: In function 'analyse_instr':
   arch/powerpc/lib/sstep.c:1147:61: error: comparison of unsigned expression >= 0 is always true [-Werror=type-limits]
    1147 | #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
         |                                                             ^~
   arch/powerpc/lib/sstep.c:1975:33: note: in expansion of macro 'MASK64'
    1975 |     op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
         |                                 ^~~~~~
>> arch/powerpc/lib/sstep.c:1339:3: error: label 'unknown_opcode' used but not defined
    1339 |   goto unknown_opcode;
         |   ^~~~
   cc1: all warnings being treated as errors
--
   arch/powerpc/lib/sstep.c: In function 'analyse_instr':
   arch/powerpc/lib/sstep.c:1147:61: warning: comparison of unsigned expression >= 0 is always true [-Wtype-limits]
    1147 | #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
         |                                                             ^~
   arch/powerpc/lib/sstep.c:1975:33: note: in expansion of macro 'MASK64'
    1975 |     op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
         |                                 ^~~~~~
>> arch/powerpc/lib/sstep.c:1339:3: error: label 'unknown_opcode' used but not defined
    1339 |   goto unknown_opcode;
         |   ^~~~


"sparse warnings: (new ones prefixed by >>)"
>> arch/powerpc/lib/sstep.c:1339:17: sparse: sparse: label 'unknown_opcode' was not declared

vim +/unknown_opcode +1339 arch/powerpc/lib/sstep.c

  1138	
  1139	/*
  1140	 * Elements of 32-bit rotate and mask instructions.
  1141	 */
  1142	#define MASK32(mb, me)	((0xffffffffUL >> (mb)) + \
  1143				 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
  1144	#ifdef __powerpc64__
  1145	#define MASK64_L(mb)	(~0UL >> (mb))
  1146	#define MASK64_R(me)	((signed long)-0x8000000000000000L >> (me))
> 1147	#define MASK64(mb, me)	(MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
  1148	#define DATA32(x)	(((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
  1149	#else
  1150	#define DATA32(x)	(x)
  1151	#endif
  1152	#define ROTATE(x, n)	((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
  1153	
  1154	/*
  1155	 * Decode an instruction, and return information about it in *op
  1156	 * without changing *regs.
  1157	 * Integer arithmetic and logical instructions, branches, and barrier
  1158	 * instructions can be emulated just using the information in *op.
  1159	 *
  1160	 * Return value is 1 if the instruction can be emulated just by
  1161	 * updating *regs with the information in *op, -1 if we need the
  1162	 * GPRs but *regs doesn't contain the full register set, or 0
  1163	 * otherwise.
  1164	 */
  1165	int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
  1166			  unsigned int instr)
  1167	{
  1168		unsigned int opcode, ra, rb, rc, rd, spr, u;
  1169		unsigned long int imm;
  1170		unsigned long int val, val2;
  1171		unsigned int mb, me, sh;
  1172		long ival;
  1173	
  1174		op->type = COMPUTE;
  1175	
  1176		opcode = instr >> 26;
  1177		switch (opcode) {
  1178		case 16:	/* bc */
  1179			op->type = BRANCH;
  1180			imm = (signed short)(instr & 0xfffc);
  1181			if ((instr & 2) == 0)
  1182				imm += regs->nip;
  1183			op->val = truncate_if_32bit(regs->msr, imm);
  1184			if (instr & 1)
  1185				op->type |= SETLK;
  1186			if (branch_taken(instr, regs, op))
  1187				op->type |= BRTAKEN;
  1188			return 1;
  1189	#ifdef CONFIG_PPC64
  1190		case 17:	/* sc */
  1191			if ((instr & 0xfe2) == 2)
  1192				op->type = SYSCALL;
  1193			else
  1194				op->type = UNKNOWN;
  1195			return 0;
  1196	#endif
  1197		case 18:	/* b */
  1198			op->type = BRANCH | BRTAKEN;
  1199			imm = instr & 0x03fffffc;
  1200			if (imm & 0x02000000)
  1201				imm -= 0x04000000;
  1202			if ((instr & 2) == 0)
  1203				imm += regs->nip;
  1204			op->val = truncate_if_32bit(regs->msr, imm);
  1205			if (instr & 1)
  1206				op->type |= SETLK;
  1207			return 1;
  1208		case 19:
  1209			switch ((instr >> 1) & 0x3ff) {
  1210			case 0:		/* mcrf */
  1211				op->type = COMPUTE + SETCC;
  1212				rd = 7 - ((instr >> 23) & 0x7);
  1213				ra = 7 - ((instr >> 18) & 0x7);
  1214				rd *= 4;
  1215				ra *= 4;
  1216				val = (regs->ccr >> ra) & 0xf;
  1217				op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
  1218				return 1;
  1219	
  1220			case 16:	/* bclr */
  1221			case 528:	/* bcctr */
  1222				op->type = BRANCH;
  1223				imm = (instr & 0x400)? regs->ctr: regs->link;
  1224				op->val = truncate_if_32bit(regs->msr, imm);
  1225				if (instr & 1)
  1226					op->type |= SETLK;
  1227				if (branch_taken(instr, regs, op))
  1228					op->type |= BRTAKEN;
  1229				return 1;
  1230	
  1231			case 18:	/* rfid, scary */
  1232				if (regs->msr & MSR_PR)
  1233					goto priv;
  1234				op->type = RFI;
  1235				return 0;
  1236	
  1237			case 150:	/* isync */
  1238				op->type = BARRIER | BARRIER_ISYNC;
  1239				return 1;
  1240	
  1241			case 33:	/* crnor */
  1242			case 129:	/* crandc */
  1243			case 193:	/* crxor */
  1244			case 225:	/* crnand */
  1245			case 257:	/* crand */
  1246			case 289:	/* creqv */
  1247			case 417:	/* crorc */
  1248			case 449:	/* cror */
  1249				op->type = COMPUTE + SETCC;
  1250				ra = (instr >> 16) & 0x1f;
  1251				rb = (instr >> 11) & 0x1f;
  1252				rd = (instr >> 21) & 0x1f;
  1253				ra = (regs->ccr >> (31 - ra)) & 1;
  1254				rb = (regs->ccr >> (31 - rb)) & 1;
  1255				val = (instr >> (6 + ra * 2 + rb)) & 1;
  1256				op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
  1257					(val << (31 - rd));
  1258				return 1;
  1259			}
  1260			break;
  1261		case 31:
  1262			switch ((instr >> 1) & 0x3ff) {
  1263			case 598:	/* sync */
  1264				op->type = BARRIER + BARRIER_SYNC;
  1265	#ifdef __powerpc64__
  1266				switch ((instr >> 21) & 3) {
  1267				case 1:		/* lwsync */
  1268					op->type = BARRIER + BARRIER_LWSYNC;
  1269					break;
  1270				case 2:		/* ptesync */
  1271					op->type = BARRIER + BARRIER_PTESYNC;
  1272					break;
  1273				}
  1274	#endif
  1275				return 1;
  1276	
  1277			case 854:	/* eieio */
  1278				op->type = BARRIER + BARRIER_EIEIO;
  1279				return 1;
  1280			}
  1281			break;
  1282		}
  1283	
  1284		/* Following cases refer to regs->gpr[], so we need all regs */
  1285		if (!FULL_REGS(regs))
  1286			return -1;
  1287	
  1288		rd = (instr >> 21) & 0x1f;
  1289		ra = (instr >> 16) & 0x1f;
  1290		rb = (instr >> 11) & 0x1f;
  1291		rc = (instr >> 6) & 0x1f;
  1292	
  1293		switch (opcode) {
  1294	#ifdef __powerpc64__
  1295		case 2:		/* tdi */
  1296			if (rd & trap_compare(regs->gpr[ra], (short) instr))
  1297				goto trap;
  1298			return 1;
  1299	#endif
  1300		case 3:		/* twi */
  1301			if (rd & trap_compare((int)regs->gpr[ra], (short) instr))
  1302				goto trap;
  1303			return 1;
  1304	
  1305	#ifdef __powerpc64__
  1306		case 4:
  1307			/*
  1308			 * There are very many instructions with this primary opcode
  1309			 * introduced in the ISA as early as v2.03. However, the ones
  1310			 * we currently emulate were all introduced with ISA 3.0
  1311			 */
  1312			if (!cpu_has_feature(CPU_FTR_ARCH_300))
  1313				return -1;
  1314	
  1315			switch (instr & 0x3f) {
  1316			case 48:	/* maddhd */
  1317				asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
  1318					     "=r" (op->val) : "r" (regs->gpr[ra]),
  1319					     "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
  1320				goto compute_done;
  1321	
  1322			case 49:	/* maddhdu */
  1323				asm volatile(PPC_MADDHDU(%0, %1, %2, %3) :
  1324					     "=r" (op->val) : "r" (regs->gpr[ra]),
  1325					     "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
  1326				goto compute_done;
  1327	
  1328			case 51:	/* maddld */
  1329				asm volatile(PPC_MADDLD(%0, %1, %2, %3) :
  1330					     "=r" (op->val) : "r" (regs->gpr[ra]),
  1331					     "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
  1332				goto compute_done;
  1333			}
  1334	
  1335			/*
  1336			 * There are other instructions from ISA 3.0 with the same
  1337			 * primary opcode which do not have emulation support yet.
  1338			 */
> 1339			goto unknown_opcode;
  1340	#endif
  1341	
  1342		case 7:		/* mulli */
  1343			op->val = regs->gpr[ra] * (short) instr;
  1344			goto compute_done;
  1345	
  1346		case 8:		/* subfic */
  1347			imm = (short) instr;
  1348			add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
  1349			return 1;
  1350	
  1351		case 10:	/* cmpli */
  1352			imm = (unsigned short) instr;
  1353			val = regs->gpr[ra];
  1354	#ifdef __powerpc64__
  1355			if ((rd & 1) == 0)
  1356				val = (unsigned int) val;
  1357	#endif
  1358			do_cmp_unsigned(regs, op, val, imm, rd >> 2);
  1359			return 1;
  1360	
  1361		case 11:	/* cmpi */
  1362			imm = (short) instr;
  1363			val = regs->gpr[ra];
  1364	#ifdef __powerpc64__
  1365			if ((rd & 1) == 0)
  1366				val = (int) val;
  1367	#endif
  1368			do_cmp_signed(regs, op, val, imm, rd >> 2);
  1369			return 1;
  1370	
  1371		case 12:	/* addic */
  1372			imm = (short) instr;
  1373			add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
  1374			return 1;
  1375	
  1376		case 13:	/* addic. */
  1377			imm = (short) instr;
  1378			add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
  1379			set_cr0(regs, op);
  1380			return 1;
  1381	
  1382		case 14:	/* addi */
  1383			imm = (short) instr;
  1384			if (ra)
  1385				imm += regs->gpr[ra];
  1386			op->val = imm;
  1387			goto compute_done;
  1388	
  1389		case 15:	/* addis */
  1390			imm = ((short) instr) << 16;
  1391			if (ra)
  1392				imm += regs->gpr[ra];
  1393			op->val = imm;
  1394			goto compute_done;
  1395	
  1396		case 19:
  1397			if (((instr >> 1) & 0x1f) == 2) {
  1398				/* addpcis */
  1399				imm = (short) (instr & 0xffc1);	/* d0 + d2 fields */
  1400				imm |= (instr >> 15) & 0x3e;	/* d1 field */
  1401				op->val = regs->nip + (imm << 16) + 4;
  1402				goto compute_done;
  1403			}
  1404			op->type = UNKNOWN;
  1405			return 0;
  1406	
  1407		case 20:	/* rlwimi */
  1408			mb = (instr >> 6) & 0x1f;
  1409			me = (instr >> 1) & 0x1f;
  1410			val = DATA32(regs->gpr[rd]);
  1411			imm = MASK32(mb, me);
  1412			op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
  1413			goto logical_done;
  1414	
  1415		case 21:	/* rlwinm */
  1416			mb = (instr >> 6) & 0x1f;
  1417			me = (instr >> 1) & 0x1f;
  1418			val = DATA32(regs->gpr[rd]);
  1419			op->val = ROTATE(val, rb) & MASK32(mb, me);
  1420			goto logical_done;
  1421	
  1422		case 23:	/* rlwnm */
  1423			mb = (instr >> 6) & 0x1f;
  1424			me = (instr >> 1) & 0x1f;
  1425			rb = regs->gpr[rb] & 0x1f;
  1426			val = DATA32(regs->gpr[rd]);
  1427			op->val = ROTATE(val, rb) & MASK32(mb, me);
  1428			goto logical_done;
  1429	
  1430		case 24:	/* ori */
  1431			op->val = regs->gpr[rd] | (unsigned short) instr;
  1432			goto logical_done_nocc;
  1433	
  1434		case 25:	/* oris */
  1435			imm = (unsigned short) instr;
  1436			op->val = regs->gpr[rd] | (imm << 16);
  1437			goto logical_done_nocc;
  1438	
  1439		case 26:	/* xori */
  1440			op->val = regs->gpr[rd] ^ (unsigned short) instr;
  1441			goto logical_done_nocc;
  1442	
  1443		case 27:	/* xoris */
  1444			imm = (unsigned short) instr;
  1445			op->val = regs->gpr[rd] ^ (imm << 16);
  1446			goto logical_done_nocc;
  1447	
  1448		case 28:	/* andi. */
  1449			op->val = regs->gpr[rd] & (unsigned short) instr;
  1450			set_cr0(regs, op);
  1451			goto logical_done_nocc;
  1452	
  1453		case 29:	/* andis. */
  1454			imm = (unsigned short) instr;
  1455			op->val = regs->gpr[rd] & (imm << 16);
  1456			set_cr0(regs, op);
  1457			goto logical_done_nocc;
  1458	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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2021-03-01  6:24 [sashal-linux-stable:queue-5.4 166/234] arch/powerpc/lib/sstep.c:1339:3: error: label 'unknown_opcode' used but not defined kernel test robot

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