From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vladimir Oltean Date: Tue, 16 Mar 2021 12:20:50 +0200 Subject: [PATCH] pci: layerscape: Change to allocate zeroed memery for struct ls_pcie In-Reply-To: <20210311073051.1548-1-Zhiqiang.Hou@nxp.com> References: <20210311073051.1548-1-Zhiqiang.Hou@nxp.com> Message-ID: <20210316102050.jsiu2fxvm4sdi7f6@skbuf> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thu, Mar 11, 2021 at 03:30:51PM +0800, Zhiqiang Hou wrote: > From: Hou Zhiqiang > > As on some incipient Layerscape platforms (LS1043A series) there isn't > separate PF control register block, these registers reside in the LUT > register block, so when the driver detected there isn't 'ctrl', it will > assign the 'lut' address to the ls_pcie->ctrl. > > The current code allocate memory for the struct ls_pcie with random > contents, this can result in skipping to assign the ls_pcie->ctrl with > the 'lut' address, then further crash with the incorrect address. > > Fixes: 118e58e26eba ("pci: layerscape: Split the EP and RC driver") > Signed-off-by: Hou Zhiqiang > --- Reviewed-by: Vladimir Oltean