From: "Cédric Le Goater" <clg@kaod.org>
To: linuxppc-dev@lists.ozlabs.org
Cc: "Cédric Le Goater" <clg@kaod.org>,
"Alexey Kardashevskiy" <aik@ozlabs.ru>
Subject: [PATCH 29/31] powerpc/powernv/pci: Rework pnv_opal_pci_msi_eoi()
Date: Fri, 30 Apr 2021 10:04:05 +0200 [thread overview]
Message-ID: <20210430080407.4030767-30-clg@kaod.org> (raw)
In-Reply-To: <20210430080407.4030767-1-clg@kaod.org>
pnv_opal_pci_msi_eoi() is called from KVM to EOI passthrough interrupts
when in real mode. Adding MSI domain broke the hack using the
'ioda.irq_chip' field to deduce the owning PHB. Fix that by using the
IRQ chip data in the MSI domain.
The 'ioda.irq_chip' field is now unused and could be removed from the
pnv_phb struct.
Cc: Paul Mackerras <paulus@ozlabs.org>
Cc: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/powerpc/include/asm/pnv-pci.h | 2 +-
arch/powerpc/kvm/book3s_hv_rm_xics.c | 8 ++++----
arch/powerpc/platforms/powernv/pci-ioda.c | 17 +++++++++++++----
3 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/include/asm/pnv-pci.h b/arch/powerpc/include/asm/pnv-pci.h
index d0ee0ede5767..b3f480799352 100644
--- a/arch/powerpc/include/asm/pnv-pci.h
+++ b/arch/powerpc/include/asm/pnv-pci.h
@@ -33,7 +33,7 @@ int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num);
void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num);
int pnv_cxl_get_irq_count(struct pci_dev *dev);
struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev);
-int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq);
+int64_t pnv_opal_pci_msi_eoi(struct irq_data *d);
bool is_pnv_opal_msi(struct irq_chip *chip);
#ifdef CONFIG_CXL_BASE
diff --git a/arch/powerpc/kvm/book3s_hv_rm_xics.c b/arch/powerpc/kvm/book3s_hv_rm_xics.c
index c2c9c733f359..1772d53526e2 100644
--- a/arch/powerpc/kvm/book3s_hv_rm_xics.c
+++ b/arch/powerpc/kvm/book3s_hv_rm_xics.c
@@ -713,6 +713,7 @@ static int ics_rm_eoi(struct kvm_vcpu *vcpu, u32 irq)
icp->rm_eoied_irq = irq;
}
+ /* Handle passthrough interrupts */
if (state->host_irq) {
++vcpu->stat.pthru_all;
if (state->intr_cpu != -1) {
@@ -766,7 +767,7 @@ int xics_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
static unsigned long eoi_rc;
-static void icp_eoi(struct irq_chip *c, u32 hwirq, __be32 xirr, bool *again)
+static void icp_eoi(struct irq_data *d, u32 hwirq, __be32 xirr, bool *again)
{
void __iomem *xics_phys;
int64_t rc;
@@ -779,7 +780,7 @@ static void icp_eoi(struct irq_chip *c, u32 hwirq, __be32 xirr, bool *again)
return;
}
- rc = pnv_opal_pci_msi_eoi(c, hwirq);
+ rc = pnv_opal_pci_msi_eoi(d);
if (rc)
eoi_rc = rc;
@@ -887,8 +888,7 @@ long kvmppc_deliver_irq_passthru(struct kvm_vcpu *vcpu,
icp_rm_deliver_irq(xics, icp, irq, false);
/* EOI the interrupt */
- icp_eoi(irq_desc_get_chip(irq_map->desc), irq_map->r_hwirq, xirr,
- again);
+ icp_eoi(irq_desc_get_irq_data(irq_map->desc), irq_map->r_hwirq, xirr, again);
if (check_too_hard(xics, icp) == H_TOO_HARD)
return 2;
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index d496d5b1b45a..8406b94cbfca 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -2107,12 +2107,21 @@ void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
pe->dma_setup_done = true;
}
-int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
+/*
+ * Called from KVM in real mode to EOI passthru interrupts. The ICP
+ * EOI is handled directly in KVM in kvmppc_deliver_irq_passthru().
+ *
+ * The IRQ data is mapped in the PCI-MSI domain and the EOI OPAL call
+ * needs an HW IRQ number mapped in the XICS IRQ domain. The HW IRQ
+ * numbers of the in-the-middle MSI domain are vector numbers and it's
+ * good enough for OPAL. Use that.
+ */
+int64_t pnv_opal_pci_msi_eoi(struct irq_data *d)
{
- struct pnv_phb *phb = container_of(chip, struct pnv_phb,
- ioda.irq_chip);
+ struct pci_controller *hose = irq_data_get_irq_chip_data(d->parent_data);
+ struct pnv_phb *phb = hose->private_data;
- return opal_pci_msi_eoi(phb->opal_id, hw_irq);
+ return opal_pci_msi_eoi(phb->opal_id, d->parent_data->hwirq);
}
/*
--
2.26.3
next prev parent reply other threads:[~2021-04-30 8:14 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-30 8:03 [PATCH 00/31] powerpc: Modernize the PCI/MSI support Cédric Le Goater
2021-04-30 8:03 ` [PATCH 01/31] powerpc/pseries/pci: Introduce __find_pe_total_msi() Cédric Le Goater
2021-04-30 8:03 ` [PATCH 02/31] powerpc/pseries/pci: Introduce rtas_prepare_msi_irqs() Cédric Le Goater
2021-04-30 8:03 ` [PATCH 03/31] powerpc/xive: Add support for IRQ domain hierarchy Cédric Le Goater
2021-04-30 8:03 ` [PATCH 04/31] powerpc/xive: Ease debugging of xive_irq_set_affinity() Cédric Le Goater
2021-04-30 8:03 ` [PATCH 05/31] powerpc/pseries/pci: Add MSI domains Cédric Le Goater
2021-04-30 8:03 ` [PATCH 06/31] powerpc/xive: Drop unmask of MSIs at startup Cédric Le Goater
2021-04-30 8:03 ` [PATCH 07/31] powerpc/xive: Fix xive_irq_set_affinity for MSI Cédric Le Goater
2021-05-14 20:48 ` Thomas Gleixner
2021-05-20 17:25 ` Cédric Le Goater
2021-04-30 8:03 ` [PATCH 08/31] powerpc/pseries/pci: Add a domain_free_irqs handler Cédric Le Goater
2021-04-30 8:03 ` [PATCH 09/31] powerpc/pseries/pci: Add a msi_free() handler to clear XIVE data Cédric Le Goater
2021-05-20 12:33 ` Cédric Le Goater
2021-04-30 8:03 ` [PATCH 10/31] powerpc/pseries/pci: Add support of MSI domains to PHB hotplug Cédric Le Goater
2021-04-30 8:03 ` [PATCH 11/31] powerpc/powernv/pci: Introduce __pnv_pci_ioda_msi_setup() Cédric Le Goater
2021-04-30 8:03 ` [PATCH 12/31] powerpc/powernv/pci: Add MSI domains Cédric Le Goater
2021-04-30 8:03 ` [PATCH 13/31] KVM: PPC: Book3S HV: Use the new IRQ chip to detect passthrough interrupts Cédric Le Goater
2021-04-30 8:03 ` [PATCH 14/31] KVM: PPC: Book3S HV: XIVE: Change interface of passthrough interrupt routines Cédric Le Goater
2021-04-30 8:03 ` [PATCH 15/31] KVM: PPC: Book3S HV: XIVE: Fix mapping of passthrough interrupts Cédric Le Goater
2021-05-14 20:51 ` Thomas Gleixner
2021-05-15 10:40 ` Marc Zyngier
2021-05-20 12:09 ` Cédric Le Goater
2021-04-30 8:03 ` [PATCH 16/31] powerpc/xics: Remove ICS list Cédric Le Goater
2021-04-30 8:03 ` [PATCH 17/31] powerpc/xics: Rename the map handler in a check handler Cédric Le Goater
2021-04-30 8:03 ` [PATCH 18/31] powerpc/xics: Give a name to the default XICS IRQ domain Cédric Le Goater
2021-04-30 8:03 ` [PATCH 19/31] powerpc/xics: Add debug logging to the set_irq_affinity handlers Cédric Le Goater
2021-04-30 8:03 ` [PATCH 20/31] powerpc/xics: Add support for IRQ domain hierarchy Cédric Le Goater
2021-04-30 8:03 ` [PATCH 21/31] powerpc/powernv/pci: Customize the MSI EOI handler to support PHB3 Cédric Le Goater
2021-04-30 8:03 ` [PATCH 22/31] powerpc/pci: Drop XIVE restriction on MSI domains Cédric Le Goater
2021-04-30 8:03 ` [PATCH 23/31] powerpc/xics: Drop unmask of MSIs at startup Cédric Le Goater
2021-04-30 8:04 ` [PATCH 24/31] powerpc/pseries/pci: Drop unused MSI code Cédric Le Goater
2021-04-30 8:04 ` [PATCH 25/31] powerpc/powernv/pci: " Cédric Le Goater
2021-04-30 8:04 ` [PATCH 26/31] powerpc/powernv/pci: Adapt is_pnv_opal_msi() to detect passthrough interrupt Cédric Le Goater
2021-04-30 8:04 ` [PATCH 27/31] powerpc/xics: Fix IRQ migration Cédric Le Goater
2021-04-30 8:04 ` [PATCH 28/31] powerpc/powernv/pci: Set the IRQ chip data for P8/CXL devices Cédric Le Goater
2021-04-30 8:04 ` Cédric Le Goater [this message]
2021-04-30 8:04 ` [PATCH 30/31] KVM: PPC: Book3S HV: XICS: Fix mapping of passthrough interrupts Cédric Le Goater
2021-04-30 8:04 ` [PATCH 31/31] genirq: Improve "hwirq" output in /proc and /sys/ Cédric Le Goater
2021-05-14 20:49 ` Thomas Gleixner
2021-05-20 12:27 ` Cédric Le Goater
2021-05-20 12:57 ` Thomas Gleixner
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