From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11C11C433ED for ; Thu, 13 May 2021 15:08:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E0DF4610F7 for ; Thu, 13 May 2021 15:08:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233598AbhEMPJj (ORCPT ); Thu, 13 May 2021 11:09:39 -0400 Received: from mga18.intel.com ([134.134.136.126]:64242 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232156AbhEMPJf (ORCPT ); Thu, 13 May 2021 11:09:35 -0400 IronPort-SDR: 2MkuJgSUn0Vaf3qug1rS09q0Ou+mVTTeMCEK8tRbAV/TRx08MYDHnLF5uyDSFhKlOVgwwVRSbV 7RWWhbLNBhpA== X-IronPort-AV: E=McAfee;i="6200,9189,9982"; a="187382670" X-IronPort-AV: E=Sophos;i="5.82,296,1613462400"; d="scan'208";a="187382670" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2021 08:08:24 -0700 IronPort-SDR: h8cnr1lRgYszrkpIKJZgTT5deHWSNW4DKLnW4hv/nIRhPifQYiZdb19NeQKFI2GUvfxErDsCe7 cGsYelF/g5Lg== X-IronPort-AV: E=Sophos;i="5.82,296,1613462400"; d="scan'208";a="409665304" Received: from jacob-builder.jf.intel.com (HELO jacob-builder) ([10.7.199.155]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2021 08:08:24 -0700 Date: Thu, 13 May 2021 08:10:50 -0700 From: Jacob Pan To: Jason Gunthorpe Cc: Christoph Hellwig , LKML , iommu@lists.linux-foundation.org, Joerg Roedel , Lu Baolu , Jean-Philippe Brucker , Yi Liu , Raj Ashok , "Tian, Kevin" , Dave Jiang , wangzhou1@hisilicon.com, zhangfei.gao@linaro.org, vkoul@kernel.org, David Woodhouse , "Luck, Tony" , jacob.jun.pan@linux.intel.com Subject: Re: [PATCH v4 1/2] iommu/sva: Tighten SVA bind API with explicit flags Message-ID: <20210513081050.5cf6a6ed@jacob-builder> In-Reply-To: <20210513133834.GC1002214@nvidia.com> References: <1620653108-44901-2-git-send-email-jacob.jun.pan@linux.intel.com> <20210510233749.GG1002214@nvidia.com> <20210510203145.086835cc@jacob-builder> <20210511114848.GK1002214@nvidia.com> <20210511091452.721e9a03@jacob-builder> <20210511163521.GN1002214@nvidia.com> <20210511110550.477a434f@jacob-builder> <20210511194726.GP1002214@nvidia.com> <20210513060012.0fcc7653@jacob-builder> <20210513133834.GC1002214@nvidia.com> Organization: OTC X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jason, On Thu, 13 May 2021 10:38:34 -0300, Jason Gunthorpe wrote: > On Thu, May 13, 2021 at 06:00:12AM -0700, Jacob Pan wrote: > > > > If you want to do SVA PASID then it also must come with DMA APIs to > > > > manage the CPU cache coherence that are all NOP's on x86. > > > > > > Yes. And we have plenty of precende where an IOMMU is in "bypass" > > > mode to allow access to all memory and then uses the simple > > > dma-direct case. > > I agree it is better not to expose the entire direct map. But the > > missing piece of using DMA APIs is the PASID. The caller needs the > > PASID value to do work submission once buffer is mapped. > > You still haven't explained why the kernel driver should have a PASID at > all. > For shared workqueue, it can only generate DMA request with PASID. The submission is done by ENQCMDS (S for supervisor) instruction. If we were not to share page tables with init_mm, we need a system PASID that doing the same direct mapping in IOMMU page tables. > Jason Thanks, Jacob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 120DDC433B4 for ; Thu, 13 May 2021 15:08:32 +0000 (UTC) Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 92183613BF for ; Thu, 13 May 2021 15:08:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 92183613BF Authentication-Results: mail.kernel.org; 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d="scan'208";a="409665304" Received: from jacob-builder.jf.intel.com (HELO jacob-builder) ([10.7.199.155]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2021 08:08:24 -0700 Date: Thu, 13 May 2021 08:10:50 -0700 From: Jacob Pan To: Jason Gunthorpe Subject: Re: [PATCH v4 1/2] iommu/sva: Tighten SVA bind API with explicit flags Message-ID: <20210513081050.5cf6a6ed@jacob-builder> In-Reply-To: <20210513133834.GC1002214@nvidia.com> References: <1620653108-44901-2-git-send-email-jacob.jun.pan@linux.intel.com> <20210510233749.GG1002214@nvidia.com> <20210510203145.086835cc@jacob-builder> <20210511114848.GK1002214@nvidia.com> <20210511091452.721e9a03@jacob-builder> <20210511163521.GN1002214@nvidia.com> <20210511110550.477a434f@jacob-builder> <20210511194726.GP1002214@nvidia.com> <20210513060012.0fcc7653@jacob-builder> <20210513133834.GC1002214@nvidia.com> Organization: OTC X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Cc: vkoul@kernel.org, "Tian, Kevin" , Dave Jiang , Raj Ashok , David Woodhouse , LKML , Christoph Hellwig , iommu@lists.linux-foundation.org, "Luck, Tony" , zhangfei.gao@linaro.org, Jean-Philippe Brucker X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Hi Jason, On Thu, 13 May 2021 10:38:34 -0300, Jason Gunthorpe wrote: > On Thu, May 13, 2021 at 06:00:12AM -0700, Jacob Pan wrote: > > > > If you want to do SVA PASID then it also must come with DMA APIs to > > > > manage the CPU cache coherence that are all NOP's on x86. > > > > > > Yes. And we have plenty of precende where an IOMMU is in "bypass" > > > mode to allow access to all memory and then uses the simple > > > dma-direct case. > > I agree it is better not to expose the entire direct map. But the > > missing piece of using DMA APIs is the PASID. The caller needs the > > PASID value to do work submission once buffer is mapped. > > You still haven't explained why the kernel driver should have a PASID at > all. > For shared workqueue, it can only generate DMA request with PASID. The submission is done by ENQCMDS (S for supervisor) instruction. If we were not to share page tables with init_mm, we need a system PASID that doing the same direct mapping in IOMMU page tables. > Jason Thanks, Jacob _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu