From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F19B8C43460 for ; Wed, 19 May 2021 06:44:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C432B61042 for ; Wed, 19 May 2021 06:44:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237662AbhESGp6 (ORCPT ); Wed, 19 May 2021 02:45:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237325AbhESGp5 (ORCPT ); Wed, 19 May 2021 02:45:57 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BC79C06175F for ; Tue, 18 May 2021 23:44:38 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id s4so4897629plg.12 for ; Tue, 18 May 2021 23:44:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=beagleboard-org.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=crJApTk0fR8CS3cRDbB3V67gscNvYMiJEHMFrBZfWUo=; b=zDGZZs/er8Q9IuA9Imgu2QK64TdNwRQPa6zLFs3OWErIjQOBeBTCV7kAFI8XkEVKBr 7bimA/liFg+A8v/bCayXSehaSTT0F7V13I/Q44TYvfDL10K/hpHYxVbbzgQSr9Ocp1KW OjhyTVZqfbu6yFKgiafgqAFXyy8hw1jzKdN/Qpnb81hAz+pcdvz1+YxUEqVBvhNjLBfp uZPrxYwQiNSc0Udlc4+QVfWruZN81uje9iEir53nWlq/lfHmC7bWlKHsBxeRdqXjIVFp LnRvKqglalyIDwsrVoT/VOk+EEY/tiruqS+80tcJK3sSdDz0WMgb/5lbceYP6Gsiljpb Ycgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=crJApTk0fR8CS3cRDbB3V67gscNvYMiJEHMFrBZfWUo=; b=KWoaFo3ahb4rlX6W/sr7dYzhjWxdNNeQS17LkQHLpdQ88d1AL68AvreayvnDOm66uS eC7a6Jnr0AcjFOMkuzDmErFrsWkcY8G+6V6uBGTdg1bxjkWoGD96A+rE1xfgbmQhKJXl SoOuKYwPVLIdFie8I1vjkQOScHEvTIA49b6Suon3AJKLXn2H4AZKU5oK3GQtghK/7o0z d6amgAVrMD1hDoTUDGZYDyJvM4fVsQHOx01zkItwMapGatxF/WUySum1F7X2kw5woAfq ENNGl61gLsBZujNLB1fZAelk+QD+teWNWja/UJ4ojz0aFFJZv9YEhYN6jVQyX6G4hXlY MFDA== X-Gm-Message-State: AOAM533J1WcHLcnKD2ST2uXSir6tnP/g65b3nNMGBFa+fBjATqwI+3fT kdeNKe/kzlkI5zVQjmYqr1REsg== X-Google-Smtp-Source: ABdhPJy9tsWxCDo/o3R7ta1owz+e2PxTX//mYRmicr9Nz+qbfH9zpmvYaQDcpfama4JkK8fiYfECwQ== X-Received: by 2002:a17:902:e8cb:b029:ee:f963:4fd8 with SMTP id v11-20020a170902e8cbb02900eef9634fd8mr9185136plg.40.1621406677878; Tue, 18 May 2021 23:44:37 -0700 (PDT) Received: from x1 ([2601:1c0:4701:ae70:9384:8c4b:dc2b:c4d0]) by smtp.gmail.com with ESMTPSA id v14sm8823848pfi.25.2021.05.18.23.44.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 May 2021 23:44:37 -0700 (PDT) Date: Tue, 18 May 2021 23:44:35 -0700 From: Drew Fustini To: Guo Ren Cc: Christoph Hellwig , Anup Patel , Palmer Dabbelt , wefu@redhat.com, lazyparser@gmail.com, linux-riscv , Linux Kernel Mailing List , linux-arch , linux-sunxi@lists.linux.dev, Guo Ren , paul.walmsley@sifive.com, Nick Kossifidis , Benjamin Koch , Matteo Croce , Wei Fu Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support Message-ID: <20210519064435.GA3076809@x1> References: <1621400656-25678-1-git-send-email-guoren@kernel.org> <20210519052048.GA24853@lst.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 19, 2021 at 01:48:23PM +0800, Guo Ren wrote: > On Wed, May 19, 2021 at 1:20 PM Christoph Hellwig wrote: > > > > On Wed, May 19, 2021 at 05:04:13AM +0000, guoren@kernel.org wrote: > > > From: Guo Ren > > > > > > The RISC-V ISA doesn't yet specify how to query or modify PMAs, so let > > > vendors define the custom properties of memory regions in PTE. > > > > Err, hell no. The ISA needs to gets this fixed first. Then we can > > talk about alternatives patching things in or trapping in the SBI. > > But if the RISC-V ISA can't get these basic done after years we can't > > support it in Linux at all. > > The patchset just leaves a configuration chance for vendors. Before > RISC-V ISA fixes it, we should give the chance to let vendor solve > their real chip issues. This patch series looks like it might be useful for the StarFive JH7100 [1] [2] too as it has peripherals on a non-coherent interconnect. GMAC, USB and SDIO require that the L2 cache must be manually flushed after DMA operations if the data is intended to be shared with U74 cores [2]. There is the RISC-V Cache Management Operation, or CMO, task group [3] but I am not sure if that can help the SoC's that have already been fabbed like the the D1 and the JH7100. thanks, drew [1] https://github.com/starfive-tech/beaglev_doc/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf [2] https://github.com/starfive-tech/beaglev_doc/blob/main/JH7100%20Cache%20Coherence%20V1.0.pdf [3] https://github.com/riscv/riscv-CMOs From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D687FC433ED for ; Wed, 19 May 2021 06:45:27 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5992861042 for ; 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Tue, 18 May 2021 23:44:37 -0700 (PDT) Date: Tue, 18 May 2021 23:44:35 -0700 From: Drew Fustini To: Guo Ren Cc: Christoph Hellwig , Anup Patel , Palmer Dabbelt , wefu@redhat.com, lazyparser@gmail.com, linux-riscv , Linux Kernel Mailing List , linux-arch , linux-sunxi@lists.linux.dev, Guo Ren , paul.walmsley@sifive.com, Nick Kossifidis , Benjamin Koch , Matteo Croce , Wei Fu Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support Message-ID: <20210519064435.GA3076809@x1> References: <1621400656-25678-1-git-send-email-guoren@kernel.org> <20210519052048.GA24853@lst.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210518_234439_672911_90DAB434 X-CRM114-Status: GOOD ( 18.74 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, May 19, 2021 at 01:48:23PM +0800, Guo Ren wrote: > On Wed, May 19, 2021 at 1:20 PM Christoph Hellwig wrote: > > > > On Wed, May 19, 2021 at 05:04:13AM +0000, guoren@kernel.org wrote: > > > From: Guo Ren > > > > > > The RISC-V ISA doesn't yet specify how to query or modify PMAs, so let > > > vendors define the custom properties of memory regions in PTE. > > > > Err, hell no. The ISA needs to gets this fixed first. Then we can > > talk about alternatives patching things in or trapping in the SBI. > > But if the RISC-V ISA can't get these basic done after years we can't > > support it in Linux at all. > > The patchset just leaves a configuration chance for vendors. Before > RISC-V ISA fixes it, we should give the chance to let vendor solve > their real chip issues. This patch series looks like it might be useful for the StarFive JH7100 [1] [2] too as it has peripherals on a non-coherent interconnect. GMAC, USB and SDIO require that the L2 cache must be manually flushed after DMA operations if the data is intended to be shared with U74 cores [2]. There is the RISC-V Cache Management Operation, or CMO, task group [3] but I am not sure if that can help the SoC's that have already been fabbed like the the D1 and the JH7100. thanks, drew [1] https://github.com/starfive-tech/beaglev_doc/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf [2] https://github.com/starfive-tech/beaglev_doc/blob/main/JH7100%20Cache%20Coherence%20V1.0.pdf [3] https://github.com/riscv/riscv-CMOs _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv