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Fri, 21 May 2021 15:24:48 +0000 From: Liam Howlett To: Aneesh Kumar K.V CC: Linus Torvalds , Linux-MM , Andrew Morton , Michael Ellerman , linuxppc-dev , Kalesh Singh , Nick Piggin , Joel Fernandes , Christophe Leroy Subject: Re: [PATCH v5 7/9] mm/mremap: Move TLB flush outside page table lock Thread-Topic: [PATCH v5 7/9] mm/mremap: Move TLB flush outside page table lock Thread-Index: AQHXNzqwwBFKlf59HEyEUKG3dm/IRarsqneAgAAZiACAAKLsgIAABlIAgAA1JgCAAG78gIAAKwgA Date: Fri, 21 May 2021 15:24:48 +0000 Message-ID: <20210521152438.jczhe6nxnz5woxpl@revolver> References: <20210422054323.150993-1-aneesh.kumar@linux.ibm.com> <20210422054323.150993-8-aneesh.kumar@linux.ibm.com> <2eafd7df-65fd-1e2c-90b6-d143557a1fdc@linux.ibm.com> <5ea8fa4f-a5a2-7dc4-7958-23df6a2c1f3a@linux.ibm.com> In-Reply-To: <5ea8fa4f-a5a2-7dc4-7958-23df6a2c1f3a@linux.ibm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [23.233.25.87] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 80858931-73ac-48c0-d2f7-08d91c6c9286 x-ms-traffictypediagnostic: MWHPR1001MB2335: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:1091; 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dkim=pass header.d=oracle.com header.s=corp-2020-01-29 header.b=JWMnQM7j; dkim=pass header.d=oracle.onmicrosoft.com header.s=selector2-oracle-onmicrosoft-com header.b=TiXDp0HC; dmarc=pass (policy=none) header.from=oracle.com; spf=none (imf30.hostedemail.com: domain of liam.howlett@oracle.com has no SPF policy when checking 205.220.165.32) smtp.mailfrom=liam.howlett@oracle.com X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: D498CE0001AF X-Stat-Signature: zcbn4ehjazfi4rf88d7ged6dwstx83sc X-HE-Tag: 1621610704-876984 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: * Aneesh Kumar K.V [210521 08:51]: > On 5/21/21 11:43 AM, Linus Torvalds wrote: > > On Thu, May 20, 2021 at 5:03 PM Aneesh Kumar K.V > > wrote: > > >=20 > > > On 5/21/21 8:10 AM, Linus Torvalds wrote: > > > >=20 > > > > So mremap does need to flush the TLB before releasing the page tabl= e > > > > lock, because that's the lifetime boundary for the page that got > > > > moved. > > >=20 > > > How will we avoid that happening with > > > c49dd340180260c6239e453263a9a244da9a7c85 / > > > 2c91bd4a4e2e530582d6fd643ea7b86b27907151 . The commit improves mremap > > > performance by moving level3/level2 page table entries. When doing so= we > > > are not holding level 4 ptl lock (pte_lock()). But rather we are hold= ing > > > pmd_lock or pud_lock(). So if we move pages around without holding th= e > > > pte lock, won't the above issue happen even if we do a tlb flush with > > > holding pmd lock/pud lock? > >=20 > > Hmm. Interesting. > >=20 > > Your patch (to flush the TLB after clearing the old location, and > > before inserting it into the new one) looks like an "obvious" fix. > >=20 > > But I'm putting that "obvious" in quotes, because I'm now wondering if > > it actually fixes anything. > >=20 > > Lookie here: > >=20 > > - CPU1 does a mremap of a pmd or pud. > >=20 > > It clears the old pmd/pud, flushes the old TLB range, and then > > inserts the pmd/pud at the new location. > >=20 > > - CPU2 does a page shrinker, which calls try_to_unmap, which calls > > try_to_unmap_one. > >=20 > > These are entirely asynchronous, because they have no shared lock. The > > mremap uses the pmd lock, the try_to_unmap_one() does the rmap walk, > > which does the pte lock. > >=20 > > Now, imagine that the following ordering happens with the two > > operations above, and a CPU3 that does accesses: > >=20 > > - CPU2 follows (and sees) the old page tables in the old location and > > the took the pte lock > >=20 > > - the mremap on CPU1 starts - cleared the old pmd, flushed the tlb, > > *and* inserts in the new place. > >=20 > > - a user thread on CPU3 accesses the new location and fills the TLB > > of the *new* address mremap holds the mmap_sem in write mode as well, doesn't it? How is the us= er thread getting the new location? > >=20 > > - only now does CPU2 get to the "pte_get_and_clear()" to remove one p= age > >=20 > > - CPU2 does a TLB flush and frees the page > >=20 > > End result: > >=20 > > - both CPU1 _and_ CPU2 have flushed the TLB. > >=20 > > - but both flushed the *OLD* address > >=20 > > - the page is freed > >=20 > > - CPU3 still has the stale TLB entry pointing to the page that is now > > free and might be reused for something else > >=20 > > Am I missing something? > >=20 >=20 > That is a problem. With that it looks like CONFIG_HAVE_MOVE_PMD/PUD is > broken? I don't see an easy way to fix this? >=20 > -aneesh >=20 > = From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, PDS_BAD_THREAD_QP_64,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EE90C47076 for ; Fri, 21 May 2021 15:49:36 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AA7AC61405 for ; Fri, 21 May 2021 15:49:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AA7AC61405 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=oracle.com Authentication-Results: mail.kernel.org; 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Fri, 21 May 2021 15:24:48 +0000 From: Liam Howlett To: Aneesh Kumar K.V Subject: Re: [PATCH v5 7/9] mm/mremap: Move TLB flush outside page table lock Thread-Topic: [PATCH v5 7/9] mm/mremap: Move TLB flush outside page table lock Thread-Index: AQHXNzqwwBFKlf59HEyEUKG3dm/IRarsqneAgAAZiACAAKLsgIAABlIAgAA1JgCAAG78gIAAKwgA Date: Fri, 21 May 2021 15:24:48 +0000 Message-ID: <20210521152438.jczhe6nxnz5woxpl@revolver> References: <20210422054323.150993-1-aneesh.kumar@linux.ibm.com> <20210422054323.150993-8-aneesh.kumar@linux.ibm.com> <2eafd7df-65fd-1e2c-90b6-d143557a1fdc@linux.ibm.com> <5ea8fa4f-a5a2-7dc4-7958-23df6a2c1f3a@linux.ibm.com> In-Reply-To: <5ea8fa4f-a5a2-7dc4-7958-23df6a2c1f3a@linux.ibm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: linux.ibm.com; dkim=none (message not signed) header.d=none;linux.ibm.com; dmarc=none action=none header.from=oracle.com; x-originating-ip: [23.233.25.87] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 80858931-73ac-48c0-d2f7-08d91c6c9286 x-ms-traffictypediagnostic: MWHPR1001MB2335: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:1091; 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charset="us-ascii" Content-ID: <85DEDF2B36278E4FAC53C94D972B646C@namprd10.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: oracle.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MWHPR10MB1582.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 80858931-73ac-48c0-d2f7-08d91c6c9286 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 May 2021 15:24:48.7901 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 4e2c6054-71cb-48f1-bd6c-3a9705aca71b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: hWCA24rMs6RLlaz42gOeysVPbu13cHuLOnlbTrAi5SsP4gT3wX6HBFVORUabIpbxTLKX1bjenIRgmu1wNrAlNg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1001MB2335 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=9990 signatures=668683 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 spamscore=0 bulkscore=0 suspectscore=0 mlxlogscore=999 adultscore=0 malwarescore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2105210083 X-Proofpoint-GUID: 8eHr6EULBPK0NeHDWhLSNlptuwfhHg4V X-Proofpoint-ORIG-GUID: 8eHr6EULBPK0NeHDWhLSNlptuwfhHg4V X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev , Nick Piggin , Linux-MM , Kalesh Singh , Joel Fernandes , Andrew Morton , Linus Torvalds Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" * Aneesh Kumar K.V [210521 08:51]: > On 5/21/21 11:43 AM, Linus Torvalds wrote: > > On Thu, May 20, 2021 at 5:03 PM Aneesh Kumar K.V > > wrote: > > >=20 > > > On 5/21/21 8:10 AM, Linus Torvalds wrote: > > > >=20 > > > > So mremap does need to flush the TLB before releasing the page tabl= e > > > > lock, because that's the lifetime boundary for the page that got > > > > moved. > > >=20 > > > How will we avoid that happening with > > > c49dd340180260c6239e453263a9a244da9a7c85 / > > > 2c91bd4a4e2e530582d6fd643ea7b86b27907151 . The commit improves mremap > > > performance by moving level3/level2 page table entries. When doing so= we > > > are not holding level 4 ptl lock (pte_lock()). But rather we are hold= ing > > > pmd_lock or pud_lock(). So if we move pages around without holding th= e > > > pte lock, won't the above issue happen even if we do a tlb flush with > > > holding pmd lock/pud lock? > >=20 > > Hmm. Interesting. > >=20 > > Your patch (to flush the TLB after clearing the old location, and > > before inserting it into the new one) looks like an "obvious" fix. > >=20 > > But I'm putting that "obvious" in quotes, because I'm now wondering if > > it actually fixes anything. > >=20 > > Lookie here: > >=20 > > - CPU1 does a mremap of a pmd or pud. > >=20 > > It clears the old pmd/pud, flushes the old TLB range, and then > > inserts the pmd/pud at the new location. > >=20 > > - CPU2 does a page shrinker, which calls try_to_unmap, which calls > > try_to_unmap_one. > >=20 > > These are entirely asynchronous, because they have no shared lock. The > > mremap uses the pmd lock, the try_to_unmap_one() does the rmap walk, > > which does the pte lock. > >=20 > > Now, imagine that the following ordering happens with the two > > operations above, and a CPU3 that does accesses: > >=20 > > - CPU2 follows (and sees) the old page tables in the old location and > > the took the pte lock > >=20 > > - the mremap on CPU1 starts - cleared the old pmd, flushed the tlb, > > *and* inserts in the new place. > >=20 > > - a user thread on CPU3 accesses the new location and fills the TLB > > of the *new* address mremap holds the mmap_sem in write mode as well, doesn't it? How is the us= er thread getting the new location? > >=20 > > - only now does CPU2 get to the "pte_get_and_clear()" to remove one p= age > >=20 > > - CPU2 does a TLB flush and frees the page > >=20 > > End result: > >=20 > > - both CPU1 _and_ CPU2 have flushed the TLB. > >=20 > > - but both flushed the *OLD* address > >=20 > > - the page is freed > >=20 > > - CPU3 still has the stale TLB entry pointing to the page that is now > > free and might be reused for something else > >=20 > > Am I missing something? > >=20 >=20 > That is a problem. With that it looks like CONFIG_HAVE_MOVE_PMD/PUD is > broken? I don't see an easy way to fix this? >=20 > -aneesh >=20 > =