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Mon, 7 Jun 2021 08:12:18 -0400 (EDT) Date: Mon, 7 Jun 2021 14:12:16 +0200 From: Maxime Ripard To: Guo Ren Cc: Anup Patel , Palmer Dabbelt , Arnd Bergmann , Chen-Yu Tsai , Drew Fustini , liush@allwinnertech.com, Wei Wu =?utf-8?B?KOWQtOS8nyk=?= , wefu@redhat.com, linux-riscv , Linux Kernel Mailing List , linux-arch , linux-sunxi@lists.linux.dev, Guo Ren , Atish Patra , Christoph Hellwig Subject: Re: [RFC PATCH v2 10/11] riscv: soc: Add Allwinner SoC kconfig option Message-ID: <20210607121216.ypoehirsdypul3br@gilmour> References: <1622970249-50770-1-git-send-email-guoren@kernel.org> <1622970249-50770-14-git-send-email-guoren@kernel.org> <20210607071916.kwdbtafbqp3icgia@gilmour> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="secwxumdfbdnmyjv" Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --secwxumdfbdnmyjv Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Jun 07, 2021 at 03:43:03PM +0800, Guo Ren wrote: > On Mon, Jun 7, 2021 at 3:19 PM Maxime Ripard wrote: > > > > Hi, > > > > On Sun, Jun 06, 2021 at 09:04:08AM +0000, guoren@kernel.org wrote: > > > From: Guo Ren > > > > > > Add Allwinner kconfig option which selects SoC specific and common > > > drivers that is required for this SoC. > > > > > > Allwinner D1 uses custom PTE attributes to solve non-coherency SOC > > > interconnect issues for dma synchronization, so we set the default > > > value when SOC_SUNXI selected. > > > > > > Signed-off-by: Guo Ren > > > Co-Developed-by: Liu Shaohua > > > Signed-off-by: Liu Shaohua > > > Cc: Anup Patel > > > Cc: Atish Patra > > > Cc: Christoph Hellwig > > > Cc: Chen-Yu Tsai > > > Cc: Drew Fustini > > > Cc: Maxime Ripard > > > Cc: Palmer Dabbelt > > > Cc: Wei Fu > > > Cc: Wei Wu > > > --- > > > arch/riscv/Kconfig.socs | 12 ++++++++++++ > > > arch/riscv/configs/defconfig | 1 + > > > 2 files changed, 13 insertions(+) > > > > > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > > > index ed96376..055fb3e 100644 > > > --- a/arch/riscv/Kconfig.socs > > > +++ b/arch/riscv/Kconfig.socs > > > @@ -69,4 +69,16 @@ config SOC_CANAAN_K210_DTB_SOURCE > > > > > > endif > > > > > > +config SOC_SUNXI > > > + bool "Allwinner SoCs" > > > + depends on MMU > > > + select DWMAC_GENERIC > > > + select SERIAL_8250 > > > + select SERIAL_8250_CONSOLE > > > + select SERIAL_8250_DW > > > + select SIFIVE_PLIC > > > + select STMMAC_ETH > > > + help > > > + This enables support for Allwinner SoC platforms like the D1. > > > + > > > > We probably don't want to select DWMAC, STMMAC_ETH and the 8250 options, > > looks good otherwise. > > > > Maxime > Remove DWMAC, STMMAC_ETH is okay. >=20 > But I think we still need: > select SERIAL_8250_DW if SERIAL_8250 Well, even the UART is optional. Just enable them in the defconfig Maxime --secwxumdfbdnmyjv Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCYL4NIAAKCRDj7w1vZxhR xXytAP4mGdQrlps0ZkdQRDvgGoPmv63wCOgw7ukUbY9jEwIJGAEAwSHuyXFN1JP5 4ZeSdV0JY7fJXuRP01GiYXItu7FXhg8= =/iVS -----END PGP SIGNATURE----- --secwxumdfbdnmyjv-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 153F3C47094 for ; Mon, 7 Jun 2021 12:13:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C30DD610E7 for ; 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Mon, 7 Jun 2021 08:12:18 -0400 (EDT) Date: Mon, 7 Jun 2021 14:12:16 +0200 From: Maxime Ripard To: Guo Ren Cc: Anup Patel , Palmer Dabbelt , Arnd Bergmann , Chen-Yu Tsai , Drew Fustini , liush@allwinnertech.com, Wei Wu =?utf-8?B?KOWQtOS8nyk=?= , wefu@redhat.com, linux-riscv , Linux Kernel Mailing List , linux-arch , linux-sunxi@lists.linux.dev, Guo Ren , Atish Patra , Christoph Hellwig Subject: Re: [RFC PATCH v2 10/11] riscv: soc: Add Allwinner SoC kconfig option Message-ID: <20210607121216.ypoehirsdypul3br@gilmour> References: <1622970249-50770-1-git-send-email-guoren@kernel.org> <1622970249-50770-14-git-send-email-guoren@kernel.org> <20210607071916.kwdbtafbqp3icgia@gilmour> MIME-Version: 1.0 In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210607_051226_901887_4D79807F X-CRM114-Status: GOOD ( 25.66 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============4895260653554518800==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============4895260653554518800== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="secwxumdfbdnmyjv" Content-Disposition: inline --secwxumdfbdnmyjv Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Jun 07, 2021 at 03:43:03PM +0800, Guo Ren wrote: > On Mon, Jun 7, 2021 at 3:19 PM Maxime Ripard wrote: > > > > Hi, > > > > On Sun, Jun 06, 2021 at 09:04:08AM +0000, guoren@kernel.org wrote: > > > From: Guo Ren > > > > > > Add Allwinner kconfig option which selects SoC specific and common > > > drivers that is required for this SoC. > > > > > > Allwinner D1 uses custom PTE attributes to solve non-coherency SOC > > > interconnect issues for dma synchronization, so we set the default > > > value when SOC_SUNXI selected. > > > > > > Signed-off-by: Guo Ren > > > Co-Developed-by: Liu Shaohua > > > Signed-off-by: Liu Shaohua > > > Cc: Anup Patel > > > Cc: Atish Patra > > > Cc: Christoph Hellwig > > > Cc: Chen-Yu Tsai > > > Cc: Drew Fustini > > > Cc: Maxime Ripard > > > Cc: Palmer Dabbelt > > > Cc: Wei Fu > > > Cc: Wei Wu > > > --- > > > arch/riscv/Kconfig.socs | 12 ++++++++++++ > > > arch/riscv/configs/defconfig | 1 + > > > 2 files changed, 13 insertions(+) > > > > > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > > > index ed96376..055fb3e 100644 > > > --- a/arch/riscv/Kconfig.socs > > > +++ b/arch/riscv/Kconfig.socs > > > @@ -69,4 +69,16 @@ config SOC_CANAAN_K210_DTB_SOURCE > > > > > > endif > > > > > > +config SOC_SUNXI > > > + bool "Allwinner SoCs" > > > + depends on MMU > > > + select DWMAC_GENERIC > > > + select SERIAL_8250 > > > + select SERIAL_8250_CONSOLE > > > + select SERIAL_8250_DW > > > + select SIFIVE_PLIC > > > + select STMMAC_ETH > > > + help > > > + This enables support for Allwinner SoC platforms like the D1. > > > + > > > > We probably don't want to select DWMAC, STMMAC_ETH and the 8250 options, > > looks good otherwise. > > > > Maxime > Remove DWMAC, STMMAC_ETH is okay. >=20 > But I think we still need: > select SERIAL_8250_DW if SERIAL_8250 Well, even the UART is optional. Just enable them in the defconfig Maxime --secwxumdfbdnmyjv Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCYL4NIAAKCRDj7w1vZxhR xXytAP4mGdQrlps0ZkdQRDvgGoPmv63wCOgw7ukUbY9jEwIJGAEAwSHuyXFN1JP5 4ZeSdV0JY7fJXuRP01GiYXItu7FXhg8= =/iVS -----END PGP SIGNATURE----- --secwxumdfbdnmyjv-- --===============4895260653554518800== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============4895260653554518800==--