From: Biju Das <biju.das.jz@bp.renesas.com>
To: Rob Herring <robh+dt@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v2 4/8] arm64: dts: renesas: r9a07g044: Add SSI support
Date: Mon, 19 Jul 2021 14:40:36 +0100 [thread overview]
Message-ID: <20210719134040.7964-5-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20210719134040.7964-1-biju.das.jz@bp.renesas.com>
Add SSI{0,1,2,3} nodes to RZ/G2L SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* No change.
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 80 ++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 031238295be2..17bd09641529 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -85,6 +85,86 @@
#size-cells = <2>;
ranges;
+ ssi0: ssi@10049c00 {
+ compatible = "renesas,r9a07g044-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x10049c00 0 0x400>;
+ interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
+ <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
+ <&audio_clk1>,
+ <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ ssi1: ssi@1004a000 {
+ compatible = "renesas,r9a07g044-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x1004a000 0 0x400>;
+ interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
+ <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
+ <&audio_clk1>,
+ <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ ssi2: ssi@1004a400 {
+ compatible = "renesas,r9a07g044-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x1004a400 0 0x400>;
+ interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
+ <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
+ <&audio_clk1>,
+ <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ ssi3: ssi@1004a800 {
+ compatible = "renesas,r9a07g044-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x1004a800 0 0x400>;
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
+ <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
+ <&audio_clk1>,
+ <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
scif0: serial@1004b800 {
compatible = "renesas,scif-r9a07g044";
reg = <0 0x1004b800 0 0x400>;
--
2.17.1
next prev parent reply other threads:[~2021-07-19 13:41 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-19 13:40 [PATCH v2 0/8] Add RZ/G2L Sound support Biju Das
2021-07-19 13:40 ` Biju Das
2021-07-19 13:40 ` [PATCH v2 1/8] ASoC: dt-bindings: Document RZ/G2L bindings Biju Das
2021-07-19 13:40 ` Biju Das
2021-07-19 22:16 ` Rob Herring
2021-07-19 22:16 ` Rob Herring
2021-07-20 11:24 ` Biju Das
2021-07-20 11:24 ` Biju Das
2021-07-29 19:11 ` Rob Herring
2021-07-29 19:11 ` Rob Herring
2021-07-19 13:40 ` [PATCH v2 2/8] sound: soc: sh: Add RZ/G2L SSIF-2 driver Biju Das
2021-07-19 13:40 ` Biju Das
2021-07-20 9:57 ` Geert Uytterhoeven
2021-07-20 9:57 ` Geert Uytterhoeven
2021-07-20 10:24 ` Biju Das
2021-07-20 10:24 ` Biju Das
2021-07-19 13:40 ` [PATCH v2 3/8] arm64: dts: renesas: r9a07g044: Add external audio clock nodes Biju Das
2021-07-19 13:40 ` Biju Das [this message]
2021-07-19 13:40 ` [PATCH v2 5/8] arm64: defconfig: Enable ASoC sound support for RZ/G2L SoC Biju Das
2021-07-19 13:40 ` Biju Das
2021-07-19 13:40 ` [PATCH v2 6/8] ASoC: dt-bindings: sound: renesas,rz-ssi: Document DMA support Biju Das
2021-07-19 13:40 ` [PATCH v2 6/8] ASoC: dt-bindings: sound: renesas, rz-ssi: " Biju Das
2021-07-29 19:13 ` [PATCH v2 6/8] ASoC: dt-bindings: sound: renesas,rz-ssi: " Rob Herring
2021-07-29 19:13 ` Rob Herring
2021-07-19 13:40 ` [PATCH v2 7/8] sound: sh: rz-ssi: Add SSI DMAC support Biju Das
2021-07-19 13:40 ` Biju Das
2021-07-19 13:40 ` [PATCH v2 8/8] arm64: dts: renesas: r9a07g044: Add SSI DMA support Biju Das
2021-07-30 19:03 ` (subset) [PATCH v2 0/8] Add RZ/G2L Sound support Mark Brown
2021-07-30 19:03 ` Mark Brown
2021-07-30 19:13 ` Prabhakar Mahadev Lad
2021-07-30 19:13 ` Prabhakar Mahadev Lad
2021-07-31 6:42 ` Biju Das
2021-07-31 6:42 ` Biju Das
2021-08-02 12:16 ` Mark Brown
2021-08-02 12:16 ` Mark Brown
2021-08-02 12:32 ` Lad, Prabhakar
2021-08-02 12:32 ` Lad, Prabhakar
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