From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH for-6.2 00/53] target/arm: MVE slices 3 and 4
Date: Thu, 29 Jul 2021 12:14:19 +0100 [thread overview]
Message-ID: <20210729111512.16541-1-peter.maydell@linaro.org> (raw)
This patchseries provides the third and fourth slices of the MVE
implementation, which gives us complete coverage of all instructions
and brings us to the point where we can actually enable it.
In this series:
* fixes for minor bugs in a couple of the insns already upstream
* all the remaining integer instructions
* the remaining loads and stores (scatter-gather and interleaving)
* the floating point instructions
* patch enabling MVE for the Cortex-M55
Things still to do:
* MVE loads/stores should check alignment (this will depend on
the patchset that RTH just sent out, and I didn't want to
entangle the two features unnecessarily)
* gdbstub support (blocked on the gdb folks nailing down what
the XML for it should be)
* optimization: many of the insns should have inline versions
to use when we know we aren't doing any predication
But none of those are blockers for this landing upstream once
we reopen for 6.2.
Still to review:
03, 07, 10, 21, 26, and the new patches 36-53
thanks
-- PMM
Peter Maydell (53):
target/arm: Note that we handle VMOVL as a special case of VSHLL
target/arm: Print MVE VPR in CPU dumps
target/arm: Fix MVE VSLI by 0 and VSRI by <dt>
target/arm: Fix signed VADDV
target/arm: Fix mask handling for MVE narrowing operations
target/arm: Fix 48-bit saturating shifts
target/arm: Fix MVE 48-bit SQRSHRL for small right shifts
target/arm: Fix calculation of LTP mask when LR is 0
target/arm: Factor out mve_eci_mask()
target/arm: Fix VPT advance when ECI is non-zero
target/arm: Fix VLDRB/H/W for predicated elements
target/arm: Implement MVE VMULL (polynomial)
target/arm: Implement MVE incrementing/decrementing dup insns
target/arm: Factor out gen_vpst()
target/arm: Implement MVE integer vector comparisons
target/arm: Implement MVE integer vector-vs-scalar comparisons
target/arm: Implement MVE VPSEL
target/arm: Implement MVE VMLAS
target/arm: Implement MVE shift-by-scalar
target/arm: Move 'x' and 'a' bit definitions into vmlaldav formats
target/arm: Implement MVE integer min/max across vector
target/arm: Implement MVE VABAV
target/arm: Implement MVE narrowing moves
target/arm: Rename MVEGenDualAccOpFn to MVEGenLongDualAccOpFn
target/arm: Implement MVE VMLADAV and VMLSLDAV
target/arm: Implement MVE VMLA
target/arm: Implement MVE saturating doubling multiply accumulates
target/arm: Implement MVE VQABS, VQNEG
target/arm: Implement MVE VMAXA, VMINA
target/arm: Implement MVE VMOV to/from 2 general-purpose registers
target/arm: Implement MVE VPNOT
target/arm: Implement MVE VCTP
target/arm: Implement MVE scatter-gather insns
target/arm: Implement MVE scatter-gather immediate forms
target/arm: Implement MVE interleaving loads/stores
target/arm: Implement MVE VADD (floating-point)
target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNM
target/arm: Implement MVE VCADD
target/arm: Implement MVE VFMA and VFMS
target/arm: Implement MVE VCMUL and VCMLA
target/arm: Implement MVE VMAXNMA and VMINNMA
target/arm: Implement MVE scalar fp insns
target/arm: Implement MVE fp-with-scalar VFMA, VFMAS
softfloat: Remove assertion preventing silencing of NaN in default-NaN
mode
target/arm: Implement MVE FP max/min across vector
target/arm: Implement MVE fp vector comparisons
target/arm: Implement MVE fp scalar comparisons
target/arm: Implement MVE VCVT between floating and fixed point
target/arm: Implement MVE VCVT between fp and integer
target/arm: Implement MVE VCVT with specified rounding mode
target/arm: Implement MVE VCVT between single and half precision
target/arm: Implement MVE VRINT insns
target/arm: Enable MVE in Cortex-M55
docs/system/arm/emulation.rst | 1 +
target/arm/helper-mve.h | 425 +++++++
target/arm/translate-a32.h | 2 +
target/arm/translate.h | 6 +
target/arm/vec_internal.h | 11 +
target/arm/mve.decode | 463 +++++++-
target/arm/t32.decode | 1 +
target/arm/cpu.c | 3 +
target/arm/cpu_tcg.c | 7 +-
target/arm/mve_helper.c | 1899 +++++++++++++++++++++++++++++++-
target/arm/translate-mve.c | 1154 ++++++++++++++++++-
target/arm/translate-neon.c | 6 -
target/arm/translate-vfp.c | 2 +-
target/arm/translate.c | 33 +
target/arm/vec_helper.c | 14 +-
fpu/softfloat-specialize.c.inc | 1 -
16 files changed, 3911 insertions(+), 117 deletions(-)
--
2.20.1
next reply other threads:[~2021-07-29 11:17 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-29 11:14 Peter Maydell [this message]
2021-07-29 11:14 ` [PATCH for-6.2 01/53] target/arm: Note that we handle VMOVL as a special case of VSHLL Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 02/53] target/arm: Print MVE VPR in CPU dumps Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 03/53] target/arm: Fix MVE VSLI by 0 and VSRI by <dt> Peter Maydell
2021-07-30 18:56 ` Richard Henderson
2021-07-29 11:14 ` [PATCH for-6.2 04/53] target/arm: Fix signed VADDV Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 05/53] target/arm: Fix mask handling for MVE narrowing operations Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 06/53] target/arm: Fix 48-bit saturating shifts Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 07/53] target/arm: Fix MVE 48-bit SQRSHRL for small right shifts Peter Maydell
2021-07-30 19:07 ` Richard Henderson
2021-08-12 9:43 ` Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 08/53] target/arm: Fix calculation of LTP mask when LR is 0 Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 09/53] target/arm: Factor out mve_eci_mask() Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 10/53] target/arm: Fix VPT advance when ECI is non-zero Peter Maydell
2021-07-30 19:14 ` Richard Henderson
2021-07-29 11:14 ` [PATCH for-6.2 11/53] target/arm: Fix VLDRB/H/W for predicated elements Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 12/53] target/arm: Implement MVE VMULL (polynomial) Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 13/53] target/arm: Implement MVE incrementing/decrementing dup insns Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 14/53] target/arm: Factor out gen_vpst() Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 15/53] target/arm: Implement MVE integer vector comparisons Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 16/53] target/arm: Implement MVE integer vector-vs-scalar comparisons Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 17/53] target/arm: Implement MVE VPSEL Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 18/53] target/arm: Implement MVE VMLAS Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 19/53] target/arm: Implement MVE shift-by-scalar Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 20/53] target/arm: Move 'x' and 'a' bit definitions into vmlaldav formats Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 21/53] target/arm: Implement MVE integer min/max across vector Peter Maydell
2021-07-30 19:15 ` Richard Henderson
2021-07-29 11:14 ` [PATCH for-6.2 22/53] target/arm: Implement MVE VABAV Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 23/53] target/arm: Implement MVE narrowing moves Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 24/53] target/arm: Rename MVEGenDualAccOpFn to MVEGenLongDualAccOpFn Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 25/53] target/arm: Implement MVE VMLADAV and VMLSLDAV Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 26/53] target/arm: Implement MVE VMLA Peter Maydell
2021-07-30 19:18 ` Richard Henderson
2021-07-29 11:14 ` [PATCH for-6.2 27/53] target/arm: Implement MVE saturating doubling multiply accumulates Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 28/53] target/arm: Implement MVE VQABS, VQNEG Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 29/53] target/arm: Implement MVE VMAXA, VMINA Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 30/53] target/arm: Implement MVE VMOV to/from 2 general-purpose registers Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 31/53] target/arm: Implement MVE VPNOT Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 32/53] target/arm: Implement MVE VCTP Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 33/53] target/arm: Implement MVE scatter-gather insns Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 34/53] target/arm: Implement MVE scatter-gather immediate forms Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 35/53] target/arm: Implement MVE interleaving loads/stores Peter Maydell
2021-07-29 11:14 ` [PATCH for-6.2 36/53] target/arm: Implement MVE VADD (floating-point) Peter Maydell
2021-07-30 19:27 ` Richard Henderson
2021-07-30 19:37 ` Richard Henderson
2021-07-29 11:14 ` [PATCH for-6.2 37/53] target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNM Peter Maydell
2021-07-30 19:28 ` Richard Henderson
2021-07-29 11:14 ` [PATCH for-6.2 38/53] target/arm: Implement MVE VCADD Peter Maydell
2021-07-30 19:32 ` Richard Henderson
2021-07-29 11:14 ` [PATCH for-6.2 39/53] target/arm: Implement MVE VFMA and VFMS Peter Maydell
2021-07-30 19:34 ` Richard Henderson
2021-07-30 19:41 ` Richard Henderson
2021-07-29 11:14 ` [PATCH for-6.2 40/53] target/arm: Implement MVE VCMUL and VCMLA Peter Maydell
2021-07-30 19:47 ` Richard Henderson
2021-07-29 11:15 ` [PATCH for-6.2 41/53] target/arm: Implement MVE VMAXNMA and VMINNMA Peter Maydell
2021-07-30 19:50 ` Richard Henderson
2021-07-29 11:15 ` [PATCH for-6.2 42/53] target/arm: Implement MVE scalar fp insns Peter Maydell
2021-07-30 19:55 ` Richard Henderson
2021-07-29 11:15 ` [PATCH for-6.2 43/53] target/arm: Implement MVE fp-with-scalar VFMA, VFMAS Peter Maydell
2021-07-30 19:58 ` Richard Henderson
2021-07-29 11:15 ` [PATCH for-6.2 44/53] softfloat: Remove assertion preventing silencing of NaN in default-NaN mode Peter Maydell
2021-07-30 20:00 ` Richard Henderson
2021-07-29 11:15 ` [PATCH for-6.2 45/53] target/arm: Implement MVE FP max/min across vector Peter Maydell
2021-07-30 20:12 ` Richard Henderson
2021-07-29 11:15 ` [PATCH for-6.2 46/53] target/arm: Implement MVE fp vector comparisons Peter Maydell
2021-07-30 20:21 ` Richard Henderson
2021-07-29 11:15 ` [PATCH for-6.2 47/53] target/arm: Implement MVE fp scalar comparisons Peter Maydell
2021-07-30 20:22 ` Richard Henderson
2021-07-29 11:15 ` [PATCH for-6.2 48/53] target/arm: Implement MVE VCVT between floating and fixed point Peter Maydell
2021-07-30 20:24 ` Richard Henderson
2021-07-29 11:15 ` [PATCH for-6.2 49/53] target/arm: Implement MVE VCVT between fp and integer Peter Maydell
2021-07-30 20:27 ` Richard Henderson
2021-07-29 11:15 ` [PATCH for-6.2 50/53] target/arm: Implement MVE VCVT with specified rounding mode Peter Maydell
2021-07-30 20:28 ` Richard Henderson
2021-07-29 11:15 ` [PATCH for-6.2 51/53] target/arm: Implement MVE VCVT between single and half precision Peter Maydell
2021-07-30 20:33 ` Richard Henderson
2021-07-29 11:15 ` [PATCH for-6.2 52/53] target/arm: Implement MVE VRINT insns Peter Maydell
2021-07-30 20:47 ` Richard Henderson
2021-07-29 11:15 ` [PATCH for-6.2 53/53] target/arm: Enable MVE in Cortex-M55 Peter Maydell
2021-07-30 20:48 ` Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210729111512.16541-1-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.