From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEE24C4338F for ; Thu, 29 Jul 2021 22:29:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ADECE60720 for ; Thu, 29 Jul 2021 22:29:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230205AbhG2W3b (ORCPT ); Thu, 29 Jul 2021 18:29:31 -0400 Received: from mail.kernel.org ([198.145.29.99]:54314 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229944AbhG2W3X (ORCPT ); Thu, 29 Jul 2021 18:29:23 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 1982360720; Thu, 29 Jul 2021 22:29:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1627597759; bh=Z5vs1zoSqEBxxqhhSmMqcsfe2C7l5EM32gjPdmoyxEM=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=ow5YnxaXbEOrfH4JYT2y1RMAesCkN/7tbE/AmLKSds8GczI0Z2cjX8NvoAD0tI9zl 5It9feOWMTsxvab3SeVe0xCOyamkWOKwr8fDgv21ShbrHrv/Z8LoEP03gHi2ZdyeSS iiUkZSHEMh/r+ZgR24Bd3OxC4SCNsIH8PfONyr8yPoUM9s6AOm28pumoOJDUkLuBAp 8gxh3ZxZ6e8poQNmcPJLRm5B1L6YAuKA821nTVolYIdrBTwNGo8hCT/p6lz4KuN/3i iaFnBo60imEzrzTWVnOj2hkdx/3lV87l+H+Czbg6cuwMyDWojb9mCrlyYJ4FZIgh8Z P/U6AJk1KXKag== Date: Thu, 29 Jul 2021 17:29:17 -0500 From: Bjorn Helgaas To: Tim Harvey Cc: Richard Zhu , Lucas Stach , Bjorn Helgaas , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Lorenzo Pieralisi Subject: Re: [PATCH 3/6] PCI: imx6: add IMX8MM support Message-ID: <20210729222917.GA998237@bjorn-Precision-5520> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210723204958.7186-4-tharvey@gateworks.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Capitalize first letter of subject to match history: PCI: imx6: Add IMX8MM support On Fri, Jul 23, 2021 at 01:49:55PM -0700, Tim Harvey wrote: > Add IMX8MM support to the existing driver which shares most > functionality with the IMX8MM. > > Signed-off-by: Tim Harvey > --- > drivers/pci/controller/dwc/pci-imx6.c | 103 +++++++++++++++++++++++++- > 1 file changed, 102 insertions(+), 1 deletion(-) > + case IMX8MM: > + offset = imx6_pcie_grp_offset(imx6_pcie); > + > + dev_info(imx6_pcie->pci->dev, "%s REF_CLK is used!.\n", > + imx6_pcie->ext_osc ? "EXT" : "PLL"); > + if (imx6_pcie->ext_osc) { > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MQ_GPR_PCIE_REF_USE_PAD, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > + IMX8MM_GPR_PCIE_REF_CLK_SEL); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_AUX_EN, > + IMX8MM_GPR_PCIE_AUX_EN); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_POWER_OFF, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_SSC_EN, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > + IMX8MM_GPR_PCIE_REF_CLK_EXT); > + udelay(100); > + /* Do the PHY common block reset */ > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_CMN_RST, > + IMX8MM_GPR_PCIE_CMN_RST); > + udelay(200); > + } else { > + /* Configure the internal PLL as REF clock */ > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MQ_GPR_PCIE_REF_USE_PAD, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > + IMX8MM_GPR_PCIE_REF_CLK_SEL); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_AUX_EN, > + IMX8MM_GPR_PCIE_AUX_EN); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_POWER_OFF, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_SSC_EN, 0); Seems like all the above is common to both cases? If so, it's a shame to repeat it because it makes it hard to see what's different. > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > + IMX8MM_GPR_PCIE_REF_CLK_PLL); > + udelay(100); > + /* Configure the PHY */ > + writel(PCIE_PHY_CMN_REG62_PLL_CLK_OUT, > + imx6_pcie->phy_base + PCIE_PHY_CMN_REG62); > + writel(PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM, > + imx6_pcie->phy_base + PCIE_PHY_CMN_REG64); > + /* Do the PHY common block reset */ > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_CMN_RST, > + IMX8MM_GPR_PCIE_CMN_RST); > + udelay(200); > + } > + /* > + * In order to pass the compliance tests. > + * Configure the TRSV regiser of iMX8MM PCIe PHY. The "In order to ..." line isn't quite a sentence. Maybe it should be joined with the second line? s/regiser/register/ ? > + */ > + writel(PCIE_PHY_TRSV_REG5_GEN1_DEEMP, > + imx6_pcie->phy_base + PCIE_PHY_TRSV_REG5); > + /* check for EXT osc */ Since you have a comment here, it would be useful to spell out "osc" for newbies like me. I assume it's short for "oscillator"? > + imx6_pcie->ext_osc = of_property_read_bool(node, "fsl,ext-osc"); From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 072C9C4338F for ; Thu, 29 Jul 2021 22:31:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B0F7A60F46 for ; Thu, 29 Jul 2021 22:31:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B0F7A60F46 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Owner; bh=PQU1ffSmMuF6y08ZOZARcbiBoprE2y1SVjsCc1wj+rs=; b=0tlbRa3WbTH6vL 6FGe2inibusag5+Nc9ttg+JuZxU/vBMEsDm/mM9Xyvt0jyYMy+XVMKepvljvHosixeZfONcT4vR0r mychEiA+I4Dz39HctQRr+S3VEy6uh9N7/OwJnDVAgyzGlM4IyhGmwJb10/NUBW9f9P7kyKx4KaAcZ bHrnK4turlxhnzJM4X1ckYS+U3FsLuo3MM/X6UOnbg5uN0+UWdaJv8B9rnq6h+k/+7y2DsbjApnVY mHIwb4ITGSX3w6zQ7ckUFp04CYQGfcOwAjKUniyAs3M1Ijmjk+RM4Jy2YozaBi6cW7ueyYM+uGfdq 2TVBXTdYe2TWEuVaxRBQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m9EWp-006DRd-8I; Thu, 29 Jul 2021 22:29:23 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m9EWm-006DRG-8G for linux-arm-kernel@lists.infradead.org; Thu, 29 Jul 2021 22:29:21 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 1982360720; Thu, 29 Jul 2021 22:29:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1627597759; bh=Z5vs1zoSqEBxxqhhSmMqcsfe2C7l5EM32gjPdmoyxEM=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=ow5YnxaXbEOrfH4JYT2y1RMAesCkN/7tbE/AmLKSds8GczI0Z2cjX8NvoAD0tI9zl 5It9feOWMTsxvab3SeVe0xCOyamkWOKwr8fDgv21ShbrHrv/Z8LoEP03gHi2ZdyeSS iiUkZSHEMh/r+ZgR24Bd3OxC4SCNsIH8PfONyr8yPoUM9s6AOm28pumoOJDUkLuBAp 8gxh3ZxZ6e8poQNmcPJLRm5B1L6YAuKA821nTVolYIdrBTwNGo8hCT/p6lz4KuN/3i iaFnBo60imEzrzTWVnOj2hkdx/3lV87l+H+Czbg6cuwMyDWojb9mCrlyYJ4FZIgh8Z P/U6AJk1KXKag== Date: Thu, 29 Jul 2021 17:29:17 -0500 From: Bjorn Helgaas To: Tim Harvey Cc: Richard Zhu , Lucas Stach , Bjorn Helgaas , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Lorenzo Pieralisi Subject: Re: [PATCH 3/6] PCI: imx6: add IMX8MM support Message-ID: <20210729222917.GA998237@bjorn-Precision-5520> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210723204958.7186-4-tharvey@gateworks.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210729_152920_374731_D072940A X-CRM114-Status: GOOD ( 19.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Capitalize first letter of subject to match history: PCI: imx6: Add IMX8MM support On Fri, Jul 23, 2021 at 01:49:55PM -0700, Tim Harvey wrote: > Add IMX8MM support to the existing driver which shares most > functionality with the IMX8MM. > > Signed-off-by: Tim Harvey > --- > drivers/pci/controller/dwc/pci-imx6.c | 103 +++++++++++++++++++++++++- > 1 file changed, 102 insertions(+), 1 deletion(-) > + case IMX8MM: > + offset = imx6_pcie_grp_offset(imx6_pcie); > + > + dev_info(imx6_pcie->pci->dev, "%s REF_CLK is used!.\n", > + imx6_pcie->ext_osc ? "EXT" : "PLL"); > + if (imx6_pcie->ext_osc) { > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MQ_GPR_PCIE_REF_USE_PAD, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > + IMX8MM_GPR_PCIE_REF_CLK_SEL); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_AUX_EN, > + IMX8MM_GPR_PCIE_AUX_EN); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_POWER_OFF, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_SSC_EN, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > + IMX8MM_GPR_PCIE_REF_CLK_EXT); > + udelay(100); > + /* Do the PHY common block reset */ > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_CMN_RST, > + IMX8MM_GPR_PCIE_CMN_RST); > + udelay(200); > + } else { > + /* Configure the internal PLL as REF clock */ > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MQ_GPR_PCIE_REF_USE_PAD, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > + IMX8MM_GPR_PCIE_REF_CLK_SEL); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_AUX_EN, > + IMX8MM_GPR_PCIE_AUX_EN); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_POWER_OFF, 0); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_SSC_EN, 0); Seems like all the above is common to both cases? If so, it's a shame to repeat it because it makes it hard to see what's different. > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_REF_CLK_SEL, > + IMX8MM_GPR_PCIE_REF_CLK_PLL); > + udelay(100); > + /* Configure the PHY */ > + writel(PCIE_PHY_CMN_REG62_PLL_CLK_OUT, > + imx6_pcie->phy_base + PCIE_PHY_CMN_REG62); > + writel(PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM, > + imx6_pcie->phy_base + PCIE_PHY_CMN_REG64); > + /* Do the PHY common block reset */ > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, > + IMX8MM_GPR_PCIE_CMN_RST, > + IMX8MM_GPR_PCIE_CMN_RST); > + udelay(200); > + } > + /* > + * In order to pass the compliance tests. > + * Configure the TRSV regiser of iMX8MM PCIe PHY. The "In order to ..." line isn't quite a sentence. Maybe it should be joined with the second line? s/regiser/register/ ? > + */ > + writel(PCIE_PHY_TRSV_REG5_GEN1_DEEMP, > + imx6_pcie->phy_base + PCIE_PHY_TRSV_REG5); > + /* check for EXT osc */ Since you have a comment here, it would be useful to spell out "osc" for newbies like me. I assume it's short for "oscillator"? > + imx6_pcie->ext_osc = of_property_read_bool(node, "fsl,ext-osc"); _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel