From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82402C4338F for ; Fri, 30 Jul 2021 02:02:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5422E60F4B for ; Fri, 30 Jul 2021 02:02:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5422E60F4B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0D01C6F37F; Fri, 30 Jul 2021 02:02:21 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3BBF06F37F; Fri, 30 Jul 2021 02:02:00 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10060"; a="200186043" X-IronPort-AV: E=Sophos;i="5.84,280,1620716400"; d="scan'208";a="200186043" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2021 19:01:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,280,1620716400"; d="scan'208";a="664637799" Received: from vbelgaum-ubuntu.fm.intel.com ([10.1.27.27]) by fmsmga006.fm.intel.com with ESMTP; 29 Jul 2021 19:01:59 -0700 From: Vinay Belgaumkar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 29 Jul 2021 19:01:07 -0700 Message-Id: <20210730020107.31415-15-vinay.belgaumkar@intel.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20210730020107.31415-1-vinay.belgaumkar@intel.com> References: <20210730020107.31415-1-vinay.belgaumkar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 14/14] drm/i915/guc/rc: Setup and enable GuCRC feature X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" VGhpcyBmZWF0dXJlIGhhbmRzIG92ZXIgdGhlIGNvbnRyb2wgb2YgSFcgUkM2IHRvIHRoZSBHdUMu Ckd1QyBkZWNpZGVzIHdoZW4gdG8gcHV0IEhXIGludG8gUkM2IGJhc2VkIG9uIGl0J3MgaW50ZXJu YWwKYnVzeW5lc3MgYWxnb3JpdGhtcy4KCkd1Q1JDIG5lZWRzIEd1QyBzdWJtaXNzaW9uIHRvIGJl IGVuYWJsZWQsIGFuZCBvbmx5CnN1cHBvcnRlZCBvbiBHZW4xMisgZm9yIG5vdy4KCldoZW4gR3VD UkMgaXMgZW5hYmxlZCwgZG8gbm90IHNldCBIVyBSQzYuIFVzZSBhIEgyRyBtZXNzYWdlCnRvIHRl bGwgR3VDIHRvIGVuYWJsZSBHdUNSQy4gV2hlbiBkaXNhYmxpbmcgUkM2LCB0ZWxsIEd1QyB0bwpy ZXZlcnQgUkM2IGNvbnRyb2wgYmFjayB0byBLTUQuIEtNRCBpcyBzdGlsbCByZXNwb25zaWJsZSBm b3IKZW5hYmxpbmcgZXZlcnl0aGluZyByZWxhdGVkIHRvIENvYXJzZSBQb3dlciBHYXRpbmcgdGhv dWdoLgoKdjI6IEFkZHJlc3MgY29tbWVudHMgKE1pY2hhbCBXKQp2MzogRG9uJ3Qgc2V0IGh5c3Rl cmlzaXMgdmFsdWVzIHdoZW4gR3VDUkMgaXMgdXNlZCAoTWF0dCBSb3BlcikKdjQ6IGNoZWNrcGF0 Y2goKQoKUmV2aWV3ZWQtYnk6IE1pY2hhbCBXYWpkZWN6a28gPG1pY2hhbC53YWpkZWN6a29AaW50 ZWwuY29tPgpTaWduZWQtb2ZmLWJ5OiBWaW5heSBCZWxnYXVta2FyIDx2aW5heS5iZWxnYXVta2Fy QGludGVsLmNvbT4KLS0tCiBkcml2ZXJzL2dwdS9kcm0vaTkxNS9NYWtlZmlsZSAgICAgICAgICAg ICAgICAgfCAgMSArCiBkcml2ZXJzL2dwdS9kcm0vaTkxNS9ndC9pbnRlbF9yYzYuYyAgICAgICAg ICAgfCA0NyArKysrKysrLS0tLQogLi4uL2dwdS9kcm0vaTkxNS9ndC91Yy9hYmkvZ3VjX2FjdGlv bnNfYWJpLmggIHwgIDYgKysKIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L3VjL2ludGVsX2d1Yy5j ICAgICAgICB8ICAxICsKIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L3VjL2ludGVsX2d1Yy5oICAg ICAgICB8ICAyICsKIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L3VjL2ludGVsX2d1Y19yYy5jICAg ICB8IDgwICsrKysrKysrKysrKysrKysrKysKIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L3VjL2lu dGVsX2d1Y19yYy5oICAgICB8IDMxICsrKysrKysKIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L3Vj L2ludGVsX3VjLmggICAgICAgICB8ICAyICsKIDggZmlsZXMgY2hhbmdlZCwgMTU1IGluc2VydGlv bnMoKyksIDE1IGRlbGV0aW9ucygtKQogY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvZ3B1L2Ry bS9pOTE1L2d0L3VjL2ludGVsX2d1Y19yYy5jCiBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9n cHUvZHJtL2k5MTUvZ3QvdWMvaW50ZWxfZ3VjX3JjLmgKCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dw dS9kcm0vaTkxNS9NYWtlZmlsZSBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L01ha2VmaWxlCmluZGV4 IGQ4ZWFjNDQ2OGRmOS4uM2ZjMTdmMjBkODhlIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0v aTkxNS9NYWtlZmlsZQorKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9NYWtlZmlsZQpAQCAtMTg2 LDYgKzE4Niw3IEBAIGk5MTUteSArPSBndC91Yy9pbnRlbF91Yy5vIFwKIAkgIGd0L3VjL2ludGVs X2d1Y19mdy5vIFwKIAkgIGd0L3VjL2ludGVsX2d1Y19sb2cubyBcCiAJICBndC91Yy9pbnRlbF9n dWNfbG9nX2RlYnVnZnMubyBcCisJICBndC91Yy9pbnRlbF9ndWNfcmMubyBcCiAJICBndC91Yy9p bnRlbF9ndWNfc2xwYy5vIFwKIAkgIGd0L3VjL2ludGVsX2d1Y19zdWJtaXNzaW9uLm8gXAogCSAg Z3QvdWMvaW50ZWxfaHVjLm8gXApkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3Qv aW50ZWxfcmM2LmMgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9ndC9pbnRlbF9yYzYuYwppbmRleCAy NTlkN2ViNGUxNjUuLmY2YjkxNDQzOGEwYiAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5 MTUvZ3QvaW50ZWxfcmM2LmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3QvaW50ZWxfcmM2 LmMKQEAgLTYyLDIwICs2MiwyNSBAQCBzdGF0aWMgdm9pZCBnZW4xMV9yYzZfZW5hYmxlKHN0cnVj dCBpbnRlbF9yYzYgKnJjNikKIAl1MzIgcGdfZW5hYmxlOwogCWludCBpOwogCi0JLyogMmI6IFBy b2dyYW0gUkM2IHRocmVzaG9sZHMuKi8KLQlzZXQodW5jb3JlLCBHRU42X1JDNl9XQUtFX1JBVEVf TElNSVQsIDU0IDw8IDE2IHwgODUpOwotCXNldCh1bmNvcmUsIEdFTjEwX01FRElBX1dBS0VfUkFU RV9MSU1JVCwgMTUwKTsKKwkvKgorCSAqIFdpdGggR3VDUkMsIHRoZXNlIHBhcmFtZXRlcnMgYXJl IHNldCBieSBHdUMKKwkgKi8KKwlpZiAoIWludGVsX3VjX3VzZXNfZ3VjX3JjKCZndC0+dWMpKSB7 CisJCS8qIDJiOiBQcm9ncmFtIFJDNiB0aHJlc2hvbGRzLiovCisJCXNldCh1bmNvcmUsIEdFTjZf UkM2X1dBS0VfUkFURV9MSU1JVCwgNTQgPDwgMTYgfCA4NSk7CisJCXNldCh1bmNvcmUsIEdFTjEw X01FRElBX1dBS0VfUkFURV9MSU1JVCwgMTUwKTsKIAotCXNldCh1bmNvcmUsIEdFTjZfUkNfRVZB TFVBVElPTl9JTlRFUlZBTCwgMTI1MDAwKTsgLyogMTI1MDAgKiAxMjgwbnMgKi8KLQlzZXQodW5j b3JlLCBHRU42X1JDX0lETEVfSFlTVEVSU0lTLCAyNSk7IC8qIDI1ICogMTI4MG5zICovCi0JZm9y X2VhY2hfZW5naW5lKGVuZ2luZSwgcmM2X3RvX2d0KHJjNiksIGlkKQotCQlzZXQodW5jb3JlLCBS SU5HX01BWF9JRExFKGVuZ2luZS0+bW1pb19iYXNlKSwgMTApOworCQlzZXQodW5jb3JlLCBHRU42 X1JDX0VWQUxVQVRJT05fSU5URVJWQUwsIDEyNTAwMCk7IC8qIDEyNTAwICogMTI4MG5zICovCisJ CXNldCh1bmNvcmUsIEdFTjZfUkNfSURMRV9IWVNURVJTSVMsIDI1KTsgLyogMjUgKiAxMjgwbnMg Ki8KKwkJZm9yX2VhY2hfZW5naW5lKGVuZ2luZSwgcmM2X3RvX2d0KHJjNiksIGlkKQorCQkJc2V0 KHVuY29yZSwgUklOR19NQVhfSURMRShlbmdpbmUtPm1taW9fYmFzZSksIDEwKTsKIAotCXNldCh1 bmNvcmUsIEdVQ19NQVhfSURMRV9DT1VOVCwgMHhBKTsKKwkJc2V0KHVuY29yZSwgR1VDX01BWF9J RExFX0NPVU5ULCAweEEpOwogCi0Jc2V0KHVuY29yZSwgR0VONl9SQ19TTEVFUCwgMCk7CisJCXNl dCh1bmNvcmUsIEdFTjZfUkNfU0xFRVAsIDApOwogCi0Jc2V0KHVuY29yZSwgR0VONl9SQzZfVEhS RVNIT0xELCA1MDAwMCk7IC8qIDUwLzEyNW1zIHBlciBFSSAqLworCQlzZXQodW5jb3JlLCBHRU42 X1JDNl9USFJFU0hPTEQsIDUwMDAwKTsgLyogNTAvMTI1bXMgcGVyIEVJICovCisJfQogCiAJLyoK IAkgKiAyYzogUHJvZ3JhbSBDb2Fyc2UgUG93ZXIgR2F0aW5nIFBvbGljaWVzLgpAQCAtOTgsMTEg KzEwMywxOSBAQCBzdGF0aWMgdm9pZCBnZW4xMV9yYzZfZW5hYmxlKHN0cnVjdCBpbnRlbF9yYzYg KnJjNikKIAlzZXQodW5jb3JlLCBHRU45X01FRElBX1BHX0lETEVfSFlTVEVSRVNJUywgNjApOwog CXNldCh1bmNvcmUsIEdFTjlfUkVOREVSX1BHX0lETEVfSFlTVEVSRVNJUywgNjApOwogCi0JLyog M2E6IEVuYWJsZSBSQzYgKi8KLQlyYzYtPmN0bF9lbmFibGUgPQotCQlHRU42X1JDX0NUTF9IV19F TkFCTEUgfAotCQlHRU42X1JDX0NUTF9SQzZfRU5BQkxFIHwKLQkJR0VONl9SQ19DVExfRUlfTU9E RSgxKTsKKwkvKiAzYTogRW5hYmxlIFJDNgorCSAqCisJICogV2l0aCBHdUNSQywgd2UgZG8gbm90 IGVuYWJsZSBiaXQgMzEgb2YgUkNfQ1RMLAorCSAqIHRodXMgYWxsb3dpbmcgR3VDIHRvIGNvbnRy b2wgUkM2IGVudHJ5L2V4aXQgZnVsbHkgaW5zdGVhZC4KKwkgKiBXZSB3aWxsIG5vdCBzZXQgdGhl IEhXIEVOQUJMRSBhbmQgRUkgYml0cworCSAqLworCWlmICghaW50ZWxfZ3VjX3JjX2VuYWJsZSgm Z3QtPnVjLmd1YykpCisJCXJjNi0+Y3RsX2VuYWJsZSA9IEdFTjZfUkNfQ1RMX1JDNl9FTkFCTEU7 CisJZWxzZQorCQlyYzYtPmN0bF9lbmFibGUgPQorCQkJR0VONl9SQ19DVExfSFdfRU5BQkxFIHwK KwkJCUdFTjZfUkNfQ1RMX1JDNl9FTkFCTEUgfAorCQkJR0VONl9SQ19DVExfRUlfTU9ERSgxKTsK IAogCXBnX2VuYWJsZSA9CiAJCUdFTjlfUkVOREVSX1BHX0VOQUJMRSB8CkBAIC01MTMsNiArNTI2 LDEwIEBAIHN0YXRpYyB2b2lkIF9faW50ZWxfcmM2X2Rpc2FibGUoc3RydWN0IGludGVsX3JjNiAq cmM2KQogewogCXN0cnVjdCBkcm1faTkxNV9wcml2YXRlICppOTE1ID0gcmM2X3RvX2k5MTUocmM2 KTsKIAlzdHJ1Y3QgaW50ZWxfdW5jb3JlICp1bmNvcmUgPSByYzZfdG9fdW5jb3JlKHJjNik7CisJ c3RydWN0IGludGVsX2d0ICpndCA9IHJjNl90b19ndChyYzYpOworCisJLyogVGFrZSBjb250cm9s IG9mIFJDNiBiYWNrIGZyb20gR3VDICovCisJaW50ZWxfZ3VjX3JjX2Rpc2FibGUoJmd0LT51Yy5n dWMpOwogCiAJaW50ZWxfdW5jb3JlX2ZvcmNld2FrZV9nZXQodW5jb3JlLCBGT1JDRVdBS0VfQUxM KTsKIAlpZiAoR1JBUEhJQ1NfVkVSKGk5MTUpID49IDkpCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dw dS9kcm0vaTkxNS9ndC91Yy9hYmkvZ3VjX2FjdGlvbnNfYWJpLmggYi9kcml2ZXJzL2dwdS9kcm0v aTkxNS9ndC91Yy9hYmkvZ3VjX2FjdGlvbnNfYWJpLmgKaW5kZXggY2E1MzhlNWRlOTQwLi44ZmY1 ODIyMjJhZmYgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L3VjL2FiaS9ndWNf YWN0aW9uc19hYmkuaAorKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9ndC91Yy9hYmkvZ3VjX2Fj dGlvbnNfYWJpLmgKQEAgLTEzNSw2ICsxMzUsNyBAQCBlbnVtIGludGVsX2d1Y19hY3Rpb24gewog CUlOVEVMX0dVQ19BQ1RJT05fU0VUX0NPTlRFWFRfUFJFRU1QVElPTl9USU1FT1VUID0gMHgxMDA3 LAogCUlOVEVMX0dVQ19BQ1RJT05fQ09OVEVYVF9SRVNFVF9OT1RJRklDQVRJT04gPSAweDEwMDgs CiAJSU5URUxfR1VDX0FDVElPTl9FTkdJTkVfRkFJTFVSRV9OT1RJRklDQVRJT04gPSAweDEwMDks CisJSU5URUxfR1VDX0FDVElPTl9TRVRVUF9QQ19HVUNSQyA9IDB4MzAwNCwKIAlJTlRFTF9HVUNf QUNUSU9OX0FVVEhFTlRJQ0FURV9IVUMgPSAweDQwMDAsCiAJSU5URUxfR1VDX0FDVElPTl9SRUdJ U1RFUl9DT05URVhUID0gMHg0NTAyLAogCUlOVEVMX0dVQ19BQ1RJT05fREVSRUdJU1RFUl9DT05U RVhUID0gMHg0NTAzLApAQCAtMTQ1LDYgKzE0NiwxMSBAQCBlbnVtIGludGVsX2d1Y19hY3Rpb24g ewogCUlOVEVMX0dVQ19BQ1RJT05fTElNSVQKIH07CiAKK2VudW0gaW50ZWxfZ3VjX3JjX29wdGlv bnMgeworCUlOVEVMX0dVQ1JDX0hPU1RfQ09OVFJPTCwKKwlJTlRFTF9HVUNSQ19GSVJNV0FSRV9D T05UUk9MLAorfTsKKwogZW51bSBpbnRlbF9ndWNfcHJlZW1wdF9vcHRpb25zIHsKIAlJTlRFTF9H VUNfUFJFRU1QVF9PUFRJT05fRFJPUF9XT1JLX1EgPSAweDQsCiAJSU5URUxfR1VDX1BSRUVNUFRf T1BUSU9OX0RST1BfU1VCTUlUX1EgPSAweDgsCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0v aTkxNS9ndC91Yy9pbnRlbF9ndWMuYyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L3VjL2ludGVs X2d1Yy5jCmluZGV4IDEzZDE2MjM1M2IxYS4uZmJmY2FlNzI3ZDdmIDEwMDY0NAotLS0gYS9kcml2 ZXJzL2dwdS9kcm0vaTkxNS9ndC91Yy9pbnRlbF9ndWMuYworKysgYi9kcml2ZXJzL2dwdS9kcm0v aTkxNS9ndC91Yy9pbnRlbF9ndWMuYwpAQCAtMTU5LDYgKzE1OSw3IEBAIHZvaWQgaW50ZWxfZ3Vj X2luaXRfZWFybHkoc3RydWN0IGludGVsX2d1YyAqZ3VjKQogCWludGVsX2d1Y19sb2dfaW5pdF9l YXJseSgmZ3VjLT5sb2cpOwogCWludGVsX2d1Y19zdWJtaXNzaW9uX2luaXRfZWFybHkoZ3VjKTsK IAlpbnRlbF9ndWNfc2xwY19pbml0X2Vhcmx5KCZndWMtPnNscGMpOworCWludGVsX2d1Y19yY19p bml0X2Vhcmx5KGd1Yyk7CiAKIAltdXRleF9pbml0KCZndWMtPnNlbmRfbXV0ZXgpOwogCXNwaW5f bG9ja19pbml0KCZndWMtPmlycV9sb2NrKTsKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9p OTE1L2d0L3VjL2ludGVsX2d1Yy5oIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3QvdWMvaW50ZWxf Z3VjLmgKaW5kZXggN2RhMTFhMGI2MDU5Li4yZTI3ZmU1OTc4NmIgMTAwNjQ0Ci0tLSBhL2RyaXZl cnMvZ3B1L2RybS9pOTE1L2d0L3VjL2ludGVsX2d1Yy5oCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9p OTE1L2d0L3VjL2ludGVsX2d1Yy5oCkBAIC01OSw2ICs1OSw4IEBAIHN0cnVjdCBpbnRlbF9ndWMg ewogCiAJYm9vbCBzdWJtaXNzaW9uX3N1cHBvcnRlZDsKIAlib29sIHN1Ym1pc3Npb25fc2VsZWN0 ZWQ7CisJYm9vbCByY19zdXBwb3J0ZWQ7CisJYm9vbCByY19zZWxlY3RlZDsKIAogCXN0cnVjdCBp OTE1X3ZtYSAqYWRzX3ZtYTsKIAlzdHJ1Y3QgX19ndWNfYWRzX2Jsb2IgKmFkc19ibG9iOwpkaWZm IC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3QvdWMvaW50ZWxfZ3VjX3JjLmMgYi9kcml2 ZXJzL2dwdS9kcm0vaTkxNS9ndC91Yy9pbnRlbF9ndWNfcmMuYwpuZXcgZmlsZSBtb2RlIDEwMDY0 NAppbmRleCAwMDAwMDAwMDAwMDAuLmZjODA1ZDQ2NmQ5OQotLS0gL2Rldi9udWxsCisrKyBiL2Ry aXZlcnMvZ3B1L2RybS9pOTE1L2d0L3VjL2ludGVsX2d1Y19yYy5jCkBAIC0wLDAgKzEsODAgQEAK Ky8vIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiBNSVQKKy8qCisgKiBDb3B5cmlnaHQgwqkgMjAy MSBJbnRlbCBDb3Jwb3JhdGlvbgorICovCisKKyNpbmNsdWRlICJpbnRlbF9ndWNfcmMuaCIKKyNp bmNsdWRlICJndC9pbnRlbF9ndC5oIgorI2luY2x1ZGUgImk5MTVfZHJ2LmgiCisKK3N0YXRpYyBi b29sIF9fZ3VjX3JjX3N1cHBvcnRlZChzdHJ1Y3QgaW50ZWxfZ3VjICpndWMpCit7CisJLyogR3VD IFJDIGlzIHVuYXZhaWxhYmxlIGZvciBwcmUtR2VuMTIgKi8KKwlyZXR1cm4gZ3VjLT5zdWJtaXNz aW9uX3N1cHBvcnRlZCAmJgorCQlHUkFQSElDU19WRVIoZ3VjX3RvX2d0KGd1YyktPmk5MTUpID49 IDEyOworfQorCitzdGF0aWMgYm9vbCBfX2d1Y19yY19zZWxlY3RlZChzdHJ1Y3QgaW50ZWxfZ3Vj ICpndWMpCit7CisJaWYgKCFpbnRlbF9ndWNfcmNfaXNfc3VwcG9ydGVkKGd1YykpCisJCXJldHVy biBmYWxzZTsKKworCXJldHVybiBndWMtPnN1Ym1pc3Npb25fc2VsZWN0ZWQ7Cit9CisKK3ZvaWQg aW50ZWxfZ3VjX3JjX2luaXRfZWFybHkoc3RydWN0IGludGVsX2d1YyAqZ3VjKQoreworCWd1Yy0+ cmNfc3VwcG9ydGVkID0gX19ndWNfcmNfc3VwcG9ydGVkKGd1Yyk7CisJZ3VjLT5yY19zZWxlY3Rl ZCA9IF9fZ3VjX3JjX3NlbGVjdGVkKGd1Yyk7Cit9CisKK3N0YXRpYyBpbnQgZ3VjX2FjdGlvbl9j b250cm9sX2d1Y3JjKHN0cnVjdCBpbnRlbF9ndWMgKmd1YywgYm9vbCBlbmFibGUpCit7CisJdTMy IHJjX21vZGUgPSBlbmFibGUgPyBJTlRFTF9HVUNSQ19GSVJNV0FSRV9DT05UUk9MIDoKKwkJCQlJ TlRFTF9HVUNSQ19IT1NUX0NPTlRST0w7CisJdTMyIGFjdGlvbltdID0geworCQlJTlRFTF9HVUNf QUNUSU9OX1NFVFVQX1BDX0dVQ1JDLAorCQlyY19tb2RlCisJfTsKKwlpbnQgcmV0OworCisJcmV0 ID0gaW50ZWxfZ3VjX3NlbmQoZ3VjLCBhY3Rpb24sIEFSUkFZX1NJWkUoYWN0aW9uKSk7CisJcmV0 ID0gcmV0ID4gMCA/IC1FUFJPVE8gOiByZXQ7CisKKwlyZXR1cm4gcmV0OworfQorCitzdGF0aWMg aW50IF9fZ3VjX3JjX2NvbnRyb2woc3RydWN0IGludGVsX2d1YyAqZ3VjLCBib29sIGVuYWJsZSkK K3sKKwlzdHJ1Y3QgaW50ZWxfZ3QgKmd0ID0gZ3VjX3RvX2d0KGd1Yyk7CisJc3RydWN0IGRybV9k ZXZpY2UgKmRybSA9ICZndWNfdG9fZ3QoZ3VjKS0+aTkxNS0+ZHJtOworCWludCByZXQ7CisKKwlp ZiAoIWludGVsX3VjX3VzZXNfZ3VjX3JjKCZndC0+dWMpKQorCQlyZXR1cm4gLUVPUE5PVFNVUFA7 CisKKwlpZiAoIWludGVsX2d1Y19pc19yZWFkeShndWMpKQorCQlyZXR1cm4gLUVJTlZBTDsKKwor CXJldCA9IGd1Y19hY3Rpb25fY29udHJvbF9ndWNyYyhndWMsIGVuYWJsZSk7CisJaWYgKHJldCkg eworCQlkcm1fZXJyKGRybSwgIkZhaWxlZCB0byAlcyBHdUMgUkMgKCVwZSlcbiIsCisJCQllbmFi bGVkaXNhYmxlKGVuYWJsZSksIEVSUl9QVFIocmV0KSk7CisJCXJldHVybiByZXQ7CisJfQorCisJ ZHJtX2luZm8oJmd0LT5pOTE1LT5kcm0sICJHdUMgUkM6ICVzXG4iLAorCQkgZW5hYmxlZGRpc2Fi bGVkKGVuYWJsZSkpOworCisJcmV0dXJuIDA7Cit9CisKK2ludCBpbnRlbF9ndWNfcmNfZW5hYmxl KHN0cnVjdCBpbnRlbF9ndWMgKmd1YykKK3sKKwlyZXR1cm4gX19ndWNfcmNfY29udHJvbChndWMs IHRydWUpOworfQorCitpbnQgaW50ZWxfZ3VjX3JjX2Rpc2FibGUoc3RydWN0IGludGVsX2d1YyAq Z3VjKQoreworCXJldHVybiBfX2d1Y19yY19jb250cm9sKGd1YywgZmFsc2UpOworfQpkaWZmIC0t Z2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3QvdWMvaW50ZWxfZ3VjX3JjLmggYi9kcml2ZXJz L2dwdS9kcm0vaTkxNS9ndC91Yy9pbnRlbF9ndWNfcmMuaApuZXcgZmlsZSBtb2RlIDEwMDY0NApp bmRleCAwMDAwMDAwMDAwMDAuLjU3ZTg2YzMzNzgzOAotLS0gL2Rldi9udWxsCisrKyBiL2RyaXZl cnMvZ3B1L2RybS9pOTE1L2d0L3VjL2ludGVsX2d1Y19yYy5oCkBAIC0wLDAgKzEsMzEgQEAKKy8q IFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiBNSVQgKi8KKy8qCisgKiBDb3B5cmlnaHQgwqkgMjAy MSBJbnRlbCBDb3Jwb3JhdGlvbgorICovCisKKyNpZm5kZWYgX0lOVEVMX0dVQ19SQ19IXworI2Rl ZmluZSBfSU5URUxfR1VDX1JDX0hfCisKKyNpbmNsdWRlICJpbnRlbF9ndWNfc3VibWlzc2lvbi5o IgorCit2b2lkIGludGVsX2d1Y19yY19pbml0X2Vhcmx5KHN0cnVjdCBpbnRlbF9ndWMgKmd1Yyk7 CisKK3N0YXRpYyBpbmxpbmUgYm9vbCBpbnRlbF9ndWNfcmNfaXNfc3VwcG9ydGVkKHN0cnVjdCBp bnRlbF9ndWMgKmd1YykKK3sKKwlyZXR1cm4gZ3VjLT5yY19zdXBwb3J0ZWQ7Cit9CisKK3N0YXRp YyBpbmxpbmUgYm9vbCBpbnRlbF9ndWNfcmNfaXNfd2FudGVkKHN0cnVjdCBpbnRlbF9ndWMgKmd1 YykKK3sKKwlyZXR1cm4gZ3VjLT5zdWJtaXNzaW9uX3NlbGVjdGVkICYmIGludGVsX2d1Y19yY19p c19zdXBwb3J0ZWQoZ3VjKTsKK30KKworc3RhdGljIGlubGluZSBib29sIGludGVsX2d1Y19yY19p c191c2VkKHN0cnVjdCBpbnRlbF9ndWMgKmd1YykKK3sKKwlyZXR1cm4gaW50ZWxfZ3VjX3N1Ym1p c3Npb25faXNfdXNlZChndWMpICYmIGludGVsX2d1Y19yY19pc193YW50ZWQoZ3VjKTsKK30KKwor aW50IGludGVsX2d1Y19yY19lbmFibGUoc3RydWN0IGludGVsX2d1YyAqZ3VjKTsKK2ludCBpbnRl bF9ndWNfcmNfZGlzYWJsZShzdHJ1Y3QgaW50ZWxfZ3VjICpndWMpOworCisjZW5kaWYKZGlmZiAt LWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L3VjL2ludGVsX3VjLmggYi9kcml2ZXJzL2dw dS9kcm0vaTkxNS9ndC91Yy9pbnRlbF91Yy5oCmluZGV4IDkyNWE1OGNhNmI5NC4uODY2YjQ2Mjgy MWMwIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9ndC91Yy9pbnRlbF91Yy5oCisr KyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L3VjL2ludGVsX3VjLmgKQEAgLTcsNiArNyw3IEBA CiAjZGVmaW5lIF9JTlRFTF9VQ19IXwogCiAjaW5jbHVkZSAiaW50ZWxfZ3VjLmgiCisjaW5jbHVk ZSAiaW50ZWxfZ3VjX3JjLmgiCiAjaW5jbHVkZSAiaW50ZWxfZ3VjX3N1Ym1pc3Npb24uaCIKICNp bmNsdWRlICJpbnRlbF9ndWNfc2xwYy5oIgogI2luY2x1ZGUgImludGVsX2h1Yy5oIgpAQCAtODUs NiArODYsNyBAQCB1Y19zdGF0ZV9jaGVja2VycyhndWMsIGd1Yyk7CiB1Y19zdGF0ZV9jaGVja2Vy cyhodWMsIGh1Yyk7CiB1Y19zdGF0ZV9jaGVja2VycyhndWMsIGd1Y19zdWJtaXNzaW9uKTsKIHVj X3N0YXRlX2NoZWNrZXJzKGd1YywgZ3VjX3NscGMpOwordWNfc3RhdGVfY2hlY2tlcnMoZ3VjLCBn dWNfcmMpOwogCiAjdW5kZWYgdWNfc3RhdGVfY2hlY2tlcnMKICN1bmRlZiBfX3VjX3N0YXRlX2No ZWNrZXIKLS0gCjIuMjUuMAoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0 b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50 ZWwtZ2Z4Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB724C432BE for ; Fri, 30 Jul 2021 02:02:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8B789603E9 for ; Fri, 30 Jul 2021 02:02:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 8B789603E9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B7B356F384; Fri, 30 Jul 2021 02:02:02 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3BBF06F37F; Fri, 30 Jul 2021 02:02:00 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10060"; a="200186043" X-IronPort-AV: E=Sophos;i="5.84,280,1620716400"; d="scan'208";a="200186043" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2021 19:01:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,280,1620716400"; d="scan'208";a="664637799" Received: from vbelgaum-ubuntu.fm.intel.com ([10.1.27.27]) by fmsmga006.fm.intel.com with ESMTP; 29 Jul 2021 19:01:59 -0700 From: Vinay Belgaumkar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 14/14] drm/i915/guc/rc: Setup and enable GuCRC feature Date: Thu, 29 Jul 2021 19:01:07 -0700 Message-Id: <20210730020107.31415-15-vinay.belgaumkar@intel.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20210730020107.31415-1-vinay.belgaumkar@intel.com> References: <20210730020107.31415-1-vinay.belgaumkar@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vinay Belgaumkar , Michal Wajdeczko Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This feature hands over the control of HW RC6 to the GuC. GuC decides when to put HW into RC6 based on it's internal busyness algorithms. GuCRC needs GuC submission to be enabled, and only supported on Gen12+ for now. When GuCRC is enabled, do not set HW RC6. Use a H2G message to tell GuC to enable GuCRC. When disabling RC6, tell GuC to revert RC6 control back to KMD. KMD is still responsible for enabling everything related to Coarse Power Gating though. v2: Address comments (Michal W) v3: Don't set hysterisis values when GuCRC is used (Matt Roper) v4: checkpatch() Reviewed-by: Michal Wajdeczko Signed-off-by: Vinay Belgaumkar --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_rc6.c | 47 +++++++---- .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 6 ++ drivers/gpu/drm/i915/gt/uc/intel_guc.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 + drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 80 +++++++++++++++++++ drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h | 31 +++++++ drivers/gpu/drm/i915/gt/uc/intel_uc.h | 2 + 8 files changed, 155 insertions(+), 15 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index d8eac4468df9..3fc17f20d88e 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -186,6 +186,7 @@ i915-y += gt/uc/intel_uc.o \ gt/uc/intel_guc_fw.o \ gt/uc/intel_guc_log.o \ gt/uc/intel_guc_log_debugfs.o \ + gt/uc/intel_guc_rc.o \ gt/uc/intel_guc_slpc.o \ gt/uc/intel_guc_submission.o \ gt/uc/intel_huc.o \ diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 259d7eb4e165..f6b914438a0b 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -62,20 +62,25 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) u32 pg_enable; int i; - /* 2b: Program RC6 thresholds.*/ - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); - set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); + /* + * With GuCRC, these parameters are set by GuC + */ + if (!intel_uc_uses_guc_rc(>->uc)) { + /* 2b: Program RC6 thresholds.*/ + set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); + set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ - for_each_engine(engine, rc6_to_gt(rc6), id) - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); + set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ + set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ + for_each_engine(engine, rc6_to_gt(rc6), id) + set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); - set(uncore, GUC_MAX_IDLE_COUNT, 0xA); + set(uncore, GUC_MAX_IDLE_COUNT, 0xA); - set(uncore, GEN6_RC_SLEEP, 0); + set(uncore, GEN6_RC_SLEEP, 0); - set(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ + set(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ + } /* * 2c: Program Coarse Power Gating Policies. @@ -98,11 +103,19 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60); set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60); - /* 3a: Enable RC6 */ - rc6->ctl_enable = - GEN6_RC_CTL_HW_ENABLE | - GEN6_RC_CTL_RC6_ENABLE | - GEN6_RC_CTL_EI_MODE(1); + /* 3a: Enable RC6 + * + * With GuCRC, we do not enable bit 31 of RC_CTL, + * thus allowing GuC to control RC6 entry/exit fully instead. + * We will not set the HW ENABLE and EI bits + */ + if (!intel_guc_rc_enable(>->uc.guc)) + rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE; + else + rc6->ctl_enable = + GEN6_RC_CTL_HW_ENABLE | + GEN6_RC_CTL_RC6_ENABLE | + GEN6_RC_CTL_EI_MODE(1); pg_enable = GEN9_RENDER_PG_ENABLE | @@ -513,6 +526,10 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6) { struct drm_i915_private *i915 = rc6_to_i915(rc6); struct intel_uncore *uncore = rc6_to_uncore(rc6); + struct intel_gt *gt = rc6_to_gt(rc6); + + /* Take control of RC6 back from GuC */ + intel_guc_rc_disable(>->uc.guc); intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); if (GRAPHICS_VER(i915) >= 9) diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h index ca538e5de940..8ff582222aff 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h @@ -135,6 +135,7 @@ enum intel_guc_action { INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT = 0x1007, INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008, INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009, + INTEL_GUC_ACTION_SETUP_PC_GUCRC = 0x3004, INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502, INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503, @@ -145,6 +146,11 @@ enum intel_guc_action { INTEL_GUC_ACTION_LIMIT }; +enum intel_guc_rc_options { + INTEL_GUCRC_HOST_CONTROL, + INTEL_GUCRC_FIRMWARE_CONTROL, +}; + enum intel_guc_preempt_options { INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4, INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8, diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index 13d162353b1a..fbfcae727d7f 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -159,6 +159,7 @@ void intel_guc_init_early(struct intel_guc *guc) intel_guc_log_init_early(&guc->log); intel_guc_submission_init_early(guc); intel_guc_slpc_init_early(&guc->slpc); + intel_guc_rc_init_early(guc); mutex_init(&guc->send_mutex); spin_lock_init(&guc->irq_lock); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index 7da11a0b6059..2e27fe59786b 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -59,6 +59,8 @@ struct intel_guc { bool submission_supported; bool submission_selected; + bool rc_supported; + bool rc_selected; struct i915_vma *ads_vma; struct __guc_ads_blob *ads_blob; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c new file mode 100644 index 000000000000..fc805d466d99 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2021 Intel Corporation + */ + +#include "intel_guc_rc.h" +#include "gt/intel_gt.h" +#include "i915_drv.h" + +static bool __guc_rc_supported(struct intel_guc *guc) +{ + /* GuC RC is unavailable for pre-Gen12 */ + return guc->submission_supported && + GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12; +} + +static bool __guc_rc_selected(struct intel_guc *guc) +{ + if (!intel_guc_rc_is_supported(guc)) + return false; + + return guc->submission_selected; +} + +void intel_guc_rc_init_early(struct intel_guc *guc) +{ + guc->rc_supported = __guc_rc_supported(guc); + guc->rc_selected = __guc_rc_selected(guc); +} + +static int guc_action_control_gucrc(struct intel_guc *guc, bool enable) +{ + u32 rc_mode = enable ? INTEL_GUCRC_FIRMWARE_CONTROL : + INTEL_GUCRC_HOST_CONTROL; + u32 action[] = { + INTEL_GUC_ACTION_SETUP_PC_GUCRC, + rc_mode + }; + int ret; + + ret = intel_guc_send(guc, action, ARRAY_SIZE(action)); + ret = ret > 0 ? -EPROTO : ret; + + return ret; +} + +static int __guc_rc_control(struct intel_guc *guc, bool enable) +{ + struct intel_gt *gt = guc_to_gt(guc); + struct drm_device *drm = &guc_to_gt(guc)->i915->drm; + int ret; + + if (!intel_uc_uses_guc_rc(>->uc)) + return -EOPNOTSUPP; + + if (!intel_guc_is_ready(guc)) + return -EINVAL; + + ret = guc_action_control_gucrc(guc, enable); + if (ret) { + drm_err(drm, "Failed to %s GuC RC (%pe)\n", + enabledisable(enable), ERR_PTR(ret)); + return ret; + } + + drm_info(>->i915->drm, "GuC RC: %s\n", + enableddisabled(enable)); + + return 0; +} + +int intel_guc_rc_enable(struct intel_guc *guc) +{ + return __guc_rc_control(guc, true); +} + +int intel_guc_rc_disable(struct intel_guc *guc) +{ + return __guc_rc_control(guc, false); +} diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h new file mode 100644 index 000000000000..57e86c337838 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2021 Intel Corporation + */ + +#ifndef _INTEL_GUC_RC_H_ +#define _INTEL_GUC_RC_H_ + +#include "intel_guc_submission.h" + +void intel_guc_rc_init_early(struct intel_guc *guc); + +static inline bool intel_guc_rc_is_supported(struct intel_guc *guc) +{ + return guc->rc_supported; +} + +static inline bool intel_guc_rc_is_wanted(struct intel_guc *guc) +{ + return guc->submission_selected && intel_guc_rc_is_supported(guc); +} + +static inline bool intel_guc_rc_is_used(struct intel_guc *guc) +{ + return intel_guc_submission_is_used(guc) && intel_guc_rc_is_wanted(guc); +} + +int intel_guc_rc_enable(struct intel_guc *guc); +int intel_guc_rc_disable(struct intel_guc *guc); + +#endif diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h b/drivers/gpu/drm/i915/gt/uc/intel_uc.h index 925a58ca6b94..866b462821c0 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h @@ -7,6 +7,7 @@ #define _INTEL_UC_H_ #include "intel_guc.h" +#include "intel_guc_rc.h" #include "intel_guc_submission.h" #include "intel_guc_slpc.h" #include "intel_huc.h" @@ -85,6 +86,7 @@ uc_state_checkers(guc, guc); uc_state_checkers(huc, huc); uc_state_checkers(guc, guc_submission); uc_state_checkers(guc, guc_slpc); +uc_state_checkers(guc, guc_rc); #undef uc_state_checkers #undef __uc_state_checker -- 2.25.0