From: ira.weiny@intel.com
To: Dan Williams <dan.j.williams@intel.com>
Cc: Ira Weiny <ira.weiny@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ben Widawsky <ben.widawsky@intel.com>,
linux-cxl@vger.kernel.org
Subject: [PATCH 0/9] CDAT/DSMAS reading and cleanups
Date: Wed, 27 Oct 2021 15:40:34 -0700 [thread overview]
Message-ID: <20211027224043.3551125-1-ira.weiny@intel.com> (raw)
In-Reply-To: <20210617221620.1904031-4-ira.weiny@intel.com>
From: Ira Weiny <ira.weiny@intel.com>
This really should be 2 series and a single patch for the cxl_mem change.
But for internal review I'm just going to throw it out on email to see what
others think.
Here are the 3 cover letters.
<Documentation>
The auxiliary device documentation was not wrong but it was a bit difficult to
follow. Add clarifications to ensure that details are not missed.
</Documentation>
<CDAT/DSMAS>
Read CDAT and DSMAS data from the device.
This work was built on Jonathan's V4 series here[1]. The big change is a
conversion to an Auxiliary bus infrastructure which allows the DOE code to be
in a separate driver object which is attached to any DOE devices which are
created by the CXL device.
Other devices can then create DOE devices and have the doe driver automatically
attach to this functionality. Furthermore, user space control of DOE mailboxes
will be easier because of the separation from the parent device control.
[1] https://lore.kernel.org/linux-cxl/20210524133938.2815206-1-Jonathan.Cameron@huawei.com
</CDAT/DSMAS>
<Single patch so no cover for the cxlmem change.>
Ira Weiny (5):
Documentation/auxiliary_bus: Clarify auxiliary_device creation
Documentation/auxiliary_bus: Clarify match_name
Documentation/auxiliary_bus: Update Auxiliary device lifespan
cxl/cdat: Parse out DSMASS data from CDAT table
cxl/cxlmem: Change struct cxl_mem to a more descriptive name
Jonathan Cameron (4):
PCI: Add vendor ID for the PCI SIG
PCI/DOE: Add Data Object Exchange Aux Driver
cxl/pci: Add DOE Auxiliary Devices
cxl/mem: Add CDAT table reading from DOE
Documentation/driver-api/auxiliary_bus.rst | 137 +++-
drivers/cxl/Kconfig | 1 +
drivers/cxl/cdat.h | 81 +++
drivers/cxl/core/mbox.c | 160 ++---
drivers/cxl/core/memdev.c | 205 +++++-
drivers/cxl/cxl.h | 20 +
drivers/cxl/cxlmem.h | 79 ++-
drivers/cxl/pci.c | 355 ++++++++---
drivers/cxl/pmem.c | 32 +-
drivers/pci/Kconfig | 11 +
drivers/pci/Makefile | 3 +
drivers/pci/doe.c | 704 +++++++++++++++++++++
include/linux/pci-doe.h | 63 ++
include/linux/pci_ids.h | 1 +
include/uapi/linux/pci_regs.h | 29 +-
tools/testing/cxl/test/mem.c | 50 +-
16 files changed, 1670 insertions(+), 261 deletions(-)
create mode 100644 drivers/cxl/cdat.h
create mode 100644 drivers/pci/doe.c
create mode 100644 include/linux/pci-doe.h
--
2.28.0.rc0.12.gb6a658bd00c9
next prev parent reply other threads:[~2021-10-27 22:40 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-17 22:16 [PATCH V2 0/3] Query and use Partition Info ira.weiny
2021-06-17 22:16 ` [PATCH V2 1/3] cxl/pci: Store memory capacity values ira.weiny
2021-06-18 13:40 ` Jonathan Cameron
2021-06-17 22:16 ` [PATCH V2 2/3] cxl/mem: Account for partitionable space in ram/pmem ranges ira.weiny
2021-06-18 13:59 ` Jonathan Cameron
2021-06-18 16:30 ` Ira Weiny
2021-06-18 16:31 ` [PATCH V3] " ira.weiny
2021-06-18 16:58 ` Ben Widawsky
2021-06-18 18:48 ` Ira Weiny
2021-06-18 19:32 ` Ben Widawsky
2021-08-11 1:49 ` [PATCH v4 2/3] " Dan Williams
2021-06-17 22:16 ` [PATCH V2 3/3] cxl/mem: Adjust ram/pmem range to represent DPA ranges ira.weiny
2021-06-18 14:03 ` Jonathan Cameron
2021-06-21 19:54 ` [PATCH V3] " ira.weiny
2021-10-27 22:40 ` ira.weiny [this message]
2021-10-27 22:40 ` [PATCH 1/9] Documentation/auxiliary_bus: Clarify auxiliary_device creation ira.weiny
2021-10-27 22:40 ` [PATCH 2/9] Documentation/auxiliary_bus: Clarify match_name ira.weiny
2021-10-27 22:40 ` [PATCH 3/9] Documentation/auxiliary_bus: Update Auxiliary device lifespan ira.weiny
2021-10-27 22:43 ` [PATCH 0/9] CDAT/DSMAS reading and cleanups Ira Weiny
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