From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 84F42C19F2A for ; Thu, 11 Aug 2022 14:38:47 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AA7FD8494A; Thu, 11 Aug 2022 16:38:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=suse.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=suse.de header.i=@suse.de header.b="PbQwAEWI"; dkim=permerror (0-bit key) header.d=suse.de header.i=@suse.de header.b="RFyid/g0"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4B4C584945; Thu, 11 Aug 2022 16:38:43 +0200 (CEST) Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.220.28]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B930D84963 for ; Thu, 11 Aug 2022 16:38:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=suse.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=msuchanek@suse.de Received: from relay2.suse.de (relay2.suse.de [149.44.160.134]) by smtp-out1.suse.de (Postfix) with ESMTP id 7B3E438C7C; Thu, 11 Aug 2022 14:38:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1660228716; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rspHihV5M5mTFqOkugJCXScwBSV9X0NBkI/crPMhaQY=; b=PbQwAEWI5JHr35/CaqXnMUXX3XwqogVgvlL6SmCBsIIpDTqrW6Jh5634IrR2Xc/SJ90mQq AkvZ2/9kb8vy8kalQ92gJKaJx5R2pt4iNDLY15u8PZ/T3qPAxpv6NbqmOpf1016EdyZ/ei 4lZ89TxmDtODvE07FtJODh6GTrZ0pPU= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1660228716; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rspHihV5M5mTFqOkugJCXScwBSV9X0NBkI/crPMhaQY=; b=RFyid/g0Tq+WSCUs8jKxW0uMxTYnYnUjdtnq0boFOZXLoy39tTcjXbpFJLwD2kMZ/k0sjv 71wWgs3ZrwOZhJAw== Received: from kitsune.suse.cz (kitsune.suse.cz [10.100.12.127]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by relay2.suse.de (Postfix) with ESMTPS id B18C12C145; Thu, 11 Aug 2022 14:38:35 +0000 (UTC) Date: Thu, 11 Aug 2022 16:38:34 +0200 From: Michal =?iso-8859-1?Q?Such=E1nek?= To: Lee Jones Cc: u-boot@lists.denx.de, sjg@chromium.org, philipp.tomsich@vrull.eu, kever.yang@rock-chips.com, YouMin Chen , Xavier Drudis Ferran Subject: Re: [PATCH 3/3] ram: rk3399: Conduct memory training at 400MHz Message-ID: <20220811143834.GX17705@kitsune.suse.cz> References: <20220811075848.1791050-1-lee@kernel.org> <20220811075848.1791050-4-lee@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220811075848.1791050-4-lee@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Thu, Aug 11, 2022 at 08:58:48AM +0100, Lee Jones wrote: > Currently the default initialisation frequency is 50MHz. Although > this does appear to be suitable for some LPDDR4 RAM chips, training at > this low frequency has been seen to cause Column errors, leading to > Capacity check errors on others. > > Here we force RAM initialisation to happen at 400MHz before ramping up > to the final value running value of 800MHz after everything has been > successfully configured. > > Link: https://lore.kernel.org/u-boot/Yo4v3jUeHXTovjOH@google.com/ > Suggested-by: YouMin Chen > Signed-off-by: Lee Jones > Tested-by: Xavier Drudis Ferran Also does not cause any regression on a Pinebook Pro Tested-by: Michal Suchánek Thanks Michal > Reviewed-by: Kever Yang > --- > drivers/ram/rockchip/sdram_rk3399.c | 36 +++++++++++++++++------------ > 1 file changed, 21 insertions(+), 15 deletions(-) > > diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c > index 34d6c93f95..b05c5925d5 100644 > --- a/drivers/ram/rockchip/sdram_rk3399.c > +++ b/drivers/ram/rockchip/sdram_rk3399.c > @@ -85,7 +85,7 @@ struct sdram_rk3399_ops { > int (*data_training_first)(struct dram_info *dram, u32 channel, u8 rank, > struct rk3399_sdram_params *sdram); > int (*set_rate_index)(struct dram_info *dram, > - struct rk3399_sdram_params *params); > + struct rk3399_sdram_params *params, u32 ctl_fn); > void (*modify_param)(const struct chan_info *chan, > struct rk3399_sdram_params *params); > struct rk3399_sdram_params * > @@ -1644,7 +1644,8 @@ static int data_training_first(struct dram_info *dram, u32 channel, u8 rank, > } > > static int switch_to_phy_index1(struct dram_info *dram, > - struct rk3399_sdram_params *params) > + struct rk3399_sdram_params *params, > + u32 unused) > { > u32 channel; > u32 *denali_phy; > @@ -2539,26 +2540,25 @@ static int lpddr4_set_ctl(struct dram_info *dram, > } > > static int lpddr4_set_rate(struct dram_info *dram, > - struct rk3399_sdram_params *params) > + struct rk3399_sdram_params *params, > + u32 ctl_fn) > { > - u32 ctl_fn; > u32 phy_fn; > > - for (ctl_fn = 0; ctl_fn < 2; ctl_fn++) { > - phy_fn = lpddr4_get_phy_fn(params, ctl_fn); > + phy_fn = lpddr4_get_phy_fn(params, ctl_fn); > > - lpddr4_set_phy(dram, params, phy_fn, &dfs_cfgs_lpddr4[ctl_fn]); > - lpddr4_set_ctl(dram, params, ctl_fn, > - dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq); > + lpddr4_set_phy(dram, params, phy_fn, &dfs_cfgs_lpddr4[ctl_fn]); > + lpddr4_set_ctl(dram, params, ctl_fn, > + dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq); > > - if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) > - printf("%s: change freq to %dMHz %d, %d\n", __func__, > - dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq / MHz, > - ctl_fn, phy_fn); > - } > + if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) > + printf("%s: change freq to %dMHz %d, %d\n", __func__, > + dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq / MHz, > + ctl_fn, phy_fn); > > return 0; > } > + > #endif /* CONFIG_RAM_RK3399_LPDDR4 */ > > /* CS0,n=1 > @@ -2955,6 +2955,12 @@ static int sdram_init(struct dram_info *dram, > params->ch[ch].cap_info.rank = rank; > } > > +#if defined(CONFIG_RAM_RK3399_LPDDR4) > + /* LPDDR4 needs to be trained at 400MHz */ > + lpddr4_set_rate(dram, params, 0); > + params->base.ddr_freq = dfs_cfgs_lpddr4[0].base.ddr_freq / MHz; > +#endif > + > params->base.num_channels = 0; > for (channel = 0; channel < 2; channel++) { > const struct chan_info *chan = &dram->chan[channel]; > @@ -3005,7 +3011,7 @@ static int sdram_init(struct dram_info *dram, > params->base.stride = calculate_stride(params); > dram_all_config(dram, params); > > - ret = dram->ops->set_rate_index(dram, params); > + ret = dram->ops->set_rate_index(dram, params, 1); > if (ret) > return ret; > > -- > 2.37.1.559.g78731f0fdb-goog >