* [igt-dev] [PATCH i-g-t 0/5] IGT bits for small-bar
@ 2023-03-29 11:56 Matthew Auld
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 1/5] xe: sync small-bar uapi Matthew Auld
` (7 more replies)
0 siblings, 8 replies; 16+ messages in thread
From: Matthew Auld @ 2023-03-29 11:56 UTC (permalink / raw
To: igt-dev
small-bar IGT changes for Xe.
Kernel: https://patchwork.freedesktop.org/series/115515/
--
2.39.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 1/5] xe: sync small-bar uapi
2023-03-29 11:56 [igt-dev] [PATCH i-g-t 0/5] IGT bits for small-bar Matthew Auld
@ 2023-03-29 11:56 ` Matthew Auld
2023-04-02 23:46 ` Gwan-gyeong Mun
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 2/5] lib/xe: add visible vram helpers Matthew Auld
` (6 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Matthew Auld @ 2023-03-29 11:56 UTC (permalink / raw
To: igt-dev
We need a couple new fields for the region query and the new flag to
ensure the buffer is CPU accessible.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
include/drm-uapi/xe_drm.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
index 593b01ba..441b377b 100644
--- a/include/drm-uapi/xe_drm.h
+++ b/include/drm-uapi/xe_drm.h
@@ -169,7 +169,9 @@ struct drm_xe_query_mem_usage {
__u32 max_page_size;
__u64 total_size;
__u64 used;
- __u64 reserved[8];
+ __u64 cpu_visible_size;
+ __u64 cpu_visible_used;
+ __u64 reserved[6];
} regions[];
};
@@ -270,6 +272,7 @@ struct drm_xe_gem_create {
*/
#define XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24)
#define XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25)
+#define XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (0x1 << 26)
__u32 flags;
/**
--
2.39.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 2/5] lib/xe: add visible vram helpers
2023-03-29 11:56 [igt-dev] [PATCH i-g-t 0/5] IGT bits for small-bar Matthew Auld
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 1/5] xe: sync small-bar uapi Matthew Auld
@ 2023-03-29 11:56 ` Matthew Auld
2023-04-03 9:18 ` Gwan-gyeong Mun
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 3/5] tests/xe: handle small-bar systems Matthew Auld
` (5 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Matthew Auld @ 2023-03-29 11:56 UTC (permalink / raw
To: igt-dev
Add helpers for object creation and querying the cpu_visible related bits.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
lib/xe/xe_query.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++-
lib/xe/xe_query.h | 6 +++++
2 files changed, 74 insertions(+), 1 deletion(-)
diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index f281bc4a..48a413cd 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -140,6 +140,17 @@ static uint64_t gt_vram_size(const struct drm_xe_query_mem_usage *mem_usage,
return 0;
}
+static uint64_t gt_visible_vram_size(const struct drm_xe_query_mem_usage *mem_usage,
+ const struct drm_xe_query_gts *gts, int gt)
+{
+ int region_idx = ffs(native_region_for_gt(gts, gt)) - 1;
+
+ if (XE_IS_CLASS_VRAM(&mem_usage->regions[region_idx]))
+ return mem_usage->regions[region_idx].cpu_visible_size;
+
+ return 0;
+}
+
static bool __mem_has_vram(struct drm_xe_query_mem_usage *mem_usage)
{
for (int i = 0; i < mem_usage->num_regions; i++)
@@ -246,9 +257,14 @@ struct xe_device *xe_device_get(int fd)
xe_dev->hw_engines = xe_query_engines_new(fd, &xe_dev->number_hw_engines);
xe_dev->mem_usage = xe_query_mem_usage_new(fd);
xe_dev->vram_size = calloc(xe_dev->number_gt, sizeof(*xe_dev->vram_size));
- for (int gt = 0; gt < xe_dev->number_gt; gt++)
+ xe_dev->visible_vram_size = calloc(xe_dev->number_gt, sizeof(*xe_dev->visible_vram_size));
+ for (int gt = 0; gt < xe_dev->number_gt; gt++) {
xe_dev->vram_size[gt] = gt_vram_size(xe_dev->mem_usage,
xe_dev->gts, gt);
+ xe_dev->visible_vram_size[gt] =
+ gt_visible_vram_size(xe_dev->mem_usage,
+ xe_dev->gts, gt);
+ }
xe_dev->default_alignment = __mem_default_alignment(xe_dev->mem_usage);
xe_dev->has_vram = __mem_has_vram(xe_dev->mem_usage);
@@ -383,6 +399,20 @@ uint64_t vram_memory(int fd, int gt)
return native_region_for_gt(xe_dev->gts, gt);
}
+/**
+ * visible_vram_memory:
+ * @fd: xe device fd
+ * @gt: gt id
+ *
+ * Returns vram memory bitmask for xe device @fd and @gt id, with
+ * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM also set, to ensure that CPU access is
+ * possible.
+ */
+uint64_t visible_vram_memory(int fd, int gt)
+{
+ return vram_memory(fd, gt) | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
+}
+
/**
* vram_if_possible:
* @fd: xe device fd
@@ -400,6 +430,25 @@ uint64_t vram_if_possible(int fd, int gt)
return vram ? vram : system_memory;
}
+/**
+ * visible_vram_if_possible:
+ * @fd: xe device fd
+ * @gt: gt id
+ *
+ * Returns vram memory bitmask for xe device @fd and @gt id or system memory if
+ * there's no vram memory available for @gt. Also attaches the
+ * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM to ensure that CPU access is possible
+ * when using vram.
+ */
+uint64_t visible_vram_if_possible(int fd, int gt)
+{
+ uint64_t regions = all_memory_regions(fd);
+ uint64_t system_memory = regions & 0x1;
+ uint64_t vram = regions & (0x2 << gt);
+
+ return vram ? vram | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM : system_memory;
+}
+
/**
* xe_hw_engines:
* @fd: xe device fd
@@ -459,6 +508,23 @@ uint64_t xe_vram_size(int fd, int gt)
return xe_dev->vram_size[gt];
}
+/**
+ * xe_visible_vram_size:
+ * @fd: xe device fd
+ * @gt: gt
+ *
+ * Returns size of visible vram of xe device @fd.
+ */
+uint64_t xe_visible_vram_size(int fd, int gt)
+{
+ struct xe_device *xe_dev;
+
+ xe_dev = find_in_cache(fd);
+ igt_assert(xe_dev);
+
+ return xe_dev->visible_vram_size[gt];
+}
+
/**
* xe_get_default_alignment:
* @fd: xe device fd
@@ -475,6 +541,7 @@ xe_dev_FN(xe_get_default_alignment, default_alignment, uint32_t);
*/
xe_dev_FN(xe_va_bits, va_bits, uint32_t);
+
/**
* xe_dev_id:
* @fd: xe device fd
diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
index 3a00ecd1..5aa5b402 100644
--- a/lib/xe/xe_query.h
+++ b/lib/xe/xe_query.h
@@ -47,6 +47,9 @@ struct xe_device {
/** @vram_size: array of vram sizes for all gts */
uint64_t *vram_size;
+ /** @visible_vram_size: array of visible vram sizes for all gts */
+ uint64_t *visible_vram_size;
+
/** @default_alignment: safe alignment regardless region location */
uint32_t default_alignment;
@@ -76,13 +79,16 @@ unsigned int xe_number_gt(int fd);
uint64_t all_memory_regions(int fd);
uint64_t system_memory(int fd);
uint64_t vram_memory(int fd, int gt);
+uint64_t visible_vram_memory(int fd, int gt);
uint64_t vram_if_possible(int fd, int gt);
+uint64_t visible_vram_if_possible(int fd, int gt);
struct drm_xe_engine_class_instance *xe_hw_engines(int fd);
struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx);
unsigned int xe_number_hw_engines(int fd);
bool xe_has_vram(int fd);
//uint64_t xe_vram_size(int fd);
uint64_t xe_vram_size(int fd, int gt);
+uint64_t xe_visible_vram_size(int fd, int gt);
uint32_t xe_get_default_alignment(int fd);
uint32_t xe_va_bits(int fd);
uint16_t xe_dev_id(int fd);
--
2.39.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 3/5] tests/xe: handle small-bar systems
2023-03-29 11:56 [igt-dev] [PATCH i-g-t 0/5] IGT bits for small-bar Matthew Auld
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 1/5] xe: sync small-bar uapi Matthew Auld
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 2/5] lib/xe: add visible vram helpers Matthew Auld
@ 2023-03-29 11:56 ` Matthew Auld
2023-04-05 12:53 ` Gwan-gyeong Mun
2023-05-17 17:03 ` Kamil Konieczny
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 4/5] tests/xe/query: extend for CPU visible accounting Matthew Auld
` (4 subsequent siblings)
7 siblings, 2 replies; 16+ messages in thread
From: Matthew Auld @ 2023-03-29 11:56 UTC (permalink / raw
To: igt-dev
Convert all the existing tests that require CPU access.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
lib/xe/xe_spin.c | 3 ++-
tests/xe/xe_dma_buf_sync.c | 3 ++-
tests/xe/xe_evict.c | 32 +++++++++++++++++++-------------
tests/xe/xe_exec_balancer.c | 6 +++---
tests/xe/xe_exec_basic.c | 19 ++++++++++---------
tests/xe/xe_exec_compute_mode.c | 4 ++--
tests/xe/xe_exec_fault_mode.c | 12 ++++++++----
tests/xe/xe_exec_reset.c | 13 ++++++++-----
tests/xe/xe_exec_threads.c | 9 ++++++---
tests/xe/xe_guc_pc.c | 3 ++-
tests/xe/xe_mmap.c | 4 ++--
tests/xe/xe_pm.c | 3 ++-
tests/xe/xe_prime_self_import.c | 8 ++++----
tests/xe/xe_vm.c | 21 ++++++++++++++-------
14 files changed, 84 insertions(+), 56 deletions(-)
diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 856d0ba2..3266905c 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -100,7 +100,8 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
vm = xe_vm_create(fd, 0, 0);
- bo = xe_bo_create(fd, hwe->gt_id, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size,
+ visible_vram_if_possible(fd, hwe->gt_id));
spin = xe_bo_map(fd, bo, 0x1000);
xe_vm_bind_sync(fd, vm, bo, 0, addr, bo_size);
diff --git a/tests/xe/xe_dma_buf_sync.c b/tests/xe/xe_dma_buf_sync.c
index 8b97480a..3b4ee6bb 100644
--- a/tests/xe/xe_dma_buf_sync.c
+++ b/tests/xe/xe_dma_buf_sync.c
@@ -122,7 +122,8 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0,
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd[0]),
xe_get_default_alignment(fd[0]));
for (i = 0; i < n_bo; ++i) {
- bo[i] = xe_bo_create(fd[0], hwe0->gt_id, 0, bo_size);
+ bo[i] = xe_bo_create_flags(fd[0], 0, bo_size,
+ visible_vram_if_possible(fd[0], hwe0->gt_id));
dma_buf_fd[i] = prime_handle_to_fd(fd[0], bo[i]);
import_bo[i] = prime_fd_to_handle(fd[1], dma_buf_fd[i]);
diff --git a/tests/xe/xe_evict.c b/tests/xe/xe_evict.c
index eddbbd6f..26ed63de 100644
--- a/tests/xe/xe_evict.c
+++ b/tests/xe/xe_evict.c
@@ -98,15 +98,17 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci,
i < n_execs / 8 ? 0 : vm;
if (flags & MULTI_VM) {
- __bo = bo[i] = xe_bo_create(fd, eci->gt_id, 0,
- bo_size);
+ __bo = bo[i] = xe_bo_create_flags(fd, 0,
+ bo_size,
+ visible_vram_memory(fd, eci->gt_id));
} else if (flags & THREADED) {
- __bo = bo[i] = xe_bo_create(fd, eci->gt_id, vm,
- bo_size);
+ __bo = bo[i] = xe_bo_create_flags(fd, vm,
+ bo_size,
+ visible_vram_memory(fd, eci->gt_id));
} else {
__bo = bo[i] = xe_bo_create_flags(fd, _vm,
bo_size,
- vram_memory(fd, eci->gt_id) |
+ visible_vram_memory(fd, eci->gt_id) |
system_memory(fd));
}
} else {
@@ -281,16 +283,17 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci,
i < n_execs / 8 ? 0 : vm;
if (flags & MULTI_VM) {
- __bo = bo[i] = xe_bo_create(fd, eci->gt_id,
- 0, bo_size);
+ __bo = bo[i] = xe_bo_create_flags(fd, 0,
+ bo_size,
+ visible_vram_memory(fd, eci->gt_id));
} else if (flags & THREADED) {
- __bo = bo[i] = xe_bo_create(fd, eci->gt_id,
- vm, bo_size);
+ __bo = bo[i] = xe_bo_create_flags(fd, vm,
+ bo_size,
+ visible_vram_memory(fd, eci->gt_id));
} else {
__bo = bo[i] = xe_bo_create_flags(fd, _vm,
bo_size,
- vram_memory(fd, eci->gt_id) |
- system_memory(fd));
+ visible_vram_memory(fd, eci->gt_id));
}
} else {
__bo = bo[i % (n_execs / 2)];
@@ -455,7 +458,10 @@ threads(int fd, struct drm_xe_engine_class_instance *eci,
static uint64_t calc_bo_size(uint64_t vram_size, int mul, int div)
{
- return (ALIGN(vram_size, 0x40000000) * mul) / div;
+ if (vram_size >= 0x40000000)
+ return (ALIGN(vram_size, 0x40000000) * mul) / div;
+ else
+ return (ALIGN(vram_size, 0x10000000) * mul) / div; /* small-bar */
}
/**
@@ -670,7 +676,7 @@ igt_main
fd = drm_open_driver(DRIVER_XE);
xe_device_get(fd);
igt_require(xe_has_vram(fd));
- vram_size = xe_vram_size(fd, 0);
+ vram_size = xe_visible_vram_size(fd, 0);
igt_assert(vram_size);
xe_for_each_hw_engine(fd, hwe)
diff --git a/tests/xe/xe_exec_balancer.c b/tests/xe/xe_exec_balancer.c
index f3341a99..766e834c 100644
--- a/tests/xe/xe_exec_balancer.c
+++ b/tests/xe/xe_exec_balancer.c
@@ -70,7 +70,7 @@ static void test_all_active(int fd, int gt, int class)
bo_size = sizeof(*data) * num_placements;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
- bo = xe_bo_create(fd, gt, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < num_placements; i++) {
@@ -229,7 +229,7 @@ test_exec(int fd, int gt, int class, int n_engines, int n_execs,
}
memset(data, 0, bo_size);
} else {
- bo = xe_bo_create(fd, gt, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
data = xe_bo_map(fd, bo, bo_size);
}
@@ -454,7 +454,7 @@ test_cm(int fd, int gt, int class, int n_engines, int n_execs,
igt_assert(data);
}
} else {
- bo = xe_bo_create(fd, gt, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
diff --git a/tests/xe/xe_exec_basic.c b/tests/xe/xe_exec_basic.c
index 2a3cebd3..5e09e4a0 100644
--- a/tests/xe/xe_exec_basic.c
+++ b/tests/xe/xe_exec_basic.c
@@ -129,15 +129,16 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
}
memset(data, 0, bo_size);
} else {
- if (flags & DEFER_ALLOC) {
- bo = xe_bo_create_flags(fd, n_vm == 1 ? vm[0] : 0,
- bo_size,
- vram_if_possible(fd, eci->gt_id) |
- XE_GEM_CREATE_FLAG_DEFER_BACKING);
- } else {
- bo = xe_bo_create(fd, eci->gt_id, n_vm == 1 ? vm[0] : 0,
- bo_size);
- }
+ uint32_t bo_flags;
+
+ bo_flags = 0;
+ if (bo_flags & DEFER_ALLOC)
+ bo_flags |= XE_GEM_CREATE_FLAG_DEFER_BACKING;
+
+ bo = xe_bo_create_flags(fd, n_vm == 1 ? vm[0] : 0,
+ bo_size,
+ visible_vram_if_possible(fd, eci->gt_id) |
+ bo_flags);
if (!(flags & DEFER_BIND))
data = xe_bo_map(fd, bo, bo_size);
}
diff --git a/tests/xe/xe_exec_compute_mode.c b/tests/xe/xe_exec_compute_mode.c
index 60713a95..b06acd9b 100644
--- a/tests/xe/xe_exec_compute_mode.c
+++ b/tests/xe/xe_exec_compute_mode.c
@@ -152,8 +152,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
igt_assert(data);
}
} else {
- bo = xe_bo_create(fd, eci->gt_id, flags & VM_FOR_BO ? vm : 0,
- bo_size);
+ bo = xe_bo_create_flags(fd, flags & VM_FOR_BO ? vm : 0,
+ bo_size, visible_vram_if_possible(fd, eci->gt_id));
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
diff --git a/tests/xe/xe_exec_fault_mode.c b/tests/xe/xe_exec_fault_mode.c
index b5d924a3..95eacfd5 100644
--- a/tests/xe/xe_exec_fault_mode.c
+++ b/tests/xe/xe_exec_fault_mode.c
@@ -157,9 +157,11 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
} else {
if (flags & PREFETCH)
bo = xe_bo_create_flags(fd, 0, bo_size,
- all_memory_regions(fd));
+ all_memory_regions(fd) |
+ visible_vram_if_possible(fd, 0));
else
- bo = xe_bo_create(fd, eci->gt_id, 0, bo_size);
+ bo = xe_bo_create_flags(fd, 0, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
@@ -390,8 +392,10 @@ test_atomic(int fd, struct drm_xe_engine_class_instance *eci,
addr_wait = addr + bo_size;
bo = xe_bo_create_flags(fd, vm, bo_size,
- all_memory_regions(fd));
- bo_wait = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+ all_memory_regions(fd) |
+ visible_vram_if_possible(fd, 0));
+ bo_wait = xe_bo_create_flags(fd, vm, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
data = xe_bo_map(fd, bo, bo_size);
wait = xe_bo_map(fd, bo_wait, bo_size);
ptr = &data[0].data;
diff --git a/tests/xe/xe_exec_reset.c b/tests/xe/xe_exec_reset.c
index 57dc90dd..d171b3b3 100644
--- a/tests/xe/xe_exec_reset.c
+++ b/tests/xe/xe_exec_reset.c
@@ -51,7 +51,8 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci)
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
spin = xe_bo_map(fd, bo, bo_size);
engine = xe_engine_create(fd, vm, eci, 0);
@@ -197,7 +198,7 @@ test_balancer(int fd, int gt, int class, int n_engines, int n_execs,
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- bo = xe_bo_create(fd, gt, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < n_engines; i++) {
@@ -398,7 +399,8 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < n_engines; i++) {
@@ -577,7 +579,8 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci,
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
data = xe_bo_map(fd, bo, bo_size);
memset(data, 0, bo_size);
@@ -710,7 +713,7 @@ static void submit_jobs(struct gt_thread_data *t)
uint32_t bo;
uint32_t *data;
- bo = xe_bo_create(fd, 0, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
data = xe_bo_map(fd, bo, bo_size);
data[0] = MI_BATCH_BUFFER_END;
diff --git a/tests/xe/xe_exec_threads.c b/tests/xe/xe_exec_threads.c
index c34d8aec..1d7534e5 100644
--- a/tests/xe/xe_exec_threads.c
+++ b/tests/xe/xe_exec_threads.c
@@ -107,7 +107,8 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
igt_assert(data);
}
} else {
- bo = xe_bo_create(fd, gt, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size,
+ visible_vram_if_possible(fd, gt));
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
@@ -309,7 +310,8 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
igt_assert(data);
}
} else {
- bo = xe_bo_create(fd, eci->gt_id, 0, bo_size);
+ bo = xe_bo_create_flags(fd, 0, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
@@ -517,7 +519,8 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
igt_assert(data);
}
} else {
- bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
data = xe_bo_map(fd, bo, bo_size);
}
memset(data, 0, bo_size);
diff --git a/tests/xe/xe_guc_pc.c b/tests/xe/xe_guc_pc.c
index 60c93288..bf304bd7 100644
--- a/tests/xe/xe_guc_pc.c
+++ b/tests/xe/xe_guc_pc.c
@@ -64,7 +64,8 @@ static void exec_basic(int fd, struct drm_xe_engine_class_instance *eci,
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size,
+ visible_vram_if_possible(fd, eci->gt_id));
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < n_engines; i++) {
diff --git a/tests/xe/xe_mmap.c b/tests/xe/xe_mmap.c
index 6b313a18..b23ce10c 100644
--- a/tests/xe/xe_mmap.c
+++ b/tests/xe/xe_mmap.c
@@ -70,10 +70,10 @@ igt_main
test_mmap(fd, system_memory(fd));
igt_subtest("vram")
- test_mmap(fd, vram_memory(fd, 0));
+ test_mmap(fd, visible_vram_memory(fd, 0));
igt_subtest("vram-system")
- test_mmap(fd, vram_memory(fd, 0) | system_memory(fd));
+ test_mmap(fd, visible_vram_memory(fd, 0) | system_memory(fd));
igt_fixture {
xe_device_put(fd);
diff --git a/tests/xe/xe_pm.c b/tests/xe/xe_pm.c
index 23b8246e..b3f47355 100644
--- a/tests/xe/xe_pm.c
+++ b/tests/xe/xe_pm.c
@@ -250,7 +250,8 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
if (check_rpm && runtime_usage_available(device.pci_xe))
rpm_usage = igt_pm_get_runtime_usage(device.pci_xe);
- bo = xe_bo_create(device.fd_xe, eci->gt_id, vm, bo_size);
+ bo = xe_bo_create_flags(device.fd_xe, vm, bo_size,
+ visible_vram_if_possible(device.fd_xe, eci->gt_id));
data = xe_bo_map(device.fd_xe, bo, bo_size);
for (i = 0; i < n_engines; i++) {
diff --git a/tests/xe/xe_prime_self_import.c b/tests/xe/xe_prime_self_import.c
index 5710cff9..97e330db 100644
--- a/tests/xe/xe_prime_self_import.c
+++ b/tests/xe/xe_prime_self_import.c
@@ -107,7 +107,7 @@ static void test_with_fd_dup(void)
fd2 = drm_open_driver(DRIVER_XE);
xe_device_get(fd2);
- handle = xe_bo_create(fd1, 0, 0, BO_SIZE);
+ handle = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
dma_buf_fd1 = prime_handle_to_fd(fd1, handle);
gem_close(fd1, handle);
@@ -146,8 +146,8 @@ static void test_with_two_bos(void)
fd2 = drm_open_driver(DRIVER_XE);
xe_device_get(fd2);
- handle1 = xe_bo_create(fd1, 0, 0, BO_SIZE);
- handle2 = xe_bo_create(fd1, 0, 0, BO_SIZE);
+ handle1 = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
+ handle2 = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
dma_buf_fd = prime_handle_to_fd(fd1, handle1);
handle_import = prime_fd_to_handle(fd2, dma_buf_fd);
@@ -225,7 +225,7 @@ static void test_with_one_bo(void)
fd2 = drm_open_driver(DRIVER_XE);
xe_device_get(fd2);
- handle = xe_bo_create(fd1, 0, 0, BO_SIZE);
+ handle = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
dma_buf_fd = prime_handle_to_fd(fd1, handle);
handle_import1 = prime_fd_to_handle(fd2, dma_buf_fd);
diff --git a/tests/xe/xe_vm.c b/tests/xe/xe_vm.c
index 15356c70..96b12f60 100644
--- a/tests/xe/xe_vm.c
+++ b/tests/xe/xe_vm.c
@@ -52,7 +52,8 @@ write_dwords(int fd, uint32_t vm, int n_dwords, uint64_t *addrs)
batch_size = (n_dwords * 4 + 1) * sizeof(uint32_t);
batch_size = ALIGN(batch_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- batch_bo = xe_bo_create(fd, 0, vm, batch_size);
+ batch_bo = xe_bo_create_flags(fd, vm, batch_size,
+ visible_vram_if_possible(fd, 0));
batch_map = xe_bo_map(fd, batch_bo, batch_size);
for (i = 0; i < n_dwords; i++) {
@@ -116,7 +117,7 @@ __test_bind_one_bo(int fd, uint32_t vm, int n_addrs, uint64_t *addrs)
vms = malloc(sizeof(*vms) * n_addrs);
igt_assert(vms);
}
- bo = xe_bo_create(fd, 0, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
map = xe_bo_map(fd, bo, bo_size);
memset(map, 0, bo_size);
@@ -549,7 +550,8 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
xe_get_default_alignment(fd));
for (i = 0; i < n_bo; ++i) {
- bo[i] = xe_bo_create(fd, 0, vm, bo_size);
+ bo[i] = xe_bo_create_flags(fd, vm, bo_size,
+ visible_vram_if_possible(fd, 0));
data[i] = xe_bo_map(fd, bo[i], bo_size);
}
@@ -717,7 +719,7 @@ test_bind_engines_independent(int fd, struct drm_xe_engine_class_instance *eci)
bo_size = sizeof(*data) * N_ENGINES;
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- bo = xe_bo_create(fd, 0, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
data = xe_bo_map(fd, bo, bo_size);
for (i = 0; i < N_ENGINES; i++) {
@@ -874,7 +876,7 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
xe_get_default_alignment(fd));
- bo = xe_bo_create(fd, 0, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
data = xe_bo_map(fd, bo, bo_size);
if (flags & BIND_ARRAY_BIND_ENGINE_FLAG)
@@ -1052,7 +1054,11 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci,
map = aligned_alloc(xe_get_default_alignment(fd), bo_size);
igt_assert(map);
} else {
- bo = xe_bo_create(fd, 0, vm, bo_size);
+ igt_skip_on(xe_visible_vram_size(fd, 0) && bo_size >
+ xe_visible_vram_size(fd, 0));
+
+ bo = xe_bo_create_flags(fd, vm, bo_size,
+ visible_vram_if_possible(fd, 0));
map = xe_bo_map(fd, bo, bo_size);
}
@@ -1329,7 +1335,8 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
MAP_ANONYMOUS, -1, 0);
igt_assert(data != MAP_FAILED);
} else {
- bo = xe_bo_create(fd, 0, vm, bo_size);
+ bo = xe_bo_create_flags(fd, vm, bo_size,
+ visible_vram_if_possible(fd, 0));
map = xe_bo_map(fd, bo, bo_size);
}
memset(map, 0, bo_size);
--
2.39.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 4/5] tests/xe/query: extend for CPU visible accounting
2023-03-29 11:56 [igt-dev] [PATCH i-g-t 0/5] IGT bits for small-bar Matthew Auld
` (2 preceding siblings ...)
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 3/5] tests/xe: handle small-bar systems Matthew Auld
@ 2023-03-29 11:56 ` Matthew Auld
2023-04-17 5:54 ` Gwan-gyeong Mun
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 5/5] tests/xe/mmap: sanity check small-bar Matthew Auld
` (3 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Matthew Auld @ 2023-03-29 11:56 UTC (permalink / raw
To: igt-dev
Print the visible size and how much is used. Also sanity check the
values.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
tests/xe/xe_query.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/tests/xe/xe_query.c b/tests/xe/xe_query.c
index 3f038225..9367d65e 100644
--- a/tests/xe/xe_query.c
+++ b/tests/xe/xe_query.c
@@ -228,6 +228,21 @@ test_query_mem_usage(int fd)
igt_info("min_page_size=0x%x, max_page_size=0x%x\n",
mem_usage->regions[i].min_page_size,
mem_usage->regions[i].max_page_size);
+
+ igt_info("visible size=%lluMiB\n",
+ mem_usage->regions[i].cpu_visible_size >> 20);
+ igt_info("visible used=%lluMiB\n",
+ mem_usage->regions[i].cpu_visible_used >> 20);
+
+ igt_assert_lte_u64(mem_usage->regions[i].cpu_visible_size,
+ mem_usage->regions[i].total_size);
+ igt_assert_lte_u64(mem_usage->regions[i].cpu_visible_used,
+ mem_usage->regions[i].cpu_visible_size);
+ igt_assert_lte_u64(mem_usage->regions[i].cpu_visible_used,
+ mem_usage->regions[i].used);
+ igt_assert_lte_u64(mem_usage->regions[i].used -
+ mem_usage->regions[i].cpu_visible_used,
+ mem_usage->regions[i].total_size);
}
dump_hex_debug(mem_usage, query.size);
free(mem_usage);
--
2.39.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 5/5] tests/xe/mmap: sanity check small-bar
2023-03-29 11:56 [igt-dev] [PATCH i-g-t 0/5] IGT bits for small-bar Matthew Auld
` (3 preceding siblings ...)
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 4/5] tests/xe/query: extend for CPU visible accounting Matthew Auld
@ 2023-03-29 11:56 ` Matthew Auld
2023-03-29 12:39 ` [igt-dev] ✓ Fi.CI.BAT: success for IGT bits for small-bar Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Matthew Auld @ 2023-03-29 11:56 UTC (permalink / raw
To: igt-dev
Some basic sanity checks.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
lib/xe/xe_ioctl.c | 20 +++++++++--
lib/xe/xe_ioctl.h | 2 ++
tests/xe/xe_mmap.c | 90 +++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 108 insertions(+), 4 deletions(-)
diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
index 9d5793df..566690b2 100644
--- a/lib/xe/xe_ioctl.c
+++ b/lib/xe/xe_ioctl.c
@@ -232,17 +232,31 @@ void xe_vm_destroy(int fd, uint32_t vm)
igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_VM_DESTROY, &destroy), 0);
}
-uint32_t xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags)
+uint32_t __xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags,
+ uint32_t *handle)
{
struct drm_xe_gem_create create = {
.vm_id = vm,
.size = size,
.flags = flags,
};
+ int err;
- igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_GEM_CREATE, &create), 0);
+ err = igt_ioctl(fd, DRM_IOCTL_XE_GEM_CREATE, &create);
+ if (err)
+ return err;
- return create.handle;
+ *handle = create.handle;
+ return 0;
+}
+
+uint32_t xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags)
+{
+ uint32_t handle;
+
+ igt_assert_eq(__xe_bo_create_flags(fd, vm, size, flags, &handle), 0);
+
+ return handle;
}
uint32_t xe_bo_create(int fd, int gt, uint32_t vm, uint64_t size)
diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
index 5c7e773f..ddcefc6d 100644
--- a/lib/xe/xe_ioctl.h
+++ b/lib/xe/xe_ioctl.h
@@ -63,6 +63,8 @@ void xe_vm_unbind_all_async(int fd, uint32_t vm, uint32_t engine,
uint32_t bo, struct drm_xe_sync *sync,
uint32_t num_syncs);
void xe_vm_destroy(int fd, uint32_t vm);
+uint32_t __xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags,
+ uint32_t *handle);
uint32_t xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags);
uint32_t xe_bo_create(int fd, int gt, uint32_t vm, uint64_t size);
uint32_t xe_engine_create(int fd, uint32_t vm,
diff --git a/tests/xe/xe_mmap.c b/tests/xe/xe_mmap.c
index b23ce10c..fab08a7a 100644
--- a/tests/xe/xe_mmap.c
+++ b/tests/xe/xe_mmap.c
@@ -17,14 +17,21 @@
#include "xe/xe_ioctl.h"
#include "xe/xe_query.h"
+#include <setjmp.h>
+#include <signal.h>
#include <string.h>
-
/**
* SUBTEST: system
* Description: Test mmap on system memory
*/
+/**
+ * SUBTEST: small-bar
+ * Description: Sanity check mmap behaviour on small-bar systems
+ * GPU requirements: GPU needs to have dedicated VRAM and using small-bar
+ */
+
/**
* SUBTEST: %s
* Description: Test mmap on %arg[1] memory
@@ -57,6 +64,82 @@ test_mmap(int fd, uint32_t flags)
gem_close(fd, bo);
}
+static jmp_buf jmp;
+
+__noreturn static void sigtrap(int sig)
+{
+ siglongjmp(jmp, sig);
+}
+
+static void trap_sigbus(uint32_t *ptr)
+{
+ sighandler_t old_sigbus;
+
+ old_sigbus = signal(SIGBUS, sigtrap);
+ switch (sigsetjmp(jmp, SIGBUS)) {
+ case SIGBUS:
+ break;
+ case 0:
+ *ptr = 0xdeadbeaf;
+ default:
+ igt_assert(!"reached");
+ break;
+ }
+ signal(SIGBUS, old_sigbus);
+}
+
+static void
+test_mmap_small_bar(int fd)
+{
+ uint32_t visible_size = xe_visible_vram_size(fd, 0);
+ uint32_t bo;
+ uint64_t mmo;
+ uint32_t *map;
+
+ /* Some 2BIG invalid cases */
+ igt_assert_neq(__xe_bo_create_flags(fd, 0, visible_size,
+ visible_vram_memory(fd, 0), &bo),
+ 0);
+ igt_assert_neq(__xe_bo_create_flags(fd, 0, visible_size + 4096,
+ visible_vram_memory(fd, 0), &bo),
+ 0);
+
+ /* Normal operation */
+ bo = xe_bo_create_flags(fd, 0, visible_size / 4,
+ visible_vram_memory(fd, 0));
+ mmo = xe_bo_mmap_offset(fd, bo);
+ map = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED, fd, mmo);
+ igt_assert(map != MAP_FAILED);
+
+ map[0] = 0xdeadbeaf;
+
+ munmap(map, 4096);
+ gem_close(fd, bo);
+
+ /* Normal operation with system memory spilling */
+ bo = xe_bo_create_flags(fd, 0, visible_size,
+ visible_vram_memory(fd, 0) |
+ system_memory(fd));
+ mmo = xe_bo_mmap_offset(fd, bo);
+ map = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED, fd, mmo);
+ igt_assert(map != MAP_FAILED);
+
+ map[0] = 0xdeadbeaf;
+
+ munmap(map, 4096);
+ gem_close(fd, bo);
+
+ /* Bogus operation with SIGBUS */
+ bo = xe_bo_create_flags(fd, 0, visible_size + 4096,
+ vram_memory(fd, 0));
+ mmo = xe_bo_mmap_offset(fd, bo);
+ map = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED, fd, mmo);
+ igt_assert(map != MAP_FAILED);
+
+ trap_sigbus(map);
+ gem_close(fd, bo);
+}
+
igt_main
{
int fd;
@@ -75,6 +158,11 @@ igt_main
igt_subtest("vram-system")
test_mmap(fd, visible_vram_memory(fd, 0) | system_memory(fd));
+ igt_subtest("small-bar") {
+ igt_require(xe_visible_vram_size(fd, 0) < xe_vram_size(fd, 0));
+ test_mmap_small_bar(fd);
+ }
+
igt_fixture {
xe_device_put(fd);
close(fd);
--
2.39.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for IGT bits for small-bar
2023-03-29 11:56 [igt-dev] [PATCH i-g-t 0/5] IGT bits for small-bar Matthew Auld
` (4 preceding siblings ...)
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 5/5] tests/xe/mmap: sanity check small-bar Matthew Auld
@ 2023-03-29 12:39 ` Patchwork
2023-03-30 2:29 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2023-05-17 14:40 ` [igt-dev] ✗ Fi.CI.BUILD: failure for IGT bits for small-bar (rev2) Patchwork
7 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-03-29 12:39 UTC (permalink / raw
To: Matthew Auld; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 5403 bytes --]
== Series Details ==
Series: IGT bits for small-bar
URL : https://patchwork.freedesktop.org/series/115786/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12934 -> IGTPW_8709
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/index.html
Participating hosts (37 -> 35)
------------------------------
Missing (2): fi-kbl-soraka fi-snb-2520m
Known issues
------------
Here are the changes found in IGTPW_8709 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [PASS][1] -> [DMESG-FAIL][2] ([i915#7699])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/bat-dg2-11/igt@i915_selftest@live@migrate.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/bat-dg2-11/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@workarounds:
- bat-adlp-9: [PASS][3] -> [INCOMPLETE][4] ([i915#4983])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/bat-adlp-9/igt@i915_selftest@live@workarounds.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/bat-adlp-9/igt@i915_selftest@live@workarounds.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-1: NOTRUN -> [SKIP][5] ([i915#7828])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/bat-rpls-1/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1:
- bat-dg2-8: [PASS][6] -> [FAIL][7] ([i915#7932])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#5354])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/bat-dg2-11/igt@kms_pipe_crc_basic@read-crc.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-rpls-1: NOTRUN -> [SKIP][9] ([i915#1845])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/bat-rpls-1/igt@kms_pipe_crc_basic@suspend-read-crc.html
#### Possible fixes ####
* igt@i915_pm_rps@basic-api:
- bat-dg2-11: [FAIL][10] ([i915#8308]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/bat-dg2-11/igt@i915_pm_rps@basic-api.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/bat-dg2-11/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: [ABORT][12] ([i915#4983]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/bat-rpls-1/igt@i915_selftest@live@reset.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/bat-rpls-1/igt@i915_selftest@live@reset.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-kbl-7567u: [ABORT][14] ([i915#8299]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/fi-kbl-7567u/igt@i915_suspend@basic-s2idle-without-i915.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/fi-kbl-7567u/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-2:
- fi-bsw-n3050: [DMESG-WARN][16] ([i915#1982]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/fi-bsw-n3050/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-2.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/fi-bsw-n3050/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-2.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-2:
- bat-dg1-5: [FAIL][18] ([fdo#103375]) -> [PASS][19] +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/bat-dg1-5/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-2.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/bat-dg1-5/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-2.html
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#8299]: https://gitlab.freedesktop.org/drm/intel/issues/8299
[i915#8308]: https://gitlab.freedesktop.org/drm/intel/issues/8308
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7225 -> IGTPW_8709
CI-20190529: 20190529
CI_DRM_12934: 0d5e1ccc82c11e9d26d31b55b885a8d3f6588a8d @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_8709: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/index.html
IGT_7225: e2b54c935ac78a78a4243b22c53b1a61fd04ffdb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Testlist changes
----------------
+igt@xe_mmap@small-bar
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/index.html
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for IGT bits for small-bar
2023-03-29 11:56 [igt-dev] [PATCH i-g-t 0/5] IGT bits for small-bar Matthew Auld
` (5 preceding siblings ...)
2023-03-29 12:39 ` [igt-dev] ✓ Fi.CI.BAT: success for IGT bits for small-bar Patchwork
@ 2023-03-30 2:29 ` Patchwork
2023-05-17 14:40 ` [igt-dev] ✗ Fi.CI.BUILD: failure for IGT bits for small-bar (rev2) Patchwork
7 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-03-30 2:29 UTC (permalink / raw
To: Matthew Auld; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 18518 bytes --]
== Series Details ==
Series: IGT bits for small-bar
URL : https://patchwork.freedesktop.org/series/115786/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12934_full -> IGTPW_8709_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_8709_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_8709_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/index.html
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_8709_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-apl: [PASS][1] -> [TIMEOUT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-apl3/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-apl2/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
Known issues
------------
Here are the changes found in IGTPW_8709_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: NOTRUN -> [FAIL][3] ([i915#2842])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-glk9/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [PASS][4] -> [FAIL][5] ([i915#2842])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-apl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-apl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [PASS][6] -> [FAIL][7] ([i915#2842]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-glk9/igt@gem_exec_fair@basic-pace@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-glk7/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-apl: NOTRUN -> [SKIP][8] ([fdo#109271]) +51 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-apl1/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][9] -> [ABORT][10] ([i915#5566])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-apl4/igt@gen9_exec_parse@allowed-single.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-apl2/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc9-dpms:
- shard-apl: [PASS][11] -> [SKIP][12] ([fdo#109271])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-apl1/igt@i915_pm_dc@dc9-dpms.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-apl6/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271]) +30 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-glk1/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#3886]) +2 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-apl1/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3886]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-glk7/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: NOTRUN -> [FAIL][16] ([i915#2346])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-dpms:
- shard-snb: NOTRUN -> [SKIP][17] ([fdo#109271]) +8 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-snb5/igt@kms_flip@2x-flip-vs-dpms.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][18] -> [FAIL][19] ([i915#2122])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend@b-vga1:
- shard-snb: [PASS][20] -> [DMESG-WARN][21] ([i915#5090])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-snb2/igt@kms_flip@flip-vs-suspend@b-vga1.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-snb4/igt@kms_flip@flip-vs-suspend@b-vga1.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-glk: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#658])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-glk1/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-p010:
- shard-apl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#658])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-apl1/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-apl: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#533])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-apl2/igt@kms_vblank@pipe-d-wait-idle.html
#### Possible fixes ####
* {igt@gem_barrier_race@remote-request@rcs0}:
- shard-apl: [ABORT][25] -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-apl3/igt@gem_barrier_race@remote-request@rcs0.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-apl6/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_eio@kms:
- {shard-dg1}: [FAIL][27] ([i915#5784]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-dg1-14/igt@gem_eio@kms.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-dg1-15/igt@gem_eio@kms.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][29] ([i915#2846]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-glk8/igt@gem_exec_fair@basic-deadline.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-glk5/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_whisper@basic-fds-priority-all:
- {shard-tglu}: [INCOMPLETE][31] ([i915#6755]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-tglu-2/igt@gem_exec_whisper@basic-fds-priority-all.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-tglu-2/igt@gem_exec_whisper@basic-fds-priority-all.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [ABORT][33] ([i915#5566]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-glk1/igt@gen9_exec_parse@allowed-single.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-glk5/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc9-dpms:
- {shard-tglu}: [SKIP][35] ([i915#4281]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-tglu-7/igt@i915_pm_dc@dc9-dpms.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-tglu-2/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- {shard-dg1}: [SKIP][37] ([i915#1397]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-dg1-14/igt@i915_pm_rpm@dpms-non-lpsp.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-dg1-17/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_pm_rps@reset:
- shard-snb: [INCOMPLETE][39] ([i915#7790]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-snb7/igt@i915_pm_rps@reset.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-snb7/igt@i915_pm_rps@reset.html
* igt@i915_suspend@debugfs-reader:
- shard-apl: [ABORT][41] ([i915#180]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-apl7/igt@i915_suspend@debugfs-reader.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-apl6/igt@i915_suspend@debugfs-reader.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][43] ([i915#2346]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][45] ([i915#2122]) -> [PASS][46] +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-glk7/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ac-hdmi-a1-hdmi-a2.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-glk1/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1:
- shard-glk: [FAIL][47] ([i915#79]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
[i915#5090]: https://gitlab.freedesktop.org/drm/intel/issues/5090
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5431]: https://gitlab.freedesktop.org/drm/intel/issues/5431
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6755]: https://gitlab.freedesktop.org/drm/intel/issues/6755
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#8155]: https://gitlab.freedesktop.org/drm/intel/issues/8155
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8308]: https://gitlab.freedesktop.org/drm/intel/issues/8308
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7225 -> IGTPW_8709
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_12934: 0d5e1ccc82c11e9d26d31b55b885a8d3f6588a8d @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_8709: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/index.html
IGT_7225: e2b54c935ac78a78a4243b22c53b1a61fd04ffdb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8709/index.html
[-- Attachment #2: Type: text/html, Size: 14496 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/5] xe: sync small-bar uapi
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 1/5] xe: sync small-bar uapi Matthew Auld
@ 2023-04-02 23:46 ` Gwan-gyeong Mun
0 siblings, 0 replies; 16+ messages in thread
From: Gwan-gyeong Mun @ 2023-04-02 23:46 UTC (permalink / raw
To: Matthew Auld, igt-dev
btw, The kernel patch hasn't been merged into drm-xe yet, are there any
blockers to merge it?
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
On 3/29/23 2:56 PM, Matthew Auld wrote:
> We need a couple new fields for the region query and the new flag to
> ensure the buffer is CPU accessible.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
> include/drm-uapi/xe_drm.h | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
> index 593b01ba..441b377b 100644
> --- a/include/drm-uapi/xe_drm.h
> +++ b/include/drm-uapi/xe_drm.h
> @@ -169,7 +169,9 @@ struct drm_xe_query_mem_usage {
> __u32 max_page_size;
> __u64 total_size;
> __u64 used;
> - __u64 reserved[8];
> + __u64 cpu_visible_size;
> + __u64 cpu_visible_used;
> + __u64 reserved[6];
> } regions[];
> };
>
> @@ -270,6 +272,7 @@ struct drm_xe_gem_create {
> */
> #define XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24)
> #define XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25)
> +#define XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (0x1 << 26)
> __u32 flags;
>
> /**
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/5] lib/xe: add visible vram helpers
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 2/5] lib/xe: add visible vram helpers Matthew Auld
@ 2023-04-03 9:18 ` Gwan-gyeong Mun
2023-04-03 12:39 ` Matthew Auld
0 siblings, 1 reply; 16+ messages in thread
From: Gwan-gyeong Mun @ 2023-04-03 9:18 UTC (permalink / raw
To: Matthew Auld, igt-dev
On 3/29/23 2:56 PM, Matthew Auld wrote:
> Add helpers for object creation and querying the cpu_visible related bits.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
> lib/xe/xe_query.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++-
> lib/xe/xe_query.h | 6 +++++
> 2 files changed, 74 insertions(+), 1 deletion(-)
>
> diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
> index f281bc4a..48a413cd 100644
> --- a/lib/xe/xe_query.c
> +++ b/lib/xe/xe_query.c
> @@ -140,6 +140,17 @@ static uint64_t gt_vram_size(const struct drm_xe_query_mem_usage *mem_usage,
> return 0;
> }
>
> +static uint64_t gt_visible_vram_size(const struct drm_xe_query_mem_usage *mem_usage,
> + const struct drm_xe_query_gts *gts, int gt)
> +{
> + int region_idx = ffs(native_region_for_gt(gts, gt)) - 1;
> +
> + if (XE_IS_CLASS_VRAM(&mem_usage->regions[region_idx]))
> + return mem_usage->regions[region_idx].cpu_visible_size;
> +
> + return 0;
> +}
> +
> static bool __mem_has_vram(struct drm_xe_query_mem_usage *mem_usage)
> {
> for (int i = 0; i < mem_usage->num_regions; i++)
> @@ -246,9 +257,14 @@ struct xe_device *xe_device_get(int fd)
> xe_dev->hw_engines = xe_query_engines_new(fd, &xe_dev->number_hw_engines);
> xe_dev->mem_usage = xe_query_mem_usage_new(fd);
> xe_dev->vram_size = calloc(xe_dev->number_gt, sizeof(*xe_dev->vram_size));
> - for (int gt = 0; gt < xe_dev->number_gt; gt++)
> + xe_dev->visible_vram_size = calloc(xe_dev->number_gt, sizeof(*xe_dev->visible_vram_size));
> + for (int gt = 0; gt < xe_dev->number_gt; gt++) {
> xe_dev->vram_size[gt] = gt_vram_size(xe_dev->mem_usage,
> xe_dev->gts, gt);
> + xe_dev->visible_vram_size[gt] =
> + gt_visible_vram_size(xe_dev->mem_usage,
> + xe_dev->gts, gt);
> + }
> xe_dev->default_alignment = __mem_default_alignment(xe_dev->mem_usage);
> xe_dev->has_vram = __mem_has_vram(xe_dev->mem_usage);
>
> @@ -383,6 +399,20 @@ uint64_t vram_memory(int fd, int gt)
> return native_region_for_gt(xe_dev->gts, gt);
> }
>
> +/**
> + * visible_vram_memory:
> + * @fd: xe device fd
> + * @gt: gt id
> + *
> + * Returns vram memory bitmask for xe device @fd and @gt id, with
> + * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM also set, to ensure that CPU access is
> + * possible.
> + */
> +uint64_t visible_vram_memory(int fd, int gt)
> +{
> + return vram_memory(fd, gt) | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
> +}
> +
> /**
> * vram_if_possible:
> * @fd: xe device fd
> @@ -400,6 +430,25 @@ uint64_t vram_if_possible(int fd, int gt)
> return vram ? vram : system_memory;
> }
>
> +/**
> + * visible_vram_if_possible:
> + * @fd: xe device fd
> + * @gt: gt id
> + *
> + * Returns vram memory bitmask for xe device @fd and @gt id or system memory if
> + * there's no vram memory available for @gt. Also attaches the
> + * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM to ensure that CPU access is possible
> + * when using vram.
> + */
> +uint64_t visible_vram_if_possible(int fd, int gt)
> +{
> + uint64_t regions = all_memory_regions(fd);
> + uint64_t system_memory = regions & 0x1;
> + uint64_t vram = regions & (0x2 << gt);
> +
Hi Matt,
vram_if_possible() uses as the below check routine for vram
uint64_t vram = regions & (~0x1);
but, here uses
uint64_t vram = regions & (0x2 << gt);
Why do you use a different check method than the vram_if_possible()?
Other than that, the rest looks good.
Br,
G.G.
> + return vram ? vram | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM : system_memory;
> +}
> +
> /**
> * xe_hw_engines:
> * @fd: xe device fd
> @@ -459,6 +508,23 @@ uint64_t xe_vram_size(int fd, int gt)
> return xe_dev->vram_size[gt];
> }
>
> +/**
> + * xe_visible_vram_size:
> + * @fd: xe device fd
> + * @gt: gt
> + *
> + * Returns size of visible vram of xe device @fd.
> + */
> +uint64_t xe_visible_vram_size(int fd, int gt)
> +{
> + struct xe_device *xe_dev;
> +
> + xe_dev = find_in_cache(fd);
> + igt_assert(xe_dev);
> +
> + return xe_dev->visible_vram_size[gt];
> +}
> +
> /**
> * xe_get_default_alignment:
> * @fd: xe device fd
> @@ -475,6 +541,7 @@ xe_dev_FN(xe_get_default_alignment, default_alignment, uint32_t);
> */
> xe_dev_FN(xe_va_bits, va_bits, uint32_t);
>
> +
> /**
> * xe_dev_id:
> * @fd: xe device fd
> diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
> index 3a00ecd1..5aa5b402 100644
> --- a/lib/xe/xe_query.h
> +++ b/lib/xe/xe_query.h
> @@ -47,6 +47,9 @@ struct xe_device {
> /** @vram_size: array of vram sizes for all gts */
> uint64_t *vram_size;
>
> + /** @visible_vram_size: array of visible vram sizes for all gts */
> + uint64_t *visible_vram_size;
> +
> /** @default_alignment: safe alignment regardless region location */
> uint32_t default_alignment;
>
> @@ -76,13 +79,16 @@ unsigned int xe_number_gt(int fd);
> uint64_t all_memory_regions(int fd);
> uint64_t system_memory(int fd);
> uint64_t vram_memory(int fd, int gt);
> +uint64_t visible_vram_memory(int fd, int gt);
> uint64_t vram_if_possible(int fd, int gt);
> +uint64_t visible_vram_if_possible(int fd, int gt);
> struct drm_xe_engine_class_instance *xe_hw_engines(int fd);
> struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx);
> unsigned int xe_number_hw_engines(int fd);
> bool xe_has_vram(int fd);
> //uint64_t xe_vram_size(int fd);
> uint64_t xe_vram_size(int fd, int gt);
> +uint64_t xe_visible_vram_size(int fd, int gt);
> uint32_t xe_get_default_alignment(int fd);
> uint32_t xe_va_bits(int fd);
> uint16_t xe_dev_id(int fd);
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/5] lib/xe: add visible vram helpers
2023-04-03 9:18 ` Gwan-gyeong Mun
@ 2023-04-03 12:39 ` Matthew Auld
2023-04-03 14:17 ` Gwan-gyeong Mun
0 siblings, 1 reply; 16+ messages in thread
From: Matthew Auld @ 2023-04-03 12:39 UTC (permalink / raw
To: Gwan-gyeong Mun, igt-dev
On 03/04/2023 10:18, Gwan-gyeong Mun wrote:
>
>
> On 3/29/23 2:56 PM, Matthew Auld wrote:
>> Add helpers for object creation and querying the cpu_visible related
>> bits.
>>
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> ---
>> lib/xe/xe_query.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++-
>> lib/xe/xe_query.h | 6 +++++
>> 2 files changed, 74 insertions(+), 1 deletion(-)
>>
>> diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
>> index f281bc4a..48a413cd 100644
>> --- a/lib/xe/xe_query.c
>> +++ b/lib/xe/xe_query.c
>> @@ -140,6 +140,17 @@ static uint64_t gt_vram_size(const struct
>> drm_xe_query_mem_usage *mem_usage,
>> return 0;
>> }
>> +static uint64_t gt_visible_vram_size(const struct
>> drm_xe_query_mem_usage *mem_usage,
>> + const struct drm_xe_query_gts *gts, int gt)
>> +{
>> + int region_idx = ffs(native_region_for_gt(gts, gt)) - 1;
>> +
>> + if (XE_IS_CLASS_VRAM(&mem_usage->regions[region_idx]))
>> + return mem_usage->regions[region_idx].cpu_visible_size;
>> +
>> + return 0;
>> +}
>> +
>> static bool __mem_has_vram(struct drm_xe_query_mem_usage *mem_usage)
>> {
>> for (int i = 0; i < mem_usage->num_regions; i++)
>> @@ -246,9 +257,14 @@ struct xe_device *xe_device_get(int fd)
>> xe_dev->hw_engines = xe_query_engines_new(fd,
>> &xe_dev->number_hw_engines);
>> xe_dev->mem_usage = xe_query_mem_usage_new(fd);
>> xe_dev->vram_size = calloc(xe_dev->number_gt,
>> sizeof(*xe_dev->vram_size));
>> - for (int gt = 0; gt < xe_dev->number_gt; gt++)
>> + xe_dev->visible_vram_size = calloc(xe_dev->number_gt,
>> sizeof(*xe_dev->visible_vram_size));
>> + for (int gt = 0; gt < xe_dev->number_gt; gt++) {
>> xe_dev->vram_size[gt] = gt_vram_size(xe_dev->mem_usage,
>> xe_dev->gts, gt);
>> + xe_dev->visible_vram_size[gt] =
>> + gt_visible_vram_size(xe_dev->mem_usage,
>> + xe_dev->gts, gt);
>> + }
>> xe_dev->default_alignment =
>> __mem_default_alignment(xe_dev->mem_usage);
>> xe_dev->has_vram = __mem_has_vram(xe_dev->mem_usage);
>> @@ -383,6 +399,20 @@ uint64_t vram_memory(int fd, int gt)
>> return native_region_for_gt(xe_dev->gts, gt);
>> }
>> +/**
>> + * visible_vram_memory:
>> + * @fd: xe device fd
>> + * @gt: gt id
>> + *
>> + * Returns vram memory bitmask for xe device @fd and @gt id, with
>> + * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM also set, to ensure that CPU
>> access is
>> + * possible.
>> + */
>> +uint64_t visible_vram_memory(int fd, int gt)
>> +{
>> + return vram_memory(fd, gt) | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
>> +}
>> +
>> /**
>> * vram_if_possible:
>> * @fd: xe device fd
>> @@ -400,6 +430,25 @@ uint64_t vram_if_possible(int fd, int gt)
>> return vram ? vram : system_memory;
>> }
>> +/**
>> + * visible_vram_if_possible:
>> + * @fd: xe device fd
>> + * @gt: gt id
>> + *
>> + * Returns vram memory bitmask for xe device @fd and @gt id or system
>> memory if
>> + * there's no vram memory available for @gt. Also attaches the
>> + * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM to ensure that CPU access is
>> possible
>> + * when using vram.
>> + */
>> +uint64_t visible_vram_if_possible(int fd, int gt)
>> +{
>> + uint64_t regions = all_memory_regions(fd);
>> + uint64_t system_memory = regions & 0x1;
>> + uint64_t vram = regions & (0x2 << gt);
>> +
> Hi Matt,
>
> vram_if_possible() uses as the below check routine for vram
>
> uint64_t vram = regions & (~0x1);
>
> but, here uses
>
> uint64_t vram = regions & (0x2 << gt);
>
> Why do you use a different check method than the vram_if_possible()?
I assume it was just copy-pasted from an earlier version of
vram_if_possible(). Although I don't quite get why it wants to use
(~0x1) here, if we are passing in the GT...
>
> Other than that, the rest looks good.
>
> Br,
> G.G.
>> + return vram ? vram | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM :
>> system_memory;
>> +}
>> +
>> /**
>> * xe_hw_engines:
>> * @fd: xe device fd
>> @@ -459,6 +508,23 @@ uint64_t xe_vram_size(int fd, int gt)
>> return xe_dev->vram_size[gt];
>> }
>> +/**
>> + * xe_visible_vram_size:
>> + * @fd: xe device fd
>> + * @gt: gt
>> + *
>> + * Returns size of visible vram of xe device @fd.
>> + */
>> +uint64_t xe_visible_vram_size(int fd, int gt)
>> +{
>> + struct xe_device *xe_dev;
>> +
>> + xe_dev = find_in_cache(fd);
>> + igt_assert(xe_dev);
>> +
>> + return xe_dev->visible_vram_size[gt];
>> +}
>> +
>> /**
>> * xe_get_default_alignment:
>> * @fd: xe device fd
>> @@ -475,6 +541,7 @@ xe_dev_FN(xe_get_default_alignment,
>> default_alignment, uint32_t);
>> */
>> xe_dev_FN(xe_va_bits, va_bits, uint32_t);
>> +
>> /**
>> * xe_dev_id:
>> * @fd: xe device fd
>> diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
>> index 3a00ecd1..5aa5b402 100644
>> --- a/lib/xe/xe_query.h
>> +++ b/lib/xe/xe_query.h
>> @@ -47,6 +47,9 @@ struct xe_device {
>> /** @vram_size: array of vram sizes for all gts */
>> uint64_t *vram_size;
>> + /** @visible_vram_size: array of visible vram sizes for all gts */
>> + uint64_t *visible_vram_size;
>> +
>> /** @default_alignment: safe alignment regardless region
>> location */
>> uint32_t default_alignment;
>> @@ -76,13 +79,16 @@ unsigned int xe_number_gt(int fd);
>> uint64_t all_memory_regions(int fd);
>> uint64_t system_memory(int fd);
>> uint64_t vram_memory(int fd, int gt);
>> +uint64_t visible_vram_memory(int fd, int gt);
>> uint64_t vram_if_possible(int fd, int gt);
>> +uint64_t visible_vram_if_possible(int fd, int gt);
>> struct drm_xe_engine_class_instance *xe_hw_engines(int fd);
>> struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx);
>> unsigned int xe_number_hw_engines(int fd);
>> bool xe_has_vram(int fd);
>> //uint64_t xe_vram_size(int fd);
>> uint64_t xe_vram_size(int fd, int gt);
>> +uint64_t xe_visible_vram_size(int fd, int gt);
>> uint32_t xe_get_default_alignment(int fd);
>> uint32_t xe_va_bits(int fd);
>> uint16_t xe_dev_id(int fd);
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/5] lib/xe: add visible vram helpers
2023-04-03 12:39 ` Matthew Auld
@ 2023-04-03 14:17 ` Gwan-gyeong Mun
0 siblings, 0 replies; 16+ messages in thread
From: Gwan-gyeong Mun @ 2023-04-03 14:17 UTC (permalink / raw
To: Matthew Auld, igt-dev
On 4/3/23 3:39 PM, Matthew Auld wrote:
> On 03/04/2023 10:18, Gwan-gyeong Mun wrote:
>>
>>
>> On 3/29/23 2:56 PM, Matthew Auld wrote:
>>> Add helpers for object creation and querying the cpu_visible related
>>> bits.
>>>
>>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>>> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>>> ---
>>> lib/xe/xe_query.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++-
>>> lib/xe/xe_query.h | 6 +++++
>>> 2 files changed, 74 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
>>> index f281bc4a..48a413cd 100644
>>> --- a/lib/xe/xe_query.c
>>> +++ b/lib/xe/xe_query.c
>>> @@ -140,6 +140,17 @@ static uint64_t gt_vram_size(const struct
>>> drm_xe_query_mem_usage *mem_usage,
>>> return 0;
>>> }
>>> +static uint64_t gt_visible_vram_size(const struct
>>> drm_xe_query_mem_usage *mem_usage,
>>> + const struct drm_xe_query_gts *gts, int gt)
>>> +{
>>> + int region_idx = ffs(native_region_for_gt(gts, gt)) - 1;
>>> +
>>> + if (XE_IS_CLASS_VRAM(&mem_usage->regions[region_idx]))
>>> + return mem_usage->regions[region_idx].cpu_visible_size;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> static bool __mem_has_vram(struct drm_xe_query_mem_usage *mem_usage)
>>> {
>>> for (int i = 0; i < mem_usage->num_regions; i++)
>>> @@ -246,9 +257,14 @@ struct xe_device *xe_device_get(int fd)
>>> xe_dev->hw_engines = xe_query_engines_new(fd,
>>> &xe_dev->number_hw_engines);
>>> xe_dev->mem_usage = xe_query_mem_usage_new(fd);
>>> xe_dev->vram_size = calloc(xe_dev->number_gt,
>>> sizeof(*xe_dev->vram_size));
>>> - for (int gt = 0; gt < xe_dev->number_gt; gt++)
>>> + xe_dev->visible_vram_size = calloc(xe_dev->number_gt,
>>> sizeof(*xe_dev->visible_vram_size));
>>> + for (int gt = 0; gt < xe_dev->number_gt; gt++) {
>>> xe_dev->vram_size[gt] = gt_vram_size(xe_dev->mem_usage,
>>> xe_dev->gts, gt);
>>> + xe_dev->visible_vram_size[gt] =
>>> + gt_visible_vram_size(xe_dev->mem_usage,
>>> + xe_dev->gts, gt);
>>> + }
>>> xe_dev->default_alignment =
>>> __mem_default_alignment(xe_dev->mem_usage);
>>> xe_dev->has_vram = __mem_has_vram(xe_dev->mem_usage);
>>> @@ -383,6 +399,20 @@ uint64_t vram_memory(int fd, int gt)
>>> return native_region_for_gt(xe_dev->gts, gt);
>>> }
>>> +/**
>>> + * visible_vram_memory:
>>> + * @fd: xe device fd
>>> + * @gt: gt id
>>> + *
>>> + * Returns vram memory bitmask for xe device @fd and @gt id, with
>>> + * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM also set, to ensure that
>>> CPU access is
>>> + * possible.
>>> + */
>>> +uint64_t visible_vram_memory(int fd, int gt)
>>> +{
>>> + return vram_memory(fd, gt) | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
>>> +}
>>> +
>>> /**
>>> * vram_if_possible:
>>> * @fd: xe device fd
>>> @@ -400,6 +430,25 @@ uint64_t vram_if_possible(int fd, int gt)
>>> return vram ? vram : system_memory;
>>> }
>>> +/**
>>> + * visible_vram_if_possible:
>>> + * @fd: xe device fd
>>> + * @gt: gt id
>>> + *
>>> + * Returns vram memory bitmask for xe device @fd and @gt id or
>>> system memory if
>>> + * there's no vram memory available for @gt. Also attaches the
>>> + * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM to ensure that CPU access
>>> is possible
>>> + * when using vram.
>>> + */
>>> +uint64_t visible_vram_if_possible(int fd, int gt)
>>> +{
>>> + uint64_t regions = all_memory_regions(fd);
>>> + uint64_t system_memory = regions & 0x1;
>>> + uint64_t vram = regions & (0x2 << gt);
>>> +
>> Hi Matt,
>>
>> vram_if_possible() uses as the below check routine for vram
>>
>> uint64_t vram = regions & (~0x1);
>>
>> but, here uses
>>
>> uint64_t vram = regions & (0x2 << gt);
>>
>> Why do you use a different check method than the vram_if_possible()?
>
> I assume it was just copy-pasted from an earlier version of
> vram_if_possible(). Although I don't quite get why it wants to use
> (~0x1) here, if we are passing in the GT...
>
If the purpose of this function is to return the flag information of the
VRAM of the specific GT passed as an argument when it is available, then
the code of vram_if_possible() should be changed like yours.
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>>
>> Other than that, the rest looks good.
>>
>> Br,
>> G.G.
>>> + return vram ? vram | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM :
>>> system_memory;
>>> +}
>>> +
>>> /**
>>> * xe_hw_engines:
>>> * @fd: xe device fd
>>> @@ -459,6 +508,23 @@ uint64_t xe_vram_size(int fd, int gt)
>>> return xe_dev->vram_size[gt];
>>> }
>>> +/**
>>> + * xe_visible_vram_size:
>>> + * @fd: xe device fd
>>> + * @gt: gt
>>> + *
>>> + * Returns size of visible vram of xe device @fd.
>>> + */
>>> +uint64_t xe_visible_vram_size(int fd, int gt)
>>> +{
>>> + struct xe_device *xe_dev;
>>> +
>>> + xe_dev = find_in_cache(fd);
>>> + igt_assert(xe_dev);
>>> +
>>> + return xe_dev->visible_vram_size[gt];
>>> +}
>>> +
>>> /**
>>> * xe_get_default_alignment:
>>> * @fd: xe device fd
>>> @@ -475,6 +541,7 @@ xe_dev_FN(xe_get_default_alignment,
>>> default_alignment, uint32_t);
>>> */
>>> xe_dev_FN(xe_va_bits, va_bits, uint32_t);
>>> +
>>> /**
>>> * xe_dev_id:
>>> * @fd: xe device fd
>>> diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h
>>> index 3a00ecd1..5aa5b402 100644
>>> --- a/lib/xe/xe_query.h
>>> +++ b/lib/xe/xe_query.h
>>> @@ -47,6 +47,9 @@ struct xe_device {
>>> /** @vram_size: array of vram sizes for all gts */
>>> uint64_t *vram_size;
>>> + /** @visible_vram_size: array of visible vram sizes for all gts */
>>> + uint64_t *visible_vram_size;
>>> +
>>> /** @default_alignment: safe alignment regardless region
>>> location */
>>> uint32_t default_alignment;
>>> @@ -76,13 +79,16 @@ unsigned int xe_number_gt(int fd);
>>> uint64_t all_memory_regions(int fd);
>>> uint64_t system_memory(int fd);
>>> uint64_t vram_memory(int fd, int gt);
>>> +uint64_t visible_vram_memory(int fd, int gt);
>>> uint64_t vram_if_possible(int fd, int gt);
>>> +uint64_t visible_vram_if_possible(int fd, int gt);
>>> struct drm_xe_engine_class_instance *xe_hw_engines(int fd);
>>> struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx);
>>> unsigned int xe_number_hw_engines(int fd);
>>> bool xe_has_vram(int fd);
>>> //uint64_t xe_vram_size(int fd);
>>> uint64_t xe_vram_size(int fd, int gt);
>>> +uint64_t xe_visible_vram_size(int fd, int gt);
>>> uint32_t xe_get_default_alignment(int fd);
>>> uint32_t xe_va_bits(int fd);
>>> uint16_t xe_dev_id(int fd);
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 3/5] tests/xe: handle small-bar systems
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 3/5] tests/xe: handle small-bar systems Matthew Auld
@ 2023-04-05 12:53 ` Gwan-gyeong Mun
2023-05-17 17:03 ` Kamil Konieczny
1 sibling, 0 replies; 16+ messages in thread
From: Gwan-gyeong Mun @ 2023-04-05 12:53 UTC (permalink / raw
To: Matthew Auld, igt-dev
On 3/29/23 2:56 PM, Matthew Auld wrote:
> Convert all the existing tests that require CPU access.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
> lib/xe/xe_spin.c | 3 ++-
> tests/xe/xe_dma_buf_sync.c | 3 ++-
> tests/xe/xe_evict.c | 32 +++++++++++++++++++-------------
> tests/xe/xe_exec_balancer.c | 6 +++---
> tests/xe/xe_exec_basic.c | 19 ++++++++++---------
> tests/xe/xe_exec_compute_mode.c | 4 ++--
> tests/xe/xe_exec_fault_mode.c | 12 ++++++++----
> tests/xe/xe_exec_reset.c | 13 ++++++++-----
> tests/xe/xe_exec_threads.c | 9 ++++++---
> tests/xe/xe_guc_pc.c | 3 ++-
> tests/xe/xe_mmap.c | 4 ++--
> tests/xe/xe_pm.c | 3 ++-
> tests/xe/xe_prime_self_import.c | 8 ++++----
> tests/xe/xe_vm.c | 21 ++++++++++++++-------
> 14 files changed, 84 insertions(+), 56 deletions(-)
>
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index 856d0ba2..3266905c 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -100,7 +100,8 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
>
> vm = xe_vm_create(fd, 0, 0);
>
> - bo = xe_bo_create(fd, hwe->gt_id, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, hwe->gt_id));
> spin = xe_bo_map(fd, bo, 0x1000);
>
> xe_vm_bind_sync(fd, vm, bo, 0, addr, bo_size);
> diff --git a/tests/xe/xe_dma_buf_sync.c b/tests/xe/xe_dma_buf_sync.c
> index 8b97480a..3b4ee6bb 100644
> --- a/tests/xe/xe_dma_buf_sync.c
> +++ b/tests/xe/xe_dma_buf_sync.c
> @@ -122,7 +122,8 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0,
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd[0]),
> xe_get_default_alignment(fd[0]));
> for (i = 0; i < n_bo; ++i) {
> - bo[i] = xe_bo_create(fd[0], hwe0->gt_id, 0, bo_size);
> + bo[i] = xe_bo_create_flags(fd[0], 0, bo_size,
> + visible_vram_if_possible(fd[0], hwe0->gt_id));
> dma_buf_fd[i] = prime_handle_to_fd(fd[0], bo[i]);
> import_bo[i] = prime_fd_to_handle(fd[1], dma_buf_fd[i]);
>
> diff --git a/tests/xe/xe_evict.c b/tests/xe/xe_evict.c
> index eddbbd6f..26ed63de 100644
> --- a/tests/xe/xe_evict.c
> +++ b/tests/xe/xe_evict.c
> @@ -98,15 +98,17 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci,
> i < n_execs / 8 ? 0 : vm;
>
> if (flags & MULTI_VM) {
> - __bo = bo[i] = xe_bo_create(fd, eci->gt_id, 0,
> - bo_size);
> + __bo = bo[i] = xe_bo_create_flags(fd, 0,
> + bo_size,
> + visible_vram_memory(fd, eci->gt_id));
> } else if (flags & THREADED) {
> - __bo = bo[i] = xe_bo_create(fd, eci->gt_id, vm,
> - bo_size);
> + __bo = bo[i] = xe_bo_create_flags(fd, vm,
> + bo_size,
> + visible_vram_memory(fd, eci->gt_id));
> } else {
> __bo = bo[i] = xe_bo_create_flags(fd, _vm,
> bo_size,
> - vram_memory(fd, eci->gt_id) |
> + visible_vram_memory(fd, eci->gt_id) |
> system_memory(fd));
> }
> } else {
> @@ -281,16 +283,17 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci,
> i < n_execs / 8 ? 0 : vm;
>
> if (flags & MULTI_VM) {
> - __bo = bo[i] = xe_bo_create(fd, eci->gt_id,
> - 0, bo_size);
> + __bo = bo[i] = xe_bo_create_flags(fd, 0,
> + bo_size,
> + visible_vram_memory(fd, eci->gt_id));
> } else if (flags & THREADED) {
> - __bo = bo[i] = xe_bo_create(fd, eci->gt_id,
> - vm, bo_size);
> + __bo = bo[i] = xe_bo_create_flags(fd, vm,
> + bo_size,
> + visible_vram_memory(fd, eci->gt_id));
> } else {
> __bo = bo[i] = xe_bo_create_flags(fd, _vm,
> bo_size,
> - vram_memory(fd, eci->gt_id) |
> - system_memory(fd));
> + visible_vram_memory(fd, eci->gt_id));
> }
> } else {
> __bo = bo[i % (n_execs / 2)];
> @@ -455,7 +458,10 @@ threads(int fd, struct drm_xe_engine_class_instance *eci,
>
> static uint64_t calc_bo_size(uint64_t vram_size, int mul, int div)
> {
> - return (ALIGN(vram_size, 0x40000000) * mul) / div;
> + if (vram_size >= 0x40000000)
> + return (ALIGN(vram_size, 0x40000000) * mul) / div;
> + else
> + return (ALIGN(vram_size, 0x10000000) * mul) / div; /* small-bar */
> }
It's not directly related to this patch, although I'm just curious
because I don't know exactly how this test case was added in the first
place, since the part that comes in as an argument seems to be used to
calculate the size of the buffer to allocate, and since the mul and div
variables are not used except to determine the size of the buffer, why
not just put the value to be multiplied by the buffer directly into the
section?
rest of changes looks good to me.
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>
> /**
> @@ -670,7 +676,7 @@ igt_main
> fd = drm_open_driver(DRIVER_XE);
> xe_device_get(fd);
> igt_require(xe_has_vram(fd));
> - vram_size = xe_vram_size(fd, 0);
> + vram_size = xe_visible_vram_size(fd, 0);
> igt_assert(vram_size);
>
> xe_for_each_hw_engine(fd, hwe)
> diff --git a/tests/xe/xe_exec_balancer.c b/tests/xe/xe_exec_balancer.c
> index f3341a99..766e834c 100644
> --- a/tests/xe/xe_exec_balancer.c
> +++ b/tests/xe/xe_exec_balancer.c
> @@ -70,7 +70,7 @@ static void test_all_active(int fd, int gt, int class)
> bo_size = sizeof(*data) * num_placements;
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
>
> - bo = xe_bo_create(fd, gt, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
> data = xe_bo_map(fd, bo, bo_size);
>
> for (i = 0; i < num_placements; i++) {
> @@ -229,7 +229,7 @@ test_exec(int fd, int gt, int class, int n_engines, int n_execs,
> }
> memset(data, 0, bo_size);
> } else {
> - bo = xe_bo_create(fd, gt, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
> data = xe_bo_map(fd, bo, bo_size);
> }
>
> @@ -454,7 +454,7 @@ test_cm(int fd, int gt, int class, int n_engines, int n_execs,
> igt_assert(data);
> }
> } else {
> - bo = xe_bo_create(fd, gt, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> diff --git a/tests/xe/xe_exec_basic.c b/tests/xe/xe_exec_basic.c
> index 2a3cebd3..5e09e4a0 100644
> --- a/tests/xe/xe_exec_basic.c
> +++ b/tests/xe/xe_exec_basic.c
> @@ -129,15 +129,16 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
> }
> memset(data, 0, bo_size);
> } else {
> - if (flags & DEFER_ALLOC) {
> - bo = xe_bo_create_flags(fd, n_vm == 1 ? vm[0] : 0,
> - bo_size,
> - vram_if_possible(fd, eci->gt_id) |
> - XE_GEM_CREATE_FLAG_DEFER_BACKING);
> - } else {
> - bo = xe_bo_create(fd, eci->gt_id, n_vm == 1 ? vm[0] : 0,
> - bo_size);
> - }
> + uint32_t bo_flags;
> +
> + bo_flags = 0;
> + if (bo_flags & DEFER_ALLOC)
> + bo_flags |= XE_GEM_CREATE_FLAG_DEFER_BACKING;
> +
> + bo = xe_bo_create_flags(fd, n_vm == 1 ? vm[0] : 0,
> + bo_size,
> + visible_vram_if_possible(fd, eci->gt_id) |
> + bo_flags);
> if (!(flags & DEFER_BIND))
> data = xe_bo_map(fd, bo, bo_size);
> }
> diff --git a/tests/xe/xe_exec_compute_mode.c b/tests/xe/xe_exec_compute_mode.c
> index 60713a95..b06acd9b 100644
> --- a/tests/xe/xe_exec_compute_mode.c
> +++ b/tests/xe/xe_exec_compute_mode.c
> @@ -152,8 +152,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
> igt_assert(data);
> }
> } else {
> - bo = xe_bo_create(fd, eci->gt_id, flags & VM_FOR_BO ? vm : 0,
> - bo_size);
> + bo = xe_bo_create_flags(fd, flags & VM_FOR_BO ? vm : 0,
> + bo_size, visible_vram_if_possible(fd, eci->gt_id));
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> diff --git a/tests/xe/xe_exec_fault_mode.c b/tests/xe/xe_exec_fault_mode.c
> index b5d924a3..95eacfd5 100644
> --- a/tests/xe/xe_exec_fault_mode.c
> +++ b/tests/xe/xe_exec_fault_mode.c
> @@ -157,9 +157,11 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
> } else {
> if (flags & PREFETCH)
> bo = xe_bo_create_flags(fd, 0, bo_size,
> - all_memory_regions(fd));
> + all_memory_regions(fd) |
> + visible_vram_if_possible(fd, 0));
> else
> - bo = xe_bo_create(fd, eci->gt_id, 0, bo_size);
> + bo = xe_bo_create_flags(fd, 0, bo_size,
> + visible_vram_if_possible(fd, eci->gt_id));
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> @@ -390,8 +392,10 @@ test_atomic(int fd, struct drm_xe_engine_class_instance *eci,
> addr_wait = addr + bo_size;
>
> bo = xe_bo_create_flags(fd, vm, bo_size,
> - all_memory_regions(fd));
> - bo_wait = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> + all_memory_regions(fd) |
> + visible_vram_if_possible(fd, 0));
> + bo_wait = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, eci->gt_id));
> data = xe_bo_map(fd, bo, bo_size);
> wait = xe_bo_map(fd, bo_wait, bo_size);
> ptr = &data[0].data;
> diff --git a/tests/xe/xe_exec_reset.c b/tests/xe/xe_exec_reset.c
> index 57dc90dd..d171b3b3 100644
> --- a/tests/xe/xe_exec_reset.c
> +++ b/tests/xe/xe_exec_reset.c
> @@ -51,7 +51,8 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci)
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
>
> - bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, eci->gt_id));
> spin = xe_bo_map(fd, bo, bo_size);
>
> engine = xe_engine_create(fd, vm, eci, 0);
> @@ -197,7 +198,7 @@ test_balancer(int fd, int gt, int class, int n_engines, int n_execs,
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
>
> - bo = xe_bo_create(fd, gt, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
> data = xe_bo_map(fd, bo, bo_size);
>
> for (i = 0; i < n_engines; i++) {
> @@ -398,7 +399,8 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
>
> - bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, eci->gt_id));
> data = xe_bo_map(fd, bo, bo_size);
>
> for (i = 0; i < n_engines; i++) {
> @@ -577,7 +579,8 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci,
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
>
> - bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, eci->gt_id));
> data = xe_bo_map(fd, bo, bo_size);
> memset(data, 0, bo_size);
>
> @@ -710,7 +713,7 @@ static void submit_jobs(struct gt_thread_data *t)
> uint32_t bo;
> uint32_t *data;
>
> - bo = xe_bo_create(fd, 0, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
> data = xe_bo_map(fd, bo, bo_size);
> data[0] = MI_BATCH_BUFFER_END;
>
> diff --git a/tests/xe/xe_exec_threads.c b/tests/xe/xe_exec_threads.c
> index c34d8aec..1d7534e5 100644
> --- a/tests/xe/xe_exec_threads.c
> +++ b/tests/xe/xe_exec_threads.c
> @@ -107,7 +107,8 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
> igt_assert(data);
> }
> } else {
> - bo = xe_bo_create(fd, gt, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, gt));
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> @@ -309,7 +310,8 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
> igt_assert(data);
> }
> } else {
> - bo = xe_bo_create(fd, eci->gt_id, 0, bo_size);
> + bo = xe_bo_create_flags(fd, 0, bo_size,
> + visible_vram_if_possible(fd, eci->gt_id));
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> @@ -517,7 +519,8 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
> igt_assert(data);
> }
> } else {
> - bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, eci->gt_id));
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> diff --git a/tests/xe/xe_guc_pc.c b/tests/xe/xe_guc_pc.c
> index 60c93288..bf304bd7 100644
> --- a/tests/xe/xe_guc_pc.c
> +++ b/tests/xe/xe_guc_pc.c
> @@ -64,7 +64,8 @@ static void exec_basic(int fd, struct drm_xe_engine_class_instance *eci,
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
>
> - bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, eci->gt_id));
> data = xe_bo_map(fd, bo, bo_size);
>
> for (i = 0; i < n_engines; i++) {
> diff --git a/tests/xe/xe_mmap.c b/tests/xe/xe_mmap.c
> index 6b313a18..b23ce10c 100644
> --- a/tests/xe/xe_mmap.c
> +++ b/tests/xe/xe_mmap.c
> @@ -70,10 +70,10 @@ igt_main
> test_mmap(fd, system_memory(fd));
>
> igt_subtest("vram")
> - test_mmap(fd, vram_memory(fd, 0));
> + test_mmap(fd, visible_vram_memory(fd, 0));
>
> igt_subtest("vram-system")
> - test_mmap(fd, vram_memory(fd, 0) | system_memory(fd));
> + test_mmap(fd, visible_vram_memory(fd, 0) | system_memory(fd));
>
> igt_fixture {
> xe_device_put(fd);
> diff --git a/tests/xe/xe_pm.c b/tests/xe/xe_pm.c
> index 23b8246e..b3f47355 100644
> --- a/tests/xe/xe_pm.c
> +++ b/tests/xe/xe_pm.c
> @@ -250,7 +250,8 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
> if (check_rpm && runtime_usage_available(device.pci_xe))
> rpm_usage = igt_pm_get_runtime_usage(device.pci_xe);
>
> - bo = xe_bo_create(device.fd_xe, eci->gt_id, vm, bo_size);
> + bo = xe_bo_create_flags(device.fd_xe, vm, bo_size,
> + visible_vram_if_possible(device.fd_xe, eci->gt_id));
> data = xe_bo_map(device.fd_xe, bo, bo_size);
>
> for (i = 0; i < n_engines; i++) {
> diff --git a/tests/xe/xe_prime_self_import.c b/tests/xe/xe_prime_self_import.c
> index 5710cff9..97e330db 100644
> --- a/tests/xe/xe_prime_self_import.c
> +++ b/tests/xe/xe_prime_self_import.c
> @@ -107,7 +107,7 @@ static void test_with_fd_dup(void)
> fd2 = drm_open_driver(DRIVER_XE);
> xe_device_get(fd2);
>
> - handle = xe_bo_create(fd1, 0, 0, BO_SIZE);
> + handle = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
>
> dma_buf_fd1 = prime_handle_to_fd(fd1, handle);
> gem_close(fd1, handle);
> @@ -146,8 +146,8 @@ static void test_with_two_bos(void)
> fd2 = drm_open_driver(DRIVER_XE);
> xe_device_get(fd2);
>
> - handle1 = xe_bo_create(fd1, 0, 0, BO_SIZE);
> - handle2 = xe_bo_create(fd1, 0, 0, BO_SIZE);
> + handle1 = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
> + handle2 = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
>
> dma_buf_fd = prime_handle_to_fd(fd1, handle1);
> handle_import = prime_fd_to_handle(fd2, dma_buf_fd);
> @@ -225,7 +225,7 @@ static void test_with_one_bo(void)
> fd2 = drm_open_driver(DRIVER_XE);
> xe_device_get(fd2);
>
> - handle = xe_bo_create(fd1, 0, 0, BO_SIZE);
> + handle = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
>
> dma_buf_fd = prime_handle_to_fd(fd1, handle);
> handle_import1 = prime_fd_to_handle(fd2, dma_buf_fd);
> diff --git a/tests/xe/xe_vm.c b/tests/xe/xe_vm.c
> index 15356c70..96b12f60 100644
> --- a/tests/xe/xe_vm.c
> +++ b/tests/xe/xe_vm.c
> @@ -52,7 +52,8 @@ write_dwords(int fd, uint32_t vm, int n_dwords, uint64_t *addrs)
> batch_size = (n_dwords * 4 + 1) * sizeof(uint32_t);
> batch_size = ALIGN(batch_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
> - batch_bo = xe_bo_create(fd, 0, vm, batch_size);
> + batch_bo = xe_bo_create_flags(fd, vm, batch_size,
> + visible_vram_if_possible(fd, 0));
> batch_map = xe_bo_map(fd, batch_bo, batch_size);
>
> for (i = 0; i < n_dwords; i++) {
> @@ -116,7 +117,7 @@ __test_bind_one_bo(int fd, uint32_t vm, int n_addrs, uint64_t *addrs)
> vms = malloc(sizeof(*vms) * n_addrs);
> igt_assert(vms);
> }
> - bo = xe_bo_create(fd, 0, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
> map = xe_bo_map(fd, bo, bo_size);
> memset(map, 0, bo_size);
>
> @@ -549,7 +550,8 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
> xe_get_default_alignment(fd));
>
> for (i = 0; i < n_bo; ++i) {
> - bo[i] = xe_bo_create(fd, 0, vm, bo_size);
> + bo[i] = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, 0));
> data[i] = xe_bo_map(fd, bo[i], bo_size);
> }
>
> @@ -717,7 +719,7 @@ test_bind_engines_independent(int fd, struct drm_xe_engine_class_instance *eci)
> bo_size = sizeof(*data) * N_ENGINES;
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
> - bo = xe_bo_create(fd, 0, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
> data = xe_bo_map(fd, bo, bo_size);
>
> for (i = 0; i < N_ENGINES; i++) {
> @@ -874,7 +876,7 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
>
> - bo = xe_bo_create(fd, 0, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
> data = xe_bo_map(fd, bo, bo_size);
>
> if (flags & BIND_ARRAY_BIND_ENGINE_FLAG)
> @@ -1052,7 +1054,11 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci,
> map = aligned_alloc(xe_get_default_alignment(fd), bo_size);
> igt_assert(map);
> } else {
> - bo = xe_bo_create(fd, 0, vm, bo_size);
> + igt_skip_on(xe_visible_vram_size(fd, 0) && bo_size >
> + xe_visible_vram_size(fd, 0));
> +
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, 0));
> map = xe_bo_map(fd, bo, bo_size);
> }
>
> @@ -1329,7 +1335,8 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
> MAP_ANONYMOUS, -1, 0);
> igt_assert(data != MAP_FAILED);
> } else {
> - bo = xe_bo_create(fd, 0, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, 0));
> map = xe_bo_map(fd, bo, bo_size);
> }
> memset(map, 0, bo_size);
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 4/5] tests/xe/query: extend for CPU visible accounting
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 4/5] tests/xe/query: extend for CPU visible accounting Matthew Auld
@ 2023-04-17 5:54 ` Gwan-gyeong Mun
0 siblings, 0 replies; 16+ messages in thread
From: Gwan-gyeong Mun @ 2023-04-17 5:54 UTC (permalink / raw
To: Matthew Auld, igt-dev
On 3/29/23 2:56 PM, Matthew Auld wrote:
> Print the visible size and how much is used. Also sanity check the
> values.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
> tests/xe/xe_query.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/tests/xe/xe_query.c b/tests/xe/xe_query.c
> index 3f038225..9367d65e 100644
> --- a/tests/xe/xe_query.c
> +++ b/tests/xe/xe_query.c
> @@ -228,6 +228,21 @@ test_query_mem_usage(int fd)
> igt_info("min_page_size=0x%x, max_page_size=0x%x\n",
> mem_usage->regions[i].min_page_size,
> mem_usage->regions[i].max_page_size);
> +
> + igt_info("visible size=%lluMiB\n",
> + mem_usage->regions[i].cpu_visible_size >> 20);
> + igt_info("visible used=%lluMiB\n",
> + mem_usage->regions[i].cpu_visible_used >> 20);
> +
> + igt_assert_lte_u64(mem_usage->regions[i].cpu_visible_size,
> + mem_usage->regions[i].total_size);
> + igt_assert_lte_u64(mem_usage->regions[i].cpu_visible_used,
> + mem_usage->regions[i].cpu_visible_size);
> + igt_assert_lte_u64(mem_usage->regions[i].cpu_visible_used,
> + mem_usage->regions[i].used);
> + igt_assert_lte_u64(mem_usage->regions[i].used -
> + mem_usage->regions[i].cpu_visible_used,
> + mem_usage->regions[i].total_size);
Although not exactly the cpu visible sanity check that the title of this
commit refers to, but there is no sanity check between used and total_size.
If it's not a semantic duplicate check, could you add this sanity check
as well?
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> }
> dump_hex_debug(mem_usage, query.size);
> free(mem_usage);
^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] ✗ Fi.CI.BUILD: failure for IGT bits for small-bar (rev2)
2023-03-29 11:56 [igt-dev] [PATCH i-g-t 0/5] IGT bits for small-bar Matthew Auld
` (6 preceding siblings ...)
2023-03-30 2:29 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
@ 2023-05-17 14:40 ` Patchwork
7 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-05-17 14:40 UTC (permalink / raw
To: Matthew Auld; +Cc: igt-dev
== Series Details ==
Series: IGT bits for small-bar (rev2)
URL : https://patchwork.freedesktop.org/series/115786/
State : failure
== Summary ==
Applying: xe: sync small-bar uapi
Applying: lib/xe: add visible vram helpers
Using index info to reconstruct a base tree...
M lib/xe/xe_query.c
M lib/xe/xe_query.h
Falling back to patching base and 3-way merge...
Auto-merging lib/xe/xe_query.h
Auto-merging lib/xe/xe_query.c
Applying: tests/xe: handle small-bar systems
Using index info to reconstruct a base tree...
M tests/xe/xe_dma_buf_sync.c
M tests/xe/xe_evict.c
M tests/xe/xe_exec_balancer.c
M tests/xe/xe_exec_basic.c
M tests/xe/xe_exec_compute_mode.c
M tests/xe/xe_exec_fault_mode.c
M tests/xe/xe_exec_reset.c
M tests/xe/xe_exec_threads.c
M tests/xe/xe_guc_pc.c
M tests/xe/xe_pm.c
M tests/xe/xe_prime_self_import.c
M tests/xe/xe_vm.c
Falling back to patching base and 3-way merge...
Auto-merging tests/xe/xe_vm.c
CONFLICT (content): Merge conflict in tests/xe/xe_vm.c
Auto-merging tests/xe/xe_prime_self_import.c
Auto-merging tests/xe/xe_pm.c
Auto-merging tests/xe/xe_guc_pc.c
Auto-merging tests/xe/xe_exec_threads.c
Auto-merging tests/xe/xe_exec_reset.c
Auto-merging tests/xe/xe_exec_fault_mode.c
Auto-merging tests/xe/xe_exec_compute_mode.c
Auto-merging tests/xe/xe_exec_basic.c
Auto-merging tests/xe/xe_exec_balancer.c
Auto-merging tests/xe/xe_evict.c
Auto-merging tests/xe/xe_dma_buf_sync.c
Patch failed at 0003 tests/xe: handle small-bar systems
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 3/5] tests/xe: handle small-bar systems
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 3/5] tests/xe: handle small-bar systems Matthew Auld
2023-04-05 12:53 ` Gwan-gyeong Mun
@ 2023-05-17 17:03 ` Kamil Konieczny
1 sibling, 0 replies; 16+ messages in thread
From: Kamil Konieczny @ 2023-05-17 17:03 UTC (permalink / raw
To: igt-dev; +Cc: Matthew Auld
Hi Matthew,
On 2023-03-29 at 12:56:40 +0100, Matthew Auld wrote:
> Convert all the existing tests that require CPU access.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
> lib/xe/xe_spin.c | 3 ++-
Could you move this change into separate patch ?
lib/xe/xe_spin: handle small-bar systems
Please also rebase on latest igt.
> tests/xe/xe_dma_buf_sync.c | 3 ++-
> tests/xe/xe_evict.c | 32 +++++++++++++++++++-------------
> tests/xe/xe_exec_balancer.c | 6 +++---
> tests/xe/xe_exec_basic.c | 19 ++++++++++---------
> tests/xe/xe_exec_compute_mode.c | 4 ++--
> tests/xe/xe_exec_fault_mode.c | 12 ++++++++----
> tests/xe/xe_exec_reset.c | 13 ++++++++-----
> tests/xe/xe_exec_threads.c | 9 ++++++---
> tests/xe/xe_guc_pc.c | 3 ++-
> tests/xe/xe_mmap.c | 4 ++--
> tests/xe/xe_pm.c | 3 ++-
> tests/xe/xe_prime_self_import.c | 8 ++++----
> tests/xe/xe_vm.c | 21 ++++++++++++++-------
> 14 files changed, 84 insertions(+), 56 deletions(-)
>
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index 856d0ba2..3266905c 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -100,7 +100,8 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
>
> vm = xe_vm_create(fd, 0, 0);
>
> - bo = xe_bo_create(fd, hwe->gt_id, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, hwe->gt_id));
> spin = xe_bo_map(fd, bo, 0x1000);
>
> xe_vm_bind_sync(fd, vm, bo, 0, addr, bo_size);
> diff --git a/tests/xe/xe_dma_buf_sync.c b/tests/xe/xe_dma_buf_sync.c
> index 8b97480a..3b4ee6bb 100644
> --- a/tests/xe/xe_dma_buf_sync.c
> +++ b/tests/xe/xe_dma_buf_sync.c
> @@ -122,7 +122,8 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0,
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd[0]),
> xe_get_default_alignment(fd[0]));
> for (i = 0; i < n_bo; ++i) {
> - bo[i] = xe_bo_create(fd[0], hwe0->gt_id, 0, bo_size);
> + bo[i] = xe_bo_create_flags(fd[0], 0, bo_size,
> + visible_vram_if_possible(fd[0], hwe0->gt_id));
> dma_buf_fd[i] = prime_handle_to_fd(fd[0], bo[i]);
> import_bo[i] = prime_fd_to_handle(fd[1], dma_buf_fd[i]);
>
> diff --git a/tests/xe/xe_evict.c b/tests/xe/xe_evict.c
> index eddbbd6f..26ed63de 100644
> --- a/tests/xe/xe_evict.c
> +++ b/tests/xe/xe_evict.c
> @@ -98,15 +98,17 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci,
> i < n_execs / 8 ? 0 : vm;
>
> if (flags & MULTI_VM) {
> - __bo = bo[i] = xe_bo_create(fd, eci->gt_id, 0,
> - bo_size);
> + __bo = bo[i] = xe_bo_create_flags(fd, 0,
> + bo_size,
> + visible_vram_memory(fd, eci->gt_id));
> } else if (flags & THREADED) {
> - __bo = bo[i] = xe_bo_create(fd, eci->gt_id, vm,
> - bo_size);
> + __bo = bo[i] = xe_bo_create_flags(fd, vm,
> + bo_size,
> + visible_vram_memory(fd, eci->gt_id));
> } else {
> __bo = bo[i] = xe_bo_create_flags(fd, _vm,
> bo_size,
> - vram_memory(fd, eci->gt_id) |
> + visible_vram_memory(fd, eci->gt_id) |
> system_memory(fd));
> }
> } else {
> @@ -281,16 +283,17 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci,
> i < n_execs / 8 ? 0 : vm;
>
> if (flags & MULTI_VM) {
> - __bo = bo[i] = xe_bo_create(fd, eci->gt_id,
> - 0, bo_size);
> + __bo = bo[i] = xe_bo_create_flags(fd, 0,
> + bo_size,
> + visible_vram_memory(fd, eci->gt_id));
> } else if (flags & THREADED) {
> - __bo = bo[i] = xe_bo_create(fd, eci->gt_id,
> - vm, bo_size);
> + __bo = bo[i] = xe_bo_create_flags(fd, vm,
> + bo_size,
> + visible_vram_memory(fd, eci->gt_id));
> } else {
> __bo = bo[i] = xe_bo_create_flags(fd, _vm,
> bo_size,
> - vram_memory(fd, eci->gt_id) |
> - system_memory(fd));
> + visible_vram_memory(fd, eci->gt_id));
> }
> } else {
> __bo = bo[i % (n_execs / 2)];
> @@ -455,7 +458,10 @@ threads(int fd, struct drm_xe_engine_class_instance *eci,
>
> static uint64_t calc_bo_size(uint64_t vram_size, int mul, int div)
> {
> - return (ALIGN(vram_size, 0x40000000) * mul) / div;
> + if (vram_size >= 0x40000000)
> + return (ALIGN(vram_size, 0x40000000) * mul) / div;
---------------------------------------- ^
> + else
> + return (ALIGN(vram_size, 0x10000000) * mul) / div; /* small-bar */
---------------------------------------- ^
Could you use some const or defines instead of this ?
Like SZ_1GB and SZ_4GB ?
> }
>
> /**
> @@ -670,7 +676,7 @@ igt_main
> fd = drm_open_driver(DRIVER_XE);
> xe_device_get(fd);
> igt_require(xe_has_vram(fd));
> - vram_size = xe_vram_size(fd, 0);
> + vram_size = xe_visible_vram_size(fd, 0);
> igt_assert(vram_size);
>
> xe_for_each_hw_engine(fd, hwe)
> diff --git a/tests/xe/xe_exec_balancer.c b/tests/xe/xe_exec_balancer.c
> index f3341a99..766e834c 100644
> --- a/tests/xe/xe_exec_balancer.c
> +++ b/tests/xe/xe_exec_balancer.c
> @@ -70,7 +70,7 @@ static void test_all_active(int fd, int gt, int class)
> bo_size = sizeof(*data) * num_placements;
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
>
> - bo = xe_bo_create(fd, gt, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
> data = xe_bo_map(fd, bo, bo_size);
>
> for (i = 0; i < num_placements; i++) {
> @@ -229,7 +229,7 @@ test_exec(int fd, int gt, int class, int n_engines, int n_execs,
> }
> memset(data, 0, bo_size);
> } else {
> - bo = xe_bo_create(fd, gt, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
> data = xe_bo_map(fd, bo, bo_size);
> }
>
> @@ -454,7 +454,7 @@ test_cm(int fd, int gt, int class, int n_engines, int n_execs,
> igt_assert(data);
> }
> } else {
> - bo = xe_bo_create(fd, gt, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> diff --git a/tests/xe/xe_exec_basic.c b/tests/xe/xe_exec_basic.c
> index 2a3cebd3..5e09e4a0 100644
> --- a/tests/xe/xe_exec_basic.c
> +++ b/tests/xe/xe_exec_basic.c
> @@ -129,15 +129,16 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
> }
> memset(data, 0, bo_size);
> } else {
> - if (flags & DEFER_ALLOC) {
------------------- ^
> - bo = xe_bo_create_flags(fd, n_vm == 1 ? vm[0] : 0,
> - bo_size,
> - vram_if_possible(fd, eci->gt_id) |
> - XE_GEM_CREATE_FLAG_DEFER_BACKING);
> - } else {
> - bo = xe_bo_create(fd, eci->gt_id, n_vm == 1 ? vm[0] : 0,
> - bo_size);
> - }
> + uint32_t bo_flags;
> +
> + bo_flags = 0;
imho better:
bo_flags = visible_vram_if_possible(fd, eci->gt_id);
see below.
> + if (bo_flags & DEFER_ALLOC)
------------------- ^
s/bo_flags/flags/
> + bo_flags |= XE_GEM_CREATE_FLAG_DEFER_BACKING;
> +
> + bo = xe_bo_create_flags(fd, n_vm == 1 ? vm[0] : 0,
> + bo_size,
> + visible_vram_if_possible(fd, eci->gt_id) |
--------------------------------------- ^
Why not move this to bo_flags init above ?
Regards,
Kamil
> + bo_flags);
> if (!(flags & DEFER_BIND))
> data = xe_bo_map(fd, bo, bo_size);
> }
> diff --git a/tests/xe/xe_exec_compute_mode.c b/tests/xe/xe_exec_compute_mode.c
> index 60713a95..b06acd9b 100644
> --- a/tests/xe/xe_exec_compute_mode.c
> +++ b/tests/xe/xe_exec_compute_mode.c
> @@ -152,8 +152,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
> igt_assert(data);
> }
> } else {
> - bo = xe_bo_create(fd, eci->gt_id, flags & VM_FOR_BO ? vm : 0,
> - bo_size);
> + bo = xe_bo_create_flags(fd, flags & VM_FOR_BO ? vm : 0,
> + bo_size, visible_vram_if_possible(fd, eci->gt_id));
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> diff --git a/tests/xe/xe_exec_fault_mode.c b/tests/xe/xe_exec_fault_mode.c
> index b5d924a3..95eacfd5 100644
> --- a/tests/xe/xe_exec_fault_mode.c
> +++ b/tests/xe/xe_exec_fault_mode.c
> @@ -157,9 +157,11 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
> } else {
> if (flags & PREFETCH)
> bo = xe_bo_create_flags(fd, 0, bo_size,
> - all_memory_regions(fd));
> + all_memory_regions(fd) |
> + visible_vram_if_possible(fd, 0));
> else
> - bo = xe_bo_create(fd, eci->gt_id, 0, bo_size);
> + bo = xe_bo_create_flags(fd, 0, bo_size,
> + visible_vram_if_possible(fd, eci->gt_id));
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> @@ -390,8 +392,10 @@ test_atomic(int fd, struct drm_xe_engine_class_instance *eci,
> addr_wait = addr + bo_size;
>
> bo = xe_bo_create_flags(fd, vm, bo_size,
> - all_memory_regions(fd));
> - bo_wait = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> + all_memory_regions(fd) |
> + visible_vram_if_possible(fd, 0));
> + bo_wait = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, eci->gt_id));
> data = xe_bo_map(fd, bo, bo_size);
> wait = xe_bo_map(fd, bo_wait, bo_size);
> ptr = &data[0].data;
> diff --git a/tests/xe/xe_exec_reset.c b/tests/xe/xe_exec_reset.c
> index 57dc90dd..d171b3b3 100644
> --- a/tests/xe/xe_exec_reset.c
> +++ b/tests/xe/xe_exec_reset.c
> @@ -51,7 +51,8 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci)
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
>
> - bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, eci->gt_id));
> spin = xe_bo_map(fd, bo, bo_size);
>
> engine = xe_engine_create(fd, vm, eci, 0);
> @@ -197,7 +198,7 @@ test_balancer(int fd, int gt, int class, int n_engines, int n_execs,
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
>
> - bo = xe_bo_create(fd, gt, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
> data = xe_bo_map(fd, bo, bo_size);
>
> for (i = 0; i < n_engines; i++) {
> @@ -398,7 +399,8 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
>
> - bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, eci->gt_id));
> data = xe_bo_map(fd, bo, bo_size);
>
> for (i = 0; i < n_engines; i++) {
> @@ -577,7 +579,8 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci,
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
>
> - bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, eci->gt_id));
> data = xe_bo_map(fd, bo, bo_size);
> memset(data, 0, bo_size);
>
> @@ -710,7 +713,7 @@ static void submit_jobs(struct gt_thread_data *t)
> uint32_t bo;
> uint32_t *data;
>
> - bo = xe_bo_create(fd, 0, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
> data = xe_bo_map(fd, bo, bo_size);
> data[0] = MI_BATCH_BUFFER_END;
>
> diff --git a/tests/xe/xe_exec_threads.c b/tests/xe/xe_exec_threads.c
> index c34d8aec..1d7534e5 100644
> --- a/tests/xe/xe_exec_threads.c
> +++ b/tests/xe/xe_exec_threads.c
> @@ -107,7 +107,8 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
> igt_assert(data);
> }
> } else {
> - bo = xe_bo_create(fd, gt, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, gt));
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> @@ -309,7 +310,8 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
> igt_assert(data);
> }
> } else {
> - bo = xe_bo_create(fd, eci->gt_id, 0, bo_size);
> + bo = xe_bo_create_flags(fd, 0, bo_size,
> + visible_vram_if_possible(fd, eci->gt_id));
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> @@ -517,7 +519,8 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
> igt_assert(data);
> }
> } else {
> - bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, eci->gt_id));
> data = xe_bo_map(fd, bo, bo_size);
> }
> memset(data, 0, bo_size);
> diff --git a/tests/xe/xe_guc_pc.c b/tests/xe/xe_guc_pc.c
> index 60c93288..bf304bd7 100644
> --- a/tests/xe/xe_guc_pc.c
> +++ b/tests/xe/xe_guc_pc.c
> @@ -64,7 +64,8 @@ static void exec_basic(int fd, struct drm_xe_engine_class_instance *eci,
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
>
> - bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, eci->gt_id));
> data = xe_bo_map(fd, bo, bo_size);
>
> for (i = 0; i < n_engines; i++) {
> diff --git a/tests/xe/xe_mmap.c b/tests/xe/xe_mmap.c
> index 6b313a18..b23ce10c 100644
> --- a/tests/xe/xe_mmap.c
> +++ b/tests/xe/xe_mmap.c
> @@ -70,10 +70,10 @@ igt_main
> test_mmap(fd, system_memory(fd));
>
> igt_subtest("vram")
> - test_mmap(fd, vram_memory(fd, 0));
> + test_mmap(fd, visible_vram_memory(fd, 0));
>
> igt_subtest("vram-system")
> - test_mmap(fd, vram_memory(fd, 0) | system_memory(fd));
> + test_mmap(fd, visible_vram_memory(fd, 0) | system_memory(fd));
>
> igt_fixture {
> xe_device_put(fd);
> diff --git a/tests/xe/xe_pm.c b/tests/xe/xe_pm.c
> index 23b8246e..b3f47355 100644
> --- a/tests/xe/xe_pm.c
> +++ b/tests/xe/xe_pm.c
> @@ -250,7 +250,8 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
> if (check_rpm && runtime_usage_available(device.pci_xe))
> rpm_usage = igt_pm_get_runtime_usage(device.pci_xe);
>
> - bo = xe_bo_create(device.fd_xe, eci->gt_id, vm, bo_size);
> + bo = xe_bo_create_flags(device.fd_xe, vm, bo_size,
> + visible_vram_if_possible(device.fd_xe, eci->gt_id));
> data = xe_bo_map(device.fd_xe, bo, bo_size);
>
> for (i = 0; i < n_engines; i++) {
> diff --git a/tests/xe/xe_prime_self_import.c b/tests/xe/xe_prime_self_import.c
> index 5710cff9..97e330db 100644
> --- a/tests/xe/xe_prime_self_import.c
> +++ b/tests/xe/xe_prime_self_import.c
> @@ -107,7 +107,7 @@ static void test_with_fd_dup(void)
> fd2 = drm_open_driver(DRIVER_XE);
> xe_device_get(fd2);
>
> - handle = xe_bo_create(fd1, 0, 0, BO_SIZE);
> + handle = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
>
> dma_buf_fd1 = prime_handle_to_fd(fd1, handle);
> gem_close(fd1, handle);
> @@ -146,8 +146,8 @@ static void test_with_two_bos(void)
> fd2 = drm_open_driver(DRIVER_XE);
> xe_device_get(fd2);
>
> - handle1 = xe_bo_create(fd1, 0, 0, BO_SIZE);
> - handle2 = xe_bo_create(fd1, 0, 0, BO_SIZE);
> + handle1 = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
> + handle2 = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
>
> dma_buf_fd = prime_handle_to_fd(fd1, handle1);
> handle_import = prime_fd_to_handle(fd2, dma_buf_fd);
> @@ -225,7 +225,7 @@ static void test_with_one_bo(void)
> fd2 = drm_open_driver(DRIVER_XE);
> xe_device_get(fd2);
>
> - handle = xe_bo_create(fd1, 0, 0, BO_SIZE);
> + handle = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
>
> dma_buf_fd = prime_handle_to_fd(fd1, handle);
> handle_import1 = prime_fd_to_handle(fd2, dma_buf_fd);
> diff --git a/tests/xe/xe_vm.c b/tests/xe/xe_vm.c
> index 15356c70..96b12f60 100644
> --- a/tests/xe/xe_vm.c
> +++ b/tests/xe/xe_vm.c
> @@ -52,7 +52,8 @@ write_dwords(int fd, uint32_t vm, int n_dwords, uint64_t *addrs)
> batch_size = (n_dwords * 4 + 1) * sizeof(uint32_t);
> batch_size = ALIGN(batch_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
> - batch_bo = xe_bo_create(fd, 0, vm, batch_size);
> + batch_bo = xe_bo_create_flags(fd, vm, batch_size,
> + visible_vram_if_possible(fd, 0));
> batch_map = xe_bo_map(fd, batch_bo, batch_size);
>
> for (i = 0; i < n_dwords; i++) {
> @@ -116,7 +117,7 @@ __test_bind_one_bo(int fd, uint32_t vm, int n_addrs, uint64_t *addrs)
> vms = malloc(sizeof(*vms) * n_addrs);
> igt_assert(vms);
> }
> - bo = xe_bo_create(fd, 0, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
> map = xe_bo_map(fd, bo, bo_size);
> memset(map, 0, bo_size);
>
> @@ -549,7 +550,8 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
> xe_get_default_alignment(fd));
>
> for (i = 0; i < n_bo; ++i) {
> - bo[i] = xe_bo_create(fd, 0, vm, bo_size);
> + bo[i] = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, 0));
> data[i] = xe_bo_map(fd, bo[i], bo_size);
> }
>
> @@ -717,7 +719,7 @@ test_bind_engines_independent(int fd, struct drm_xe_engine_class_instance *eci)
> bo_size = sizeof(*data) * N_ENGINES;
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
> - bo = xe_bo_create(fd, 0, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
> data = xe_bo_map(fd, bo, bo_size);
>
> for (i = 0; i < N_ENGINES; i++) {
> @@ -874,7 +876,7 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
> bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
> xe_get_default_alignment(fd));
>
> - bo = xe_bo_create(fd, 0, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
> data = xe_bo_map(fd, bo, bo_size);
>
> if (flags & BIND_ARRAY_BIND_ENGINE_FLAG)
> @@ -1052,7 +1054,11 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci,
> map = aligned_alloc(xe_get_default_alignment(fd), bo_size);
> igt_assert(map);
> } else {
> - bo = xe_bo_create(fd, 0, vm, bo_size);
> + igt_skip_on(xe_visible_vram_size(fd, 0) && bo_size >
> + xe_visible_vram_size(fd, 0));
> +
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, 0));
> map = xe_bo_map(fd, bo, bo_size);
> }
>
> @@ -1329,7 +1335,8 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
> MAP_ANONYMOUS, -1, 0);
> igt_assert(data != MAP_FAILED);
> } else {
> - bo = xe_bo_create(fd, 0, vm, bo_size);
> + bo = xe_bo_create_flags(fd, vm, bo_size,
> + visible_vram_if_possible(fd, 0));
> map = xe_bo_map(fd, bo, bo_size);
> }
> memset(map, 0, bo_size);
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2023-05-17 17:05 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-03-29 11:56 [igt-dev] [PATCH i-g-t 0/5] IGT bits for small-bar Matthew Auld
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 1/5] xe: sync small-bar uapi Matthew Auld
2023-04-02 23:46 ` Gwan-gyeong Mun
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 2/5] lib/xe: add visible vram helpers Matthew Auld
2023-04-03 9:18 ` Gwan-gyeong Mun
2023-04-03 12:39 ` Matthew Auld
2023-04-03 14:17 ` Gwan-gyeong Mun
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 3/5] tests/xe: handle small-bar systems Matthew Auld
2023-04-05 12:53 ` Gwan-gyeong Mun
2023-05-17 17:03 ` Kamil Konieczny
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 4/5] tests/xe/query: extend for CPU visible accounting Matthew Auld
2023-04-17 5:54 ` Gwan-gyeong Mun
2023-03-29 11:56 ` [igt-dev] [PATCH i-g-t 5/5] tests/xe/mmap: sanity check small-bar Matthew Auld
2023-03-29 12:39 ` [igt-dev] ✓ Fi.CI.BAT: success for IGT bits for small-bar Patchwork
2023-03-30 2:29 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2023-05-17 14:40 ` [igt-dev] ✗ Fi.CI.BUILD: failure for IGT bits for small-bar (rev2) Patchwork
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