From: Krzysztof Kozlowski <krzk@kernel.org>
To: Roman Kisel <romank@linux.microsoft.com>
Cc: arnd@arndb.de, bhelgaas@google.com, bp@alien8.de,
catalin.marinas@arm.com, conor+dt@kernel.org,
dave.hansen@linux.intel.com, decui@microsoft.com,
haiyangz@microsoft.com, hpa@zytor.com, krzk+dt@kernel.org,
kw@linux.com, kys@microsoft.com, lpieralisi@kernel.org,
manivannan.sadhasivam@linaro.org, mingo@redhat.com,
robh@kernel.org, ssengar@linux.microsoft.com,
tglx@linutronix.de, wei.liu@kernel.org, will@kernel.org,
devicetree@vger.kernel.org, linux-arch@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-hyperv@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, x86@kernel.org,
benhill@microsoft.com, bperkins@microsoft.com,
sunilmut@microsoft.com
Subject: Re: [PATCH hyperv-next v4 4/6] dt-bindings: microsoft,vmbus: Add GIC and DMA coherence to the example
Date: Wed, 12 Feb 2025 07:42:28 +0100 [thread overview]
Message-ID: <20250212-rough-terrier-of-serendipity-68a0db@krzk-bin> (raw)
In-Reply-To: <20250212014321.1108840-5-romank@linux.microsoft.com>
On Tue, Feb 11, 2025 at 05:43:19PM -0800, Roman Kisel wrote:
> The existing example lacks the GIC interrupt controller property
> making it not possible to boot on ARM64, and it lacks the DMA
GIC controller is not relevant to this binding.
> coherence property making the kernel do more work on maintaining
> CPU caches on ARM64 although the VMBus trancations are cache-coherent.
>
> Add the GIC node, specify DMA coherence, and define interrupt-parent
> and interrupts properties in the example to provide a complete reference
> for platforms utilizing GIC-based interrupts, and add the DMA coherence
> property to not do extra work on the architectures where DMA defaults to
> non cache-coherent.
>
> Signed-off-by: Roman Kisel <romank@linux.microsoft.com>
> ---
> .../devicetree/bindings/bus/microsoft,vmbus.yaml | 11 +++++++++++
> 1 file changed, 11 insertions(+)
Last time I said: not tested by automation.
Now: I see automation build failures, although I do not see anything
incorrect in the code, so that's a bit surprising. Please confirm that
binding was tested on latest dtschema.
>
> diff --git a/Documentation/devicetree/bindings/bus/microsoft,vmbus.yaml b/Documentation/devicetree/bindings/bus/microsoft,vmbus.yaml
> index a8d40c766dcd..5ec69226ab85 100644
> --- a/Documentation/devicetree/bindings/bus/microsoft,vmbus.yaml
> +++ b/Documentation/devicetree/bindings/bus/microsoft,vmbus.yaml
> @@ -44,11 +44,22 @@ examples:
> #size-cells = <1>;
> ranges;
>
> + gic: intc@fe200000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0xfe200000 0x0 0x10000>, /* GIC Dist */
> + <0x0 0xfe280000 0x0 0x200000>; /* GICR */
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + }
I fail to see how this is relevant here. This is example only of vmbus.
Look how other bindings are done. Drop the example.
> +
> vmbus@ff0000000 {
> compatible = "microsoft,vmbus";
> #address-cells = <2>;
> #size-cells = <1>;
> ranges = <0x0f 0xf0000000 0x0f 0xf0000000 0x10000000>;
> + dma-coherent;
> + interrupt-parent = <&gic>;
> + interrupts = <1 2 1>;
Use proper defines for known constants.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-02-12 6:42 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-12 1:43 [PATCH hyperv-next v4 0/6] arm64: hyperv: Support Virtual Trust Level Boot Roman Kisel
2025-02-12 1:43 ` [PATCH hyperv-next v4 1/6] arm64: hyperv: Use SMCCC to detect hypervisor presence Roman Kisel
2025-02-12 6:54 ` Arnd Bergmann
2025-02-13 23:23 ` Roman Kisel
2025-02-14 8:05 ` Arnd Bergmann
2025-02-14 16:47 ` Roman Kisel
2025-02-24 23:22 ` Roman Kisel
2025-02-25 7:24 ` Arnd Bergmann
2025-02-25 22:25 ` Roman Kisel
2025-02-26 13:57 ` Arnd Bergmann
2025-02-19 23:13 ` Michael Kelley
2025-02-20 16:34 ` Roman Kisel
2025-02-12 1:43 ` [PATCH hyperv-next v4 2/6] Drivers: hv: Enable VTL mode for arm64 Roman Kisel
2025-02-19 23:14 ` Michael Kelley
2025-02-20 16:36 ` Roman Kisel
2025-02-12 1:43 ` [PATCH hyperv-next v4 3/6] Drivers: hv: Provide arch-neutral implementation of get_vtl() Roman Kisel
2025-02-19 23:17 ` Michael Kelley
2025-02-12 1:43 ` [PATCH hyperv-next v4 4/6] dt-bindings: microsoft,vmbus: Add GIC and DMA coherence to the example Roman Kisel
2025-02-12 6:42 ` Krzysztof Kozlowski [this message]
2025-02-12 23:57 ` Roman Kisel
2025-02-13 20:50 ` Roman Kisel
2025-02-12 1:43 ` [PATCH hyperv-next v4 5/6] Drivers: hv: vmbus: Get the IRQ number from DeviceTree Roman Kisel
2025-02-19 23:20 ` Michael Kelley
2025-02-12 1:43 ` [PATCH hyperv-next v4 6/6] PCI: hv: Get vPCI MSI IRQ domain " Roman Kisel
2025-02-12 17:42 ` Bjorn Helgaas
2025-02-18 22:32 ` Roman Kisel
2025-02-19 23:51 ` Roman Kisel
2025-02-19 23:29 ` Michael Kelley
2025-02-20 16:41 ` Roman Kisel
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