From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60088) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z2APe-0003wO-O0 for qemu-devel@nongnu.org; Mon, 08 Jun 2015 23:41:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z2APd-0000ry-Hc for qemu-devel@nongnu.org; Mon, 08 Jun 2015 23:41:18 -0400 Received: from [59.151.112.132] (port=12998 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z2APZ-0000LN-4D for qemu-devel@nongnu.org; Mon, 08 Jun 2015 23:41:17 -0400 From: Chen Fan Date: Tue, 9 Jun 2015 11:37:35 +0800 Message-ID: <266e5900ade44572789aca7cf4fba16dacf35ba0.1433812962.git.chen.fan.fnst@cn.fujitsu.com> In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [RFC v9 07/18] vfio: add aer support for vfio device List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: izumi.taku@jp.fujitsu.com, alex.williamson@redhat.com Calling pcie_aer_init to initilize aer related registers for vfio device, then reload physical related registers to expose device capability. Signed-off-by: Chen Fan --- hw/vfio/pci.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 54303d9..7a3fad7 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -32,6 +32,7 @@ #include "hw/pci/msi.h" #include "hw/pci/msix.h" #include "hw/pci/pci.h" +#include "hw/pci/pci_bridge.h" #include "qemu-common.h" #include "qemu/error-report.h" #include "qemu/event_notifier.h" @@ -160,6 +161,8 @@ typedef struct VFIOPCIDevice { #define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT) #define VFIO_FEATURE_ENABLE_REQ_BIT 1 #define VFIO_FEATURE_ENABLE_REQ (1 << VFIO_FEATURE_ENABLE_REQ_BIT) +#define VFIO_FEATURE_ENABLE_AER_BIT 2 +#define VFIO_FEATURE_ENABLE_AER (1 << VFIO_FEATURE_ENABLE_AER_BIT) int32_t bootindex; uint8_t pm_cap; bool has_vga; @@ -2819,12 +2822,81 @@ static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos) return 0; } +static int vfio_setup_aer(VFIOPCIDevice *vdev, uint8_t cap_ver, + int pos, uint16_t size) +{ + PCIDevice *pdev = &vdev->pdev; + uint8_t *exp_cap = pdev->config + pdev->exp.exp_cap; + PCIDevice *dev_iter; + uint8_t type; + uint32_t severity, errcap; + int ret; + + if (!(vdev->features & VFIO_FEATURE_ENABLE_AER)) { + pcie_add_capability(pdev, PCI_EXT_CAP_ID_ERR, + cap_ver, pos, size); + return 0; + } + + dev_iter = pci_bridge_get_device(pdev->bus); + if (!dev_iter) { + goto error; + } + + while (dev_iter) { + type = pcie_cap_get_type(dev_iter); + if ((type != PCI_EXP_TYPE_ROOT_PORT && + type != PCI_EXP_TYPE_UPSTREAM && + type != PCI_EXP_TYPE_DOWNSTREAM)) { + goto error; + } + + if (!dev_iter->exp.aer_cap) { + goto error; + } + + dev_iter = pci_bridge_get_device(dev_iter->bus); + } + + errcap = vfio_pci_read_config(pdev, pdev->exp.aer_cap + PCI_ERR_CAP, 4); + /* + * The ability to record multiple headers is depending on + * the state of the Multiple Header Recording Capable bit and + * enabled by the Multiple Header Recording Enable bit. + */ + if ((errcap & PCI_ERR_CAP_MHRC) && + (errcap & PCI_ERR_CAP_MHRE)) { + pdev->exp.aer_log.log_max = PCIE_AER_LOG_MAX_DEFAULT; + } else { + pdev->exp.aer_log.log_max = 0; + } + + pcie_cap_deverr_init(pdev); + ret = pcie_aer_init(pdev, pos, size); + if (ret) { + return ret; + } + + /* load physical registers */ + severity = vfio_pci_read_config(pdev, + pdev->exp.aer_cap + PCI_ERR_UNCOR_SEVER, 4); + pci_long_test_and_clear_mask(exp_cap + PCI_ERR_UNCOR_SEVER, ~severity); + + return 0; + +error: + error_report("vfio: Unable to enable AER for device %s, parent bus " + "does not support AER signaling", vdev->vbasedev.name); + return -1; +} + static int vfio_add_ext_cap(VFIOPCIDevice *vdev, const uint8_t *config) { PCIDevice *pdev = &vdev->pdev; uint32_t header; uint16_t cap_id, next, size; uint8_t cap_ver; + int ret = 0; for (next = PCI_CONFIG_SPACE_SIZE; next; next = PCI_EXT_CAP_NEXT(pci_get_long(config + next))) { @@ -2840,7 +2912,19 @@ static int vfio_add_ext_cap(VFIOPCIDevice *vdev, const uint8_t *config) */ size = vfio_ext_cap_max_size(config, next); - pcie_add_capability(pdev, cap_id, cap_ver, next, size); + switch (cap_id) { + case PCI_EXT_CAP_ID_ERR: + ret = vfio_setup_aer(vdev, cap_ver, next, size); + break; + default: + pcie_add_capability(pdev, cap_id, cap_ver, next, size); + break; + } + + if (ret) { + return ret; + } + if (next == PCI_CONFIG_SPACE_SIZE) { /* Begin the rebuild, we should set the next offset zero. */ pci_set_long(pdev->config + next, PCI_EXT_CAP(cap_id, cap_ver, 0)); -- 1.9.3