* [PATCH] riscv: hwprobe: export Zihintpause ISA extension
@ 2024-02-19 15:49 ` Clément Léger
0 siblings, 0 replies; 6+ messages in thread
From: Clément Léger @ 2024-02-19 15:49 UTC (permalink / raw
To: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou,
linux-doc, linux-riscv, linux-kernel
Cc: Clément Léger, Robbin Ehn
Export the Zihintpause ISA extension through hwprobe which allows using
"pause" instructions. Some userspace applications (OpenJDK for
instance) uses this to handle some locking back-off.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
Documentation/arch/riscv/hwprobe.rst | 4 ++++
arch/riscv/include/uapi/asm/hwprobe.h | 1 +
arch/riscv/kernel/sys_hwprobe.c | 1 +
3 files changed, 6 insertions(+)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index b2bcc9eed9aa..0012c8433613 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -188,6 +188,10 @@ The following keys are defined:
manual starting from commit 95cf1f9 ("Add changes requested by Ved
during signoff")
+ * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is
+ supported as defined in the RISC-V ISA manual starting from commit commit
+ d8ab5c78c207 ("Zihintpause is ratified").
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 9f2a8e3ff204..31c570cbd1c5 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -59,6 +59,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
+#define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index a7c56b41efd2..1008d25880e1 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -111,6 +111,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
EXT_KEY(ZTSO);
EXT_KEY(ZACAS);
EXT_KEY(ZICOND);
+ EXT_KEY(ZIHINTPAUSE);
if (has_vector()) {
EXT_KEY(ZVBB);
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] riscv: hwprobe: export Zihintpause ISA extension
@ 2024-02-19 15:49 ` Clément Léger
0 siblings, 0 replies; 6+ messages in thread
From: Clément Léger @ 2024-02-19 15:49 UTC (permalink / raw
To: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou,
linux-doc, linux-riscv, linux-kernel
Cc: Clément Léger, Robbin Ehn
Export the Zihintpause ISA extension through hwprobe which allows using
"pause" instructions. Some userspace applications (OpenJDK for
instance) uses this to handle some locking back-off.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
Documentation/arch/riscv/hwprobe.rst | 4 ++++
arch/riscv/include/uapi/asm/hwprobe.h | 1 +
arch/riscv/kernel/sys_hwprobe.c | 1 +
3 files changed, 6 insertions(+)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index b2bcc9eed9aa..0012c8433613 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -188,6 +188,10 @@ The following keys are defined:
manual starting from commit 95cf1f9 ("Add changes requested by Ved
during signoff")
+ * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is
+ supported as defined in the RISC-V ISA manual starting from commit commit
+ d8ab5c78c207 ("Zihintpause is ratified").
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 9f2a8e3ff204..31c570cbd1c5 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -59,6 +59,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
+#define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index a7c56b41efd2..1008d25880e1 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -111,6 +111,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
EXT_KEY(ZTSO);
EXT_KEY(ZACAS);
EXT_KEY(ZICOND);
+ EXT_KEY(ZIHINTPAUSE);
if (has_vector()) {
EXT_KEY(ZVBB);
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: hwprobe: export Zihintpause ISA extension
2024-02-19 15:49 ` Clément Léger
@ 2024-02-20 23:42 ` Atish Patra
-1 siblings, 0 replies; 6+ messages in thread
From: Atish Patra @ 2024-02-20 23:42 UTC (permalink / raw
To: Clément Léger, Jonathan Corbet, Paul Walmsley,
Palmer Dabbelt, Albert Ou, linux-doc, linux-riscv, linux-kernel
Cc: Robbin Ehn
On 2/19/24 07:49, Clément Léger wrote:
> Export the Zihintpause ISA extension through hwprobe which allows using
> "pause" instructions. Some userspace applications (OpenJDK for
> instance) uses this to handle some locking back-off.
>
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
>
> ---
> Documentation/arch/riscv/hwprobe.rst | 4 ++++
> arch/riscv/include/uapi/asm/hwprobe.h | 1 +
> arch/riscv/kernel/sys_hwprobe.c | 1 +
> 3 files changed, 6 insertions(+)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index b2bcc9eed9aa..0012c8433613 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -188,6 +188,10 @@ The following keys are defined:
> manual starting from commit 95cf1f9 ("Add changes requested by Ved
> during signoff")
>
> + * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is
> + supported as defined in the RISC-V ISA manual starting from commit commit
> + d8ab5c78c207 ("Zihintpause is ratified").
> +
> * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
> information about the selected set of processors.
>
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 9f2a8e3ff204..31c570cbd1c5 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -59,6 +59,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
> #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
> #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
> +#define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36)
> #define RISCV_HWPROBE_KEY_CPUPERF_0 5
> #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index a7c56b41efd2..1008d25880e1 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -111,6 +111,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> EXT_KEY(ZTSO);
> EXT_KEY(ZACAS);
> EXT_KEY(ZICOND);
> + EXT_KEY(ZIHINTPAUSE);
>
> if (has_vector()) {
> EXT_KEY(ZVBB);
Reviewed-by: Atish Patra <atishp@rivosinc.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: hwprobe: export Zihintpause ISA extension
@ 2024-02-20 23:42 ` Atish Patra
0 siblings, 0 replies; 6+ messages in thread
From: Atish Patra @ 2024-02-20 23:42 UTC (permalink / raw
To: Clément Léger, Jonathan Corbet, Paul Walmsley,
Palmer Dabbelt, Albert Ou, linux-doc, linux-riscv, linux-kernel
Cc: Robbin Ehn
On 2/19/24 07:49, Clément Léger wrote:
> Export the Zihintpause ISA extension through hwprobe which allows using
> "pause" instructions. Some userspace applications (OpenJDK for
> instance) uses this to handle some locking back-off.
>
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
>
> ---
> Documentation/arch/riscv/hwprobe.rst | 4 ++++
> arch/riscv/include/uapi/asm/hwprobe.h | 1 +
> arch/riscv/kernel/sys_hwprobe.c | 1 +
> 3 files changed, 6 insertions(+)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index b2bcc9eed9aa..0012c8433613 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -188,6 +188,10 @@ The following keys are defined:
> manual starting from commit 95cf1f9 ("Add changes requested by Ved
> during signoff")
>
> + * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is
> + supported as defined in the RISC-V ISA manual starting from commit commit
> + d8ab5c78c207 ("Zihintpause is ratified").
> +
> * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
> information about the selected set of processors.
>
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 9f2a8e3ff204..31c570cbd1c5 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -59,6 +59,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
> #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
> #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
> +#define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36)
> #define RISCV_HWPROBE_KEY_CPUPERF_0 5
> #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index a7c56b41efd2..1008d25880e1 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -111,6 +111,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> EXT_KEY(ZTSO);
> EXT_KEY(ZACAS);
> EXT_KEY(ZICOND);
> + EXT_KEY(ZIHINTPAUSE);
>
> if (has_vector()) {
> EXT_KEY(ZVBB);
Reviewed-by: Atish Patra <atishp@rivosinc.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: hwprobe: export Zihintpause ISA extension
2024-02-20 23:42 ` Atish Patra
@ 2024-02-21 8:06 ` Clément Léger
-1 siblings, 0 replies; 6+ messages in thread
From: Clément Léger @ 2024-02-21 8:06 UTC (permalink / raw
To: Atish Patra, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt,
Albert Ou, linux-doc, linux-riscv, linux-kernel
Cc: Robbin Ehn
On 21/02/2024 00:42, Atish Patra wrote:
> during signoff")
> + * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause
> extension is
> + supported as defined in the RISC-V ISA manual starting from
> commit commit
Looks like I did a typo ("commit" twice). Let me send a V2.
Clément
> + d8ab5c78c207 ("Zihintpause is ratified").
> +
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: hwprobe: export Zihintpause ISA extension
@ 2024-02-21 8:06 ` Clément Léger
0 siblings, 0 replies; 6+ messages in thread
From: Clément Léger @ 2024-02-21 8:06 UTC (permalink / raw
To: Atish Patra, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt,
Albert Ou, linux-doc, linux-riscv, linux-kernel
Cc: Robbin Ehn
On 21/02/2024 00:42, Atish Patra wrote:
> during signoff")
> + * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause
> extension is
> + supported as defined in the RISC-V ISA manual starting from
> commit commit
Looks like I did a typo ("commit" twice). Let me send a V2.
Clément
> + d8ab5c78c207 ("Zihintpause is ratified").
> +
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
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2024-02-19 15:49 [PATCH] riscv: hwprobe: export Zihintpause ISA extension Clément Léger
2024-02-19 15:49 ` Clément Léger
2024-02-20 23:42 ` Atish Patra
2024-02-20 23:42 ` Atish Patra
2024-02-21 8:06 ` Clément Léger
2024-02-21 8:06 ` Clément Léger
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