From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EE01C4332F for ; Mon, 27 Dec 2021 17:37:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230365AbhL0RhE (ORCPT ); Mon, 27 Dec 2021 12:37:04 -0500 Received: from 113.196.136.162.ll.static.sparqnet.net ([113.196.136.162]:58372 "EHLO mg.sunplus.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230338AbhL0RhC (ORCPT ); Mon, 27 Dec 2021 12:37:02 -0500 X-MailGates: (flag:3,DYNAMIC,RELAY,NOHOST:PASS)(compute_score:DELIVER,40 ,3) Received: from 172.17.9.112 by mg01.sunplus.com with MailGates ESMTP Server V5.0(4599:0:AUTH_RELAY) (envelope-from ); Tue, 28 Dec 2021 01:36:59 +0800 (CST) Received: from sphcmbx02.sunplus.com.tw (172.17.9.112) by sphcmbx02.sunplus.com.tw (172.17.9.112) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Tue, 28 Dec 2021 01:36:59 +0800 Received: from sphcmbx02.sunplus.com.tw ([fe80::fd3d:ad1a:de2a:18bd]) by sphcmbx02.sunplus.com.tw ([fe80::fd3d:ad1a:de2a:18bd%14]) with mapi id 15.00.1497.026; Tue, 28 Dec 2021 01:36:59 +0800 From: =?big5?B?V2VsbHMgTHUgp2aq2sTL?= To: Rob Herring , Wells Lu CC: "linus.walleij@linaro.org" , "linux-gpio@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "dvorkin@tibbo.com" Subject: RE: [PATCH v5 1/2] dt-bindings: pinctrl: Add dt-bindings for Sunplus SP7021 Thread-Topic: [PATCH v5 1/2] dt-bindings: pinctrl: Add dt-bindings for Sunplus SP7021 Thread-Index: AQHX+JsIGEz+1S7LlUitkhzfzPTvr6xGATGAgACWILA= Date: Mon, 27 Dec 2021 17:36:59 +0000 Message-ID: <54d148935bb84a64894872c07196e99d@sphcmbx02.sunplus.com.tw> References: <1640331779-18277-1-git-send-email-wellslutw@gmail.com> <1640331779-18277-2-git-send-email-wellslutw@gmail.com> In-Reply-To: Accept-Language: zh-TW, en-US Content-Language: zh-TW X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [172.25.108.39] Content-Type: text/plain; charset="big5" Content-Transfer-Encoding: base64 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SGkgUm9iLA0KDQpUaGFua3MgYSBsb3QgZm9yIHJldmlldy4NCg0KUGxlYXNlIHNlZSBteSByZXBs aWVzIGJlbG93Og0KDQoNCj4gPiBBZGQgZHQtYmluZGluZ3MgaGVhZGVyIGZpbGVzIGFuZCBkb2N1 bWVudGF0aW9uIGZvciBTdW5wbHVzIFNQNzAyMSBTb0MuDQo+ID4NCj4gPiBTaWduZWQtb2ZmLWJ5 OiBXZWxscyBMdSA8d2VsbHNsdXR3QGdtYWlsLmNvbT4NCj4gPiAtLS0NCj4gPiBDaGFuZ2VzIGlu IFY1DQo+ID4gICAtIFJlbW92ZWQgIkdQSU9YVDIiIHJlZ2lzdGVycw0KPiA+DQo+ID4gIC4uLi9i aW5kaW5ncy9waW5jdHJsL3N1bnBsdXMsc3A3MDIxLXBpbmN0cmwueWFtbCAgIHwgMzczICsrKysr KysrKysrKysrKysrKysrKw0KPiA+ICBNQUlOVEFJTkVSUyAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICB8ICAgOSArDQo+ID4gIGluY2x1ZGUvZHQtYmluZGluZ3MvcGluY3Ry bC9zcHBjdGwtc3A3MDIxLmggICAgICAgIHwgMTcxICsrKysrKysrKysNCj4gPiAgaW5jbHVkZS9k dC1iaW5kaW5ncy9waW5jdHJsL3NwcGN0bC5oICAgICAgICAgICAgICAgfCAgMzAgKysNCj4gPiAg NCBmaWxlcyBjaGFuZ2VkLCA1ODMgaW5zZXJ0aW9ucygrKQ0KPiA+ICBjcmVhdGUgbW9kZSAxMDA2 NDQNCj4gPiBEb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvcGluY3RybC9zdW5wbHVz LHNwNzAyMS1waW5jdHJsLnlhbWwNCj4gPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGluY2x1ZGUvZHQt YmluZGluZ3MvcGluY3RybC9zcHBjdGwtc3A3MDIxLmgNCj4gPiAgY3JlYXRlIG1vZGUgMTAwNjQ0 IGluY2x1ZGUvZHQtYmluZGluZ3MvcGluY3RybC9zcHBjdGwuaA0KPiA+DQo+ID4gZGlmZiAtLWdp dA0KPiA+IGEvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL3BpbmN0cmwvc3VucGx1 cyxzcDcwMjEtcGluY3RybC55YW0NCj4gPiBsDQo+ID4gYi9Eb2N1bWVudGF0aW9uL2RldmljZXRy ZWUvYmluZGluZ3MvcGluY3RybC9zdW5wbHVzLHNwNzAyMS1waW5jdHJsLnlhbQ0KPiA+IGwNCj4g PiBuZXcgZmlsZSBtb2RlIDEwMDY0NA0KPiA+IGluZGV4IDAwMDAwMDAuLjI2NzIxNjkNCj4gPiAt LS0gL2Rldi9udWxsDQo+ID4gKysrIGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdz L3BpbmN0cmwvc3VucGx1cyxzcDcwMjEtcGluY3RybA0KPiA+ICsrKyAueWFtbA0KPiA+IEBAIC0w LDAgKzEsMzczIEBADQo+ID4gKyMgU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IChHUEwtMi4wLW9u bHkgT1IgQlNELTItQ2xhdXNlKSAjIENvcHlyaWdodA0KPiA+ICsoQykgU3VucGx1cyBDby4sIEx0 ZC4NCj4gPiArJVlBTUwgMS4yDQo+ID4gKy0tLQ0KPiA+ICskaWQ6DQo+ID4gK2h0dHA6Ly9kZXZp Y2V0cmVlLm9yZy9zY2hlbWFzL3BpbmN0cmwvc3VucGx1cyxzcDcwMjEtcGluY3RybC55YW1sIw0K PiA+ICskc2NoZW1hOiBodHRwOi8vZGV2aWNldHJlZS5vcmcvbWV0YS1zY2hlbWFzL2NvcmUueWFt bCMNCj4gPiArDQo+ID4gK3RpdGxlOiBTdW5wbHVzIFNQNzAyMSBQaW4gQ29udHJvbGxlciBEZXZp Y2UgVHJlZSBCaW5kaW5ncw0KPiA+ICsNCj4gPiArbWFpbnRhaW5lcnM6DQo+ID4gKyAgLSBEdm9y a2luIERtaXRyeSA8ZHZvcmtpbkB0aWJiby5jb20+DQo+ID4gKyAgLSBXZWxscyBMdSA8d2VsbHNs dXR3QGdtYWlsLmNvbT4NCj4gPiArDQo+ID4gK2Rlc2NyaXB0aW9uOiB8DQo+ID4gKyAgVGhlIFN1 bnBsdXMgU1A3MDIxIHBpbiBjb250cm9sbGVyIGlzIHVzZWQgdG8gY29udHJvbCBTb0MgcGlucy4N Cj4gPiArUGxlYXNlDQo+ID4gKyAgcmVmZXIgdG8gcGluY3RybC1iaW5kaW5ncy50eHQgaW4gdGhp cyBkaXJlY3RvcnkgZm9yIGRldGFpbHMgb2YgdGhlDQo+ID4gK2NvbW1vbg0KPiA+ICsgIHBpbmN0 cmwgYmluZGluZ3MgdXNlZCBieSBjbGllbnQgZGV2aWNlcy4NCj4gPiArDQo+ID4gKyAgU1A3MDIx IGhhcyA5OSBkaWdpdGFsIEdQSU8gcGlucyB3aGljaCBhcmUgbnVtYmVyZWQgZnJvbSBHUElPIDAg dG8NCj4gPiArIDk4LiBBbGwgIGFyZSBtdWx0aXBsZXhlZCB3aXRoIHNvbWUgc3BlY2lhbCBmdW5j dGlvbiBwaW5zLiBTUDcwMjEgaGFzDQo+ID4gKyAzIHR5cGVzIG9mICBzcGVjaWFsIGZ1bmN0aW9u IHBpbnM6DQo+ID4gKw0KPiA+ICsgICgxKSBmdW5jdGlvbi1ncm91cCBwaW5zOg0KPiA+ICsgICAg ICBFeCAxIChTUEktTk9SIGZsYXNoKToNCj4gPiArICAgICAgICBJZiBjb250cm9sLWZpZWxkIFNQ SV9GTEFTSF9TRUwgaXMgc2V0IHRvIDEsIEdQSU8gODMsIDg0LCA4NiBhbmQgODcNCj4gPiArICAg ICAgICB3aWxsIGJlIHBpbnMgb2YgU1BJLU5PUiBmbGFzaC4gSWYgaXQgaXMgc2V0IHRvIDIsIEdQ SU8gNzYsIDc4LCA3OQ0KPiA+ICsgICAgICAgIGFuZCA4MSB3aWxsIGJlIHBpbnMgb2YgU1BJLU5P UiBmbGFzaC4NCj4gPiArDQo+ID4gKyAgICAgIEV4IDIgKFVBUlRfMCk6DQo+ID4gKyAgICAgICAg SWYgY29udHJvbC1iaXQgVUEwX1NFTCBpcyBzZXQgdG8gMSwgR1BJTyA4OCBhbmQgODkgd2lsbCBi ZSBUWCBhbmQNCj4gPiArICAgICAgICBSWCBwaW5zIG9mIFVBUlRfMCAoVUFSVCBjaGFubmVsIDAp Lg0KPiA+ICsNCj4gPiArICAgICAgRXggMyAoZU1NQyk6DQo+ID4gKyAgICAgICAgSWYgY29udHJv bC1iaXQgRU1NQ19TRUwgaXMgc2V0IHRvIDEsIEdQSU8gNzIsIDczLCA3NCwgNzUsIDc2LCA3NywN Cj4gPiArICAgICAgICA3OCwgNzksIDgwLCA4MSB3aWxsIGJlIHBpbnMgb2YgYW4gZU1NQyBkZXZp Y2UuDQo+ID4gKw0KPiA+ICsgICAgICBQcm9wZXJ0aWVzICJmdW5jdGlvbiIgYW5kICJncm91cHMi IGFyZSB1c2VkIHRvIHNlbGVjdCBmdW5jdGlvbi1ncm91cA0KPiA+ICsgICAgICBwaW5zLg0KPiA+ ICsNCj4gPiArICAoMikgZnVsbHkgcGluLW11eCAobGlrZSBwaG9uZSBleGNoYW5nZSBtdXgpIHBp bnM6DQo+ID4gKyAgICAgIEdQSU8gOCB0byA3MSBhcmUgJ2Z1bGx5IHBpbi1tdXgnIHBpbnMuIEFu eSBwaW5zIG9mIHBlcmlwaGVyYWxzIG9mDQo+ID4gKyAgICAgIFNQNzAyMSAoZXg6IFVBUlRfMSwg VUFSVF8yLCBVQVJUXzMsIFVBUlRfNCwgSTJDXzAsIEkyQ18xLCBhbmQgZXRjLikNCj4gPiArICAg ICAgY2FuIGJlIHJvdXRlZCB0byBhbnkgcGlucyBvZiBmdWxseSBwaW4tbXV4IHBpbnMuDQo+ID4g Kw0KPiA+ICsgICAgICBFeCAxIChVQVJUIGNoYW5uZWwgMSk6DQo+ID4gKyAgICAgICAgSWYgY29u dHJvbC1maWVsZCBVQTFfVFhfU0VMIGlzIHNldCB0byAzLCBUWCBwaW4gb2YgVUFSVF8xIHdpbGwg YmUNCj4gPiArICAgICAgICByb3V0ZWQgdG8gR1BJTyAxMCAoMyAtIDEgKyA4ID0gMTApLg0KPiA+ ICsgICAgICAgIElmIGNvbnRyb2wtZmllbGQgVUExX1JYX1NFTCBpcyBzZXQgdG8gNCwgUlggcGlu IG9mIFVBUlRfMSB3aWxsIGJlDQo+ID4gKyAgICAgICAgcm91dGVkIHRvIEdQSU8gMTEgKDQgLSAx ICsgOCA9IDExKS4NCj4gPiArICAgICAgICBJZiBjb250cm9sLWZpZWxkIFVBMV9SVFNfU0VMIGlz IHNldCB0byA1LCBSVFMgcGluIG9mIFVBUlRfMSB3aWxsDQo+ID4gKyAgICAgICAgYmUgcm91dGVk IHRvIEdQSU8gMTIgKDUgLSAxICsgOCA9IDEyKS4NCj4gPiArICAgICAgICBJZiBjb250cm9sLWZp ZWxkIFVBMV9DVFNfU0VMIGlzIHNldCB0byA2LCBDVFMgcGluIG9mIFVBUlRfMSB3aWxsDQo+ID4g KyAgICAgICAgYmUgcm91dGVkIHRvIEdQSU8gMTMgKDYgLSAxICsgOCA9IDEzKS4NCj4gPiArDQo+ ID4gKyAgICAgIEV4IDIgKEkyQyBjaGFubmVsIDApOg0KPiA+ICsgICAgICAgIElmIGNvbnRyb2wt ZmllbGQgSTJDMF9DTEtfU0VMIGlzIHNldCB0byAyMCwgQ0xLIHBpbiBvZiBJMkNfMCB3aWxsDQo+ ID4gKyAgICAgICAgYmUgcm91dGVkIHRvIEdQSU8gMjcgKDIwIC0gMSArIDggPSAyNykuDQo+ID4g KyAgICAgICAgSWYgY29udHJvbC1maWVsZCBJMkMwX0RBVEFfU0VMIGlzIHNldCB0byAyMSwgREFU QSBwaW4gb2YgSTJDXzANCj4gPiArICAgICAgICB3aWxsIGJlIHJvdXRlZCB0byBHUElPIDI4ICgy MSAtIDEgKyA5ID0gMjgpLg0KPiA+ICsNCj4gPiArICAgICAgVG90YWxseSwgU1A3MDIxIGhhcyAx MjAgcGVyaXBoZXJhbCBwaW5zLiBUaGUgcGVyaXBoZXJhbCBwaW5zIGNhbiBiZQ0KPiA+ICsgICAg ICByb3V0ZWQgdG8gYW55IG9mIDY0ICdmdWxseSBwaW4tbXV4JyBwaW5zLg0KPiA+ICsNCj4gPiAr ICAoMykgSS9PIHByb2Nlc3NvciBwaW5zDQo+ID4gKyAgICAgIFNQNzAyMSBoYXMgYSBidWlsdC1p biBJL08gcHJvY2Vzc29yLg0KPiA+ICsgICAgICBBbnkgR1BJTyBwaW5zIChHUElPIDAgdG8gOTgp IGNhbiBiZSBzZXQgdG8gcGlucyBvZiBJL08gcHJvY2Vzc29yLg0KPiA+ICsNCj4gPiArICBWZW5k b3IgcHJvcGVydHkgInN1bnBsdXMscGlucyIgaXMgdXNlZCB0byBzZWxlY3QgImZ1bGx5IHBpbi1t dXgiDQo+ID4gKyBwaW5zLCAgIkkvTyBwcm9jZXNzb3IgcGlucyIgYW5kICJkaWdpdGFsIEdQSU8i IHBpbnMuDQo+ID4gKw0KPiA+ICsgIFRoZSBkZXZpY2Ugbm9kZSBvZiBwaW4gY29udHJvbGxlciBv ZiBTdW5wbHVzIFNQNzAyMSBoYXMgZm9sbG93aW5nDQo+ID4gKyBwcm9wZXJ0aWVzLg0KPiA+ICsN Cj4gPiArcHJvcGVydGllczoNCj4gPiArICBjb21wYXRpYmxlOg0KPiA+ICsgICAgY29uc3Q6IHN1 bnBsdXMsc3A3MDIxLXBjdGwNCj4gPiArDQo+ID4gKyAgZ3Bpby1jb250cm9sbGVyOiB0cnVlDQo+ ID4gKw0KPiA+ICsgICcjZ3Bpby1jZWxscyc6DQo+ID4gKyAgICBjb25zdDogMg0KPiA+ICsNCj4g PiArICByZWc6DQo+ID4gKyAgICBpdGVtczoNCj4gPiArICAgICAgLSBkZXNjcmlwdGlvbjogdGhl IE1PT04yIHJlZ2lzdGVycw0KPiA+ICsgICAgICAtIGRlc2NyaXB0aW9uOiB0aGUgR1BJT1hUIHJl Z2lzdGVycw0KPiA+ICsgICAgICAtIGRlc2NyaXB0aW9uOiB0aGUgRklSU1QgcmVnaXN0ZXJzDQo+ ID4gKyAgICAgIC0gZGVzY3JpcHRpb246IHRoZSBNT09OMSByZWdpc3RlcnMNCj4gPiArDQo+ID4g KyAgcmVnLW5hbWVzOg0KPiA+ICsgICAgaXRlbXM6DQo+ID4gKyAgICAgIC0gY29uc3Q6IG1vb24y DQo+ID4gKyAgICAgIC0gY29uc3Q6IGdwaW94dA0KPiA+ICsgICAgICAtIGNvbnN0OiBmaXJzdA0K PiA+ICsgICAgICAtIGNvbnN0OiBtb29uMQ0KPiA+ICsNCj4gPiArICBjbG9ja3M6DQo+ID4gKyAg ICBtYXhJdGVtczogMQ0KPiA+ICsNCj4gPiArICByZXNldHM6DQo+ID4gKyAgICBtYXhJdGVtczog MQ0KPiA+ICsNCj4gPiArcGF0dGVyblByb3BlcnRpZXM6DQo+ID4gKyAgJy1waW5zJCc6DQo+ID4g KyAgICB0eXBlOiBvYmplY3QNCj4gPiArICAgIGRlc2NyaXB0aW9uOiB8DQo+ID4gKyAgICAgIEEg cGluY3RybCBub2RlIHNob3VsZCBjb250YWluIGF0IGxlYXN0IG9uZSBzdWJub2RlcyByZXByZXNl bnRpbmcgdGhlDQo+ID4gKyAgICAgIHBpbnMgb3IgZnVuY3Rpb24tcGlucyBncm91cCBhdmFpbGFi bGUgb24gdGhlIG1hY2hpbmUuIEVhY2ggc3Vibm9kZQ0KPiA+ICsgICAgICB3aWxsIGxpc3QgdGhl IHBpbnMgaXQgbmVlZHMsIGFuZCBob3cgdGhleSBzaG91bGQgYmUgY29uZmlndXJlZC4NCj4gPiAr DQo+ID4gKyAgICAgIFBpbmN0cmwgbm9kZSdzIGNsaWVudCBkZXZpY2VzIHVzZSBzdWJub2RlcyBm b3IgZGVzaXJlZCBwaW4NCj4gPiArICAgICAgY29uZmlndXJhdGlvbi4gQ2xpZW50IGRldmljZSBz dWJub2RlcyB1c2UgYmVsb3cgc3RhbmRhcmQgcHJvcGVydGllcy4NCj4gDQo+IE5lZWQgYSAkcmVm IHRvIHBpbm11eC1ub2RlLnlhbWwNCg0KSSdsbCBhZGQgIiRyZWYgdG8gcGlubXV4LW5vZGUueWFt bCIgbmV4dCBwYXRjaC4NCg0KDQo+ID4gKw0KPiA+ICsgICAgcHJvcGVydGllczoNCj4gPiArICAg ICAgc3VucGx1cyxwaW5zOg0KPiANCj4gQ2FuJ3QgeW91IGp1c3QgdXNlICdwaW5zJyBoZXJlPw0K DQpObywgcHJvcGVydHkgInN1bnBsdXMscGlucyIgZGVmaW5lZCBoZXJlIGlzIGRpZmZlcmVudCBm cm9tIHN0YW5kYXJkIHByb3BlcnR5ICJwaW5zIi4NCk1yLiBMaW51cyBXYWxsZWlqIGFza2VkIG1l IHRvIGFkZCAic3VucGx1cywiIHByZWZpeC4NCg0KDQo+ID4gKyAgICAgICAgZGVzY3JpcHRpb246 IHwNCj4gPiArICAgICAgICAgIERlZmluZSAnc3VucGx1cyxwaW5zJyB3aGljaCBhcmUgdXNlZCBi eSBwaW5jdHJsIG5vZGUncyBjbGllbnQNCj4gPiArICAgICAgICAgIGRldmljZS4NCj4gPiArDQo+ ID4gKyAgICAgICAgICBJdCBjb25zaXN0cyBvZiBvbmUgb3IgbW9yZSBpbnRlZ2VycyB3aGljaCBy ZXByZXNlbnRzIHRoZSBjb25maWcNCj4gPiArICAgICAgICAgIHNldHRpbmcgZm9yIGNvcnJlc3Bv bmRpbmcgcGluLiBFYWNoIGludGVnZXIgZGVmaW5lcyBhIGluZGl2aWR1YWwNCj4gPiArICAgICAg ICAgIHBpbiBpbiB3aGljaDoNCj4gPiArDQo+ID4gKyAgICAgICAgICBCaXQgMzJ+MjQ6IGRlZmlu ZXMgR1BJTyBudW1iZXIuIEl0cyByYW5nZSBpcyAwIH4gOTguDQo+ID4gKyAgICAgICAgICBCaXQg MjN+MTY6IGRlZmluZXMgdHlwZXM6ICgxKSBmdWxseSBwaW4tbXV4IHBpbnMNCj4gPiArICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgKDIpIElPIHByb2Nlc3NvciBwaW5zDQo+ID4g KyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICgzKSBkaWdpdGFsIEdQSU8gcGlu cw0KPiA+ICsgICAgICAgICAgQml0IDE1fjg6ICBkZWZpbmVzIHBpbnMgb2YgcGVyaXBoZXJhbHMg KHdoaWNoIGFyZSBkZWZpbmVkIGluDQo+ID4gKyAgICAgICAgICAgICAgICAgICAgICdpbmNsdWRl L2R0LWJpbmdpbmcvcGluY3RybC9zcHBjdGwuaCcpLg0KPiA+ICsgICAgICAgICAgQml0IDd+MDog ICBkZWZpbmVzIHR5cGVzIG9yIGluaXRpYWwtc3RhdGUgb2YgZGlnaXRhbCBHUElPIHBpbnMuDQo+ ID4gKw0KPiA+ICsgICAgICAgICAgUGxlYXNlIHVzZSBtYWNybyBTUFBDVExfSU9QQUQgdG8gZGVm aW5lIHRoZSBpbnRlZ2VycyBmb3IgcGlucy4NCj4gPiArDQo+ID4gKyAgICAgICAgJHJlZjogL3Nj aGVtYXMvdHlwZXMueWFtbCMvZGVmaW5pdGlvbnMvdWludDMyLWFycmF5DQo+ID4gKw0KPiA+ICsg ICAgICBmdW5jdGlvbjoNCj4gPiArICAgICAgICBkZXNjcmlwdGlvbjogfA0KPiA+ICsgICAgICAg ICAgRGVmaW5lIHBpbi1mdW5jdGlvbiB3aGljaCBpcyB1c2VkIGJ5IHBpbmN0cmwgbm9kZSdzIGNs aWVudCBkZXZpY2UuDQo+ID4gKyAgICAgICAgICBUaGUgbmFtZSBzaG91bGQgYmUgb25lIG9mIHN0 cmluZyBpbiB0aGUgZm9sbG93aW5nIGVudW1lcmF0aW9uLg0KPiA+ICsgICAgICAgICRyZWY6ICIv c2NoZW1hcy90eXBlcy55YW1sIy9kZWZpbml0aW9ucy9zdHJpbmciDQo+ID4gKyAgICAgICAgZW51 bTogWyBTUElfRkxBU0gsIFNQSV9GTEFTSF80QklULCBTUElfTkFORCwgQ0FSRDBfRU1NQywgU0Rf Q0FSRCwNCj4gPiArICAgICAgICAgICAgICAgIFVBMCwgRlBHQV9JRlgsIEhETUlfVFgsIExDRElG LCBVU0IwX09URywgVVNCMV9PVEcgXQ0KPiA+ICsNCj4gPiArICAgICAgZ3JvdXBzOg0KPiA+ICsg ICAgICAgIGRlc2NyaXB0aW9uOiB8DQo+ID4gKyAgICAgICAgICBEZWZpbmUgcGluLWdyb3VwIGlu IGEgc3BlY2lmaWVkIHBpbi1mdW5jdGlvbi4NCj4gPiArICAgICAgICAgIFRoZSBuYW1lIHNob3Vs ZCBiZSBvbmUgb2Ygc3RyaW5nIGluIHRoZSBmb2xsb3dpbmcgZW51bWVyYXRpb24uDQo+ID4gKyAg ICAgICAgJHJlZjogIi9zY2hlbWFzL3R5cGVzLnlhbWwjL2RlZmluaXRpb25zL3N0cmluZyINCj4g PiArICAgICAgICBlbnVtOiBbIFNQSV9GTEFTSDEsIFNQSV9GTEFTSDIsIFNQSV9GTEFTSF80QklU MSwgU1BJX0ZMQVNIXzRCSVQyLA0KPiA+ICsgICAgICAgICAgICAgICAgU1BJX05BTkQsIENBUkQw X0VNTUMsIFNEX0NBUkQsIFVBMCwgRlBHQV9JRlgsIEhETUlfVFgxLA0KPiA+ICsgICAgICAgICAg ICAgICAgSERNSV9UWDIsIEhETUlfVFgzLCBMQ0RJRiwgVVNCMF9PVEcsIFVTQjFfT1RHIF0NCj4g PiArDQo+ID4gKyAgICAgIHN1bnBsdXMsemVyb19mdW5jOg0KPiANCj4gRG9uJ3QgdXNlICdfJyBp biBwcm9wZXJ0eSBuYW1lcy4NCg0KSSdsbCByZW5hbWUgaXQgdG8gInN1bnBsdXMsemVyb2Z1bmMi IG5leHQgcGF0Y2guDQoNCg0KPiA+ICsgICAgICAgIGRlc2NyaXB0aW9uOiB8DQo+ID4gKyAgICAg ICAgICBUaGlzIGlzIGEgdmVuZG9yIHNwZWNpZmljIHByb3BlcnR5LiBJdCBpcyB1c2VkIHRvIGRp c2FibGUgcGlucw0KPiA+ICsgICAgICAgICAgd2hpY2ggYXJlIG5vdCB1c2VkIGJ5IHBpbmN0cmwg bm9kZSdzIGNsaWVudCBkZXZpY2UuDQo+ID4gKyAgICAgICAgICBTb21lIHBpbnMgbWF5IGJlIGVu YWJsZWQgYnkgYm9vdC1sb2FkZXIuIFdlIGNhbiB1c2UgdGhpcw0KPiA+ICsgICAgICAgICAgcHJv cGVydHkgdG8gZGlzYWJsZSB0aGVtLg0KPiA+ICsgICAgICAgICRyZWY6IC9zY2hlbWFzL3R5cGVz LnlhbWwjL2RlZmluaXRpb25zL3VpbnQzMi1hcnJheQ0KPiANCj4gSU1PLCBkaXNhYmxlZCBwaW5z IHNob3VsZCBiZSB1bnVzZWQgYnkgdGhlIGJvYXJkIGRlc2lnbiwgbm90IG9uZXMgdGhlIGJvb3Rs b2FkZXIgZmFpbGVkDQo+IHRvIGRpc2FibGUuDQoNCkkgYW0gc29ycnkuIEkgZG9uJ3QgdW5kZXJz dGFuZCB0aGlzIGNvbW1lbnQuDQpDb3VsZCBJIGhhdmUgbW9yZSBleHBsYW5hdGlvbj8gV2hhdCBp cyBJTU8/DQoNClRoZSBwcm9wZXJ0eSAic3VucGx1cyx6ZXJvZnVuYyIgaXMgdXNlZCB0byBkaXNh YmxlIHBpbnMgd2hpY2ggYXJlIA0KZW5hYmxlZCBieSBib290LWxvYWRlci4NCg0KRm9yIGV4YW1w bGUsIGJvb3QtbG9hZGVyLCBVLUJvb3QsIGVuYWJsZXMgYSBzZXQgb2YgSTJDIHBpbnMuIFRoZSBJ MkMgDQpwaW5zIGtlZXAgZW5hYmxlZCB3aGVuIExpbnV4IGJvb3QgdXAuIFdlIGNhbiB1c2UgInN1 bnBsdXMsemVyb2Z1bmMiIA0KdG8gZGlzYWJsZSB0aGUgSTJDIHBpbnMgaW4gTGludXguDQoNCg0K PiA+ICsNCj4gPiArICAgIGFkZGl0aW9uYWxQcm9wZXJ0aWVzOiBmYWxzZQ0KPiA+ICsNCj4gPiAr ICAgIGFsbE9mOg0KPiA+ICsgICAgICAtIGlmOg0KPiA+ICsgICAgICAgICAgcHJvcGVydGllczoN Cj4gPiArICAgICAgICAgICAgZnVuY3Rpb246DQo+ID4gKyAgICAgICAgICAgICAgZW51bToNCj4g PiArICAgICAgICAgICAgICAgIC0gU1BJX0ZMQVNIDQo+ID4gKyAgICAgICAgdGhlbjoNCj4gPiAr ICAgICAgICAgIHByb3BlcnRpZXM6DQo+ID4gKyAgICAgICAgICAgIGdyb3VwczoNCj4gPiArICAg ICAgICAgICAgICBlbnVtOg0KPiA+ICsgICAgICAgICAgICAgICAgLSBTUElfRkxBU0gxDQo+ID4g KyAgICAgICAgICAgICAgICAtIFNQSV9GTEFTSDINCj4gPiArICAgICAgLSBpZjoNCj4gPiArICAg ICAgICAgIHByb3BlcnRpZXM6DQo+ID4gKyAgICAgICAgICAgIGZ1bmN0aW9uOg0KPiA+ICsgICAg ICAgICAgICAgIGVudW06DQo+ID4gKyAgICAgICAgICAgICAgICAtIFNQSV9GTEFTSF80QklUDQo+ ID4gKyAgICAgICAgdGhlbjoNCj4gPiArICAgICAgICAgIHByb3BlcnRpZXM6DQo+ID4gKyAgICAg ICAgICAgIGdyb3VwczoNCj4gPiArICAgICAgICAgICAgICBlbnVtOg0KPiA+ICsgICAgICAgICAg ICAgICAgLSBTUElfRkxBU0hfNEJJVDENCj4gPiArICAgICAgICAgICAgICAgIC0gU1BJX0ZMQVNI XzRCSVQyDQo+ID4gKyAgICAgIC0gaWY6DQo+ID4gKyAgICAgICAgICBwcm9wZXJ0aWVzOg0KPiA+ ICsgICAgICAgICAgICBmdW5jdGlvbjoNCj4gPiArICAgICAgICAgICAgICBlbnVtOg0KPiA+ICsg ICAgICAgICAgICAgICAgLSBTUElfTkFORA0KPiA+ICsgICAgICAgIHRoZW46DQo+ID4gKyAgICAg ICAgICBwcm9wZXJ0aWVzOg0KPiA+ICsgICAgICAgICAgICBncm91cHM6DQo+ID4gKyAgICAgICAg ICAgICAgZW51bToNCj4gPiArICAgICAgICAgICAgICAgIC0gU1BJX05BTkQNCj4gPiArICAgICAg LSBpZjoNCj4gPiArICAgICAgICAgIHByb3BlcnRpZXM6DQo+ID4gKyAgICAgICAgICAgIGZ1bmN0 aW9uOg0KPiA+ICsgICAgICAgICAgICAgIGVudW06DQo+ID4gKyAgICAgICAgICAgICAgICAtIENB UkQwX0VNTUMNCj4gPiArICAgICAgICB0aGVuOg0KPiA+ICsgICAgICAgICAgcHJvcGVydGllczoN Cj4gPiArICAgICAgICAgICAgZ3JvdXBzOg0KPiA+ICsgICAgICAgICAgICAgIGVudW06DQo+ID4g KyAgICAgICAgICAgICAgICAtIENBUkQwX0VNTUMNCj4gPiArICAgICAgLSBpZjoNCj4gPiArICAg ICAgICAgIHByb3BlcnRpZXM6DQo+ID4gKyAgICAgICAgICAgIGZ1bmN0aW9uOg0KPiA+ICsgICAg ICAgICAgICAgIGVudW06DQo+ID4gKyAgICAgICAgICAgICAgICAtIFNEX0NBUkQNCj4gPiArICAg ICAgICB0aGVuOg0KPiA+ICsgICAgICAgICAgcHJvcGVydGllczoNCj4gPiArICAgICAgICAgICAg Z3JvdXBzOg0KPiA+ICsgICAgICAgICAgICAgIGVudW06DQo+ID4gKyAgICAgICAgICAgICAgICAt IFNEX0NBUkQNCj4gPiArICAgICAgLSBpZjoNCj4gPiArICAgICAgICAgIHByb3BlcnRpZXM6DQo+ ID4gKyAgICAgICAgICAgIGZ1bmN0aW9uOg0KPiA+ICsgICAgICAgICAgICAgIGVudW06DQo+ID4g KyAgICAgICAgICAgICAgICAtIFVBMA0KPiA+ICsgICAgICAgIHRoZW46DQo+ID4gKyAgICAgICAg ICBwcm9wZXJ0aWVzOg0KPiA+ICsgICAgICAgICAgICBncm91cHM6DQo+ID4gKyAgICAgICAgICAg ICAgZW51bToNCj4gPiArICAgICAgICAgICAgICAgIC0gVUEwDQo+ID4gKyAgICAgIC0gaWY6DQo+ ID4gKyAgICAgICAgICBwcm9wZXJ0aWVzOg0KPiA+ICsgICAgICAgICAgICBmdW5jdGlvbjoNCj4g PiArICAgICAgICAgICAgICBlbnVtOg0KPiA+ICsgICAgICAgICAgICAgICAgLSBGUEdBX0lGWA0K PiA+ICsgICAgICAgIHRoZW46DQo+ID4gKyAgICAgICAgICBwcm9wZXJ0aWVzOg0KPiA+ICsgICAg ICAgICAgICBncm91cHM6DQo+ID4gKyAgICAgICAgICAgICAgZW51bToNCj4gPiArICAgICAgICAg ICAgICAgIC0gRlBHQV9JRlgNCj4gPiArICAgICAgLSBpZjoNCj4gPiArICAgICAgICAgIHByb3Bl cnRpZXM6DQo+ID4gKyAgICAgICAgICAgIGZ1bmN0aW9uOg0KPiA+ICsgICAgICAgICAgICAgIGVu dW06DQo+ID4gKyAgICAgICAgICAgICAgICAtIEhETUlfVFgNCj4gPiArICAgICAgICB0aGVuOg0K PiA+ICsgICAgICAgICAgcHJvcGVydGllczoNCj4gPiArICAgICAgICAgICAgZ3JvdXBzOg0KPiA+ ICsgICAgICAgICAgICAgIGVudW06DQo+ID4gKyAgICAgICAgICAgICAgICAtIEhETUlfVFgxDQo+ ID4gKyAgICAgICAgICAgICAgICAtIEhETUlfVFgyDQo+ID4gKyAgICAgICAgICAgICAgICAtIEhE TUlfVFgzDQo+ID4gKyAgICAgIC0gaWY6DQo+ID4gKyAgICAgICAgICBwcm9wZXJ0aWVzOg0KPiA+ ICsgICAgICAgICAgICBmdW5jdGlvbjoNCj4gPiArICAgICAgICAgICAgICBlbnVtOg0KPiA+ICsg ICAgICAgICAgICAgICAgLSBMQ0RJRg0KPiA+ICsgICAgICAgIHRoZW46DQo+ID4gKyAgICAgICAg ICBwcm9wZXJ0aWVzOg0KPiA+ICsgICAgICAgICAgICBncm91cHM6DQo+ID4gKyAgICAgICAgICAg ICAgZW51bToNCj4gPiArICAgICAgICAgICAgICAgIC0gTENESUYNCj4gPiArICAgICAgLSBpZjoN Cj4gPiArICAgICAgICAgIHByb3BlcnRpZXM6DQo+ID4gKyAgICAgICAgICAgIGZ1bmN0aW9uOg0K PiA+ICsgICAgICAgICAgICAgIGVudW06DQo+ID4gKyAgICAgICAgICAgICAgICAtIFVTQjBfT1RH DQo+ID4gKyAgICAgICAgdGhlbjoNCj4gPiArICAgICAgICAgIHByb3BlcnRpZXM6DQo+ID4gKyAg ICAgICAgICAgIGdyb3VwczoNCj4gPiArICAgICAgICAgICAgICBlbnVtOg0KPiA+ICsgICAgICAg ICAgICAgICAgLSBVU0IwX09URw0KPiA+ICsgICAgICAtIGlmOg0KPiA+ICsgICAgICAgICAgcHJv cGVydGllczoNCj4gPiArICAgICAgICAgICAgZnVuY3Rpb246DQo+ID4gKyAgICAgICAgICAgICAg ZW51bToNCj4gPiArICAgICAgICAgICAgICAgIC0gVVNCMV9PVEcNCj4gPiArICAgICAgICB0aGVu Og0KPiA+ICsgICAgICAgICAgcHJvcGVydGllczoNCj4gPiArICAgICAgICAgICAgZ3JvdXBzOg0K PiA+ICsgICAgICAgICAgICAgIGVudW06DQo+ID4gKyAgICAgICAgICAgICAgICAtIFVTQjFfT1RH DQo+ID4gKw0KPiA+ICtyZXF1aXJlZDoNCj4gPiArICAtIGNvbXBhdGlibGUNCj4gPiArICAtIHJl Zw0KPiA+ICsgIC0gcmVnLW5hbWVzDQo+ID4gKyAgLSAiI2dwaW8tY2VsbHMiDQo+ID4gKyAgLSBn cGlvLWNvbnRyb2xsZXINCj4gPiArICAtIGNsb2Nrcw0KPiA+ICsgIC0gcmVzZXRzDQo+ID4gKw0K PiA+ICthZGRpdGlvbmFsUHJvcGVydGllczogZmFsc2UNCj4gPiArDQo+ID4gK2V4YW1wbGVzOg0K PiA+ICsgIC0gfA0KPiA+ICsgICAgI2luY2x1ZGUgPGR0LWJpbmRpbmdzL3BpbmN0cmwvc3BwY3Rs LXNwNzAyMS5oPg0KPiA+ICsNCj4gPiArICAgIHBpbmN0bEA5YzAwMDEwMCB7DQo+ID4gKyAgICAg ICAgY29tcGF0aWJsZSA9ICJzdW5wbHVzLHNwNzAyMS1wY3RsIjsNCj4gPiArICAgICAgICByZWcg PSA8MHg5YzAwMDEwMCAweDEwMD4sIDwweDljMDAwMzAwIDB4MTAwPiwNCj4gPiArICAgICAgICAg ICAgICA8MHg5YzAwMzJlNCAweDFjPiwgPDB4OWMwMDAwODAgMHgyMD47DQo+ID4gKyAgICAgICAg cmVnLW5hbWVzID0gIm1vb24yIiwgImdwaW94dCIsICJmaXJzdCIsICJtb29uMSI7DQo+ID4gKyAg ICAgICAgZ3Bpby1jb250cm9sbGVyOw0KPiA+ICsgICAgICAgICNncGlvLWNlbGxzID0gPDI+Ow0K PiA+ICsgICAgICAgIGNsb2NrcyA9IDwmY2xrYyAweDgzPjsNCj4gPiArICAgICAgICByZXNldHMg PSA8JnJzdGMgMHg3Mz47DQo+ID4gKw0KPiA+ICsgICAgICAgIHVhcnQwLXBpbnMgew0KPiA+ICsg ICAgICAgICAgICBmdW5jdGlvbiA9ICJVQTAiOw0KPiA+ICsgICAgICAgICAgICBncm91cHMgPSAi VUEwIjsNCj4gPiArICAgICAgICB9Ow0KPiA+ICsNCj4gPiArICAgICAgICBzcGluYW5kMC1waW5z IHsNCj4gPiArICAgICAgICAgICAgZnVuY3Rpb24gPSAiU1BJX05BTkQiOw0KPiA+ICsgICAgICAg ICAgICBncm91cHMgPSAiU1BJX05BTkQiOw0KPiA+ICsgICAgICAgIH07DQo+ID4gKw0KPiA+ICsg ICAgICAgIHVhcnQxLXBpbnMgew0KPiA+ICsgICAgICAgICAgICBzdW5wbHVzLHBpbnMgPSA8DQo+ ID4gKyAgICAgICAgICAgICAgICBTUFBDVExfSU9QQUQoMTEsIFNQUENUTF9QQ1RMX0dfUE1VWCwg TVVYRl9VQTFfVFgsIDApDQo+ID4gKyAgICAgICAgICAgICAgICBTUFBDVExfSU9QQUQoMTAsIFNQ UENUTF9QQ1RMX0dfUE1VWCwgTVVYRl9VQTFfUlgsIDApDQo+ID4gKyAgICAgICAgICAgID47DQo+ ID4gKyAgICAgICAgfTsNCj4gPiArDQo+ID4gKyAgICAgICAgdWFydDItcGlucyB7DQo+ID4gKyAg ICAgICAgICAgIHN1bnBsdXMscGlucyA9IDwNCj4gPiArICAgICAgICAgICAgICAgIFNQUENUTF9J T1BBRCgyMCwgU1BQQ1RMX1BDVExfR19QTVVYLCBNVVhGX1VBMV9UWCwgMCkNCj4gPiArICAgICAg ICAgICAgICAgIFNQUENUTF9JT1BBRCgyMSwgU1BQQ1RMX1BDVExfR19QTVVYLCBNVVhGX1VBMV9S WCwgMCkNCj4gPiArICAgICAgICAgICAgICAgIFNQUENUTF9JT1BBRCgyMiwgU1BQQ1RMX1BDVExf R19QTVVYLCBNVVhGX1VBMV9SVFMsIDApDQo+ID4gKyAgICAgICAgICAgICAgICBTUFBDVExfSU9Q QUQoMjMsIFNQUENUTF9QQ1RMX0dfUE1VWCwgTVVYRl9VQTFfQ1RTLCAwKQ0KPiA+ICsgICAgICAg ICAgICA+Ow0KPiA+ICsgICAgICAgIH07DQo+ID4gKw0KPiA+ICsgICAgICAgIGVtbWMtcGlucyB7 DQo+ID4gKyAgICAgICAgICAgIGZ1bmN0aW9uID0gIkNBUkQwX0VNTUMiOw0KPiA+ICsgICAgICAg ICAgICBncm91cHMgPSAiQ0FSRDBfRU1NQyI7DQo+ID4gKyAgICAgICAgfTsNCj4gPiArDQo+ID4g KyAgICAgICAgc2RjYXJkLXBpbnMgew0KPiA+ICsgICAgICAgICAgICBmdW5jdGlvbiA9ICJTRF9D QVJEIjsNCj4gPiArICAgICAgICAgICAgZ3JvdXBzID0gIlNEX0NBUkQiOw0KPiA+ICsgICAgICAg ICAgICBzdW5wbHVzLHBpbnMgPSA8IFNQUENUTF9JT1BBRCg5MSwgU1BQQ1RMX1BDVExfR19HUElP LCAwLCAwKSA+Ow0KPiA+ICsgICAgICAgIH07DQo+ID4gKw0KPiA+ICsgICAgICAgIGhkbWlfQV90 eDEtcGlucyB7DQo+ID4gKyAgICAgICAgICAgIGZ1bmN0aW9uID0gIkhETUlfVFgiOw0KPiA+ICsg ICAgICAgICAgICBncm91cHMgPSAiSERNSV9UWDEiOw0KPiA+ICsgICAgICAgIH07DQo+ID4gKyAg ICAgICAgaGRtaV9BX3R4Mi1waW5zIHsNCj4gPiArICAgICAgICAgICAgZnVuY3Rpb24gPSAiSERN SV9UWCI7DQo+ID4gKyAgICAgICAgICAgIGdyb3VwcyA9ICJIRE1JX1RYMiI7DQo+ID4gKyAgICAg ICAgfTsNCj4gPiArICAgICAgICBoZG1pX0FfdHgzLXBpbnMgew0KPiA+ICsgICAgICAgICAgICBm dW5jdGlvbiA9ICJIRE1JX1RYIjsNCj4gPiArICAgICAgICAgICAgZ3JvdXBzID0gIkhETUlfVFgz IjsNCj4gPiArICAgICAgICB9Ow0KPiA+ICsNCj4gPiArICAgICAgICBldGhlcm5ldC1waW5zIHsN Cj4gPiArICAgICAgICAgICAgc3VucGx1cyxwaW5zID0gPA0KPiA+ICsgICAgICAgICAgICAgICAg U1BQQ1RMX0lPUEFEKDQ5LFNQUENUTF9QQ1RMX0dfUE1VWCxNVVhGX0wyU1dfQ0xLX09VVCwwKQ0K PiA+ICsgICAgICAgICAgICAgICAgU1BQQ1RMX0lPUEFEKDQ0LFNQUENUTF9QQ1RMX0dfUE1VWCxN VVhGX0wyU1dfTUFDX1NNSV9NREMsMCkNCj4gPiArICAgICAgICAgICAgICAgIFNQUENUTF9JT1BB RCg0MyxTUFBDVExfUENUTF9HX1BNVVgsTVVYRl9MMlNXX01BQ19TTUlfTURJTywwKQ0KPiA+ICsg ICAgICAgICAgICAgICAgU1BQQ1RMX0lPUEFEKDUyLFNQUENUTF9QQ1RMX0dfUE1VWCxNVVhGX0wy U1dfUDBfTUFDX1JNSUlfVFhFTiwwKQ0KPiA+ICsgICAgICAgICAgICAgICAgU1BQQ1RMX0lPUEFE KDUwLFNQUENUTF9QQ1RMX0dfUE1VWCxNVVhGX0wyU1dfUDBfTUFDX1JNSUlfVFhEMCwwKQ0KPiA+ ICsgICAgICAgICAgICAgICAgU1BQQ1RMX0lPUEFEKDUxLFNQUENUTF9QQ1RMX0dfUE1VWCxNVVhG X0wyU1dfUDBfTUFDX1JNSUlfVFhEMSwwKQ0KPiA+ICsgICAgICAgICAgICAgICAgU1BQQ1RMX0lP UEFEKDQ2LFNQUENUTF9QQ1RMX0dfUE1VWCxNVVhGX0wyU1dfUDBfTUFDX1JNSUlfQ1JTRFYsMCkN Cj4gPiArICAgICAgICAgICAgICAgIFNQUENUTF9JT1BBRCg0NyxTUFBDVExfUENUTF9HX1BNVVgs TVVYRl9MMlNXX1AwX01BQ19STUlJX1JYRDAsMCkNCj4gPiArICAgICAgICAgICAgICAgIFNQUENU TF9JT1BBRCg0OCxTUFBDVExfUENUTF9HX1BNVVgsTVVYRl9MMlNXX1AwX01BQ19STUlJX1JYRDEs MCkNCj4gPiArICAgICAgICAgICAgPjsNCj4gPiArICAgICAgICAgICAgc3VucGx1cyx6ZXJvX2Z1 bmMgPSA8DQo+ID4gKyAgICAgICAgICAgICAgICBNVVhGX0wyU1dfTEVEX0ZMQVNIMA0KPiA+ICsg ICAgICAgICAgICAgICAgTVVYRl9MMlNXX0xFRF9PTjANCj4gPiArICAgICAgICAgICAgICAgIE1V WEZfTDJTV19QMF9NQUNfUk1JSV9SWEVSDQo+ID4gKyAgICAgICAgICAgID47DQo+ID4gKyAgICAg ICAgfTsNCj4gPiArICAgIH07DQo+ID4gKy4uLg0KPiA+IGRpZmYgLS1naXQgYS9NQUlOVEFJTkVS UyBiL01BSU5UQUlORVJTIGluZGV4IDg5MTJiMmMuLjZiMWNmYzIgMTAwNjQ0DQo+ID4gLS0tIGEv TUFJTlRBSU5FUlMNCj4gPiArKysgYi9NQUlOVEFJTkVSUw0KPiA+IEBAIC0xNTEyNyw2ICsxNTEy NywxNSBAQCBMOglsaW51eC1vbWFwQHZnZXIua2VybmVsLm9yZw0KPiA+ICBTOglNYWludGFpbmVk DQo+ID4gIEY6CWRyaXZlcnMvcGluY3RybC9waW5jdHJsLXNpbmdsZS5jDQo+ID4NCj4gPiArUElO IENPTlRST0xMRVIgLSBTVU5QTFVTIC8gVElCQk8NCj4gPiArTToJRHZvcmtpbiBEbWl0cnkgPGR2 b3JraW5AdGliYm8uY29tPg0KPiA+ICtNOglXZWxscyBMdSA8d2VsbHNsdXR3QGdtYWlsLmNvbT4N Cj4gPiArTDoJbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnIChtb2RlcmF0ZWQg Zm9yIG5vbi1zdWJzY3JpYmVycykNCj4gPiArUzoJTWFpbnRhaW5lZA0KPiA+ICtXOglodHRwczov L3N1bnBsdXMtdGliYm8uYXRsYXNzaWFuLm5ldC93aWtpL3NwYWNlcy9kb2Mvb3ZlcnZpZXcNCj4g PiArRjoJRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL3BpbmN0cmwvc3VucGx1cywq DQo+ID4gK0Y6CWluY2x1ZGUvZHQtYmluZGluZ3MvcGluY3RybC9zcHBjdGwqDQo+ID4gKw0KPiA+ ICBQS1RDRFZEIERSSVZFUg0KPiA+ICBNOglsaW51eC1ibG9ja0B2Z2VyLmtlcm5lbC5vcmcNCj4g PiAgUzoJT3JwaGFuDQo+ID4gZGlmZiAtLWdpdCBhL2luY2x1ZGUvZHQtYmluZGluZ3MvcGluY3Ry bC9zcHBjdGwtc3A3MDIxLmgNCj4gPiBiL2luY2x1ZGUvZHQtYmluZGluZ3MvcGluY3RybC9zcHBj dGwtc3A3MDIxLmgNCj4gPiBuZXcgZmlsZSBtb2RlIDEwMDY0NA0KPiA+IGluZGV4IDAwMDAwMDAu LjgyOTljYTENCj4gPiAtLS0gL2Rldi9udWxsDQo+ID4gKysrIGIvaW5jbHVkZS9kdC1iaW5kaW5n cy9waW5jdHJsL3NwcGN0bC1zcDcwMjEuaA0KPiA+IEBAIC0wLDAgKzEsMTcxIEBADQo+ID4gKy8q IFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiAoR1BMLTIuMC1vbmx5IE9SIEJTRC0yLUNsYXVzZSkg Ki8NCj4gPiArLyogU3VucGx1cyBTUDcwMjEgZHQtYmluZGluZ3MgUGluY3RybCBoZWFkZXIgZmls ZQ0KPiA+ICsgKiBDb3B5cmlnaHQgKEMpIFN1bnBsdXMgVGVjaC9UaWJibyBUZWNoLg0KPiA+ICsg KiBBdXRob3I6IER2b3JraW4gRG1pdHJ5IDxkdm9ya2luQHRpYmJvLmNvbT4gICovDQo+ID4gKw0K PiA+ICsjaWZuZGVmCV9fRFRfQklORElOR1NfUElOQ1RSTF9TUFBDVExfU1A3MDIxX0hfXw0KPiA+ ICsjZGVmaW5lCV9fRFRfQklORElOR1NfUElOQ1RSTF9TUFBDVExfU1A3MDIxX0hfXw0KPiA+ICsN Cj4gPiArI2luY2x1ZGUgPGR0LWJpbmRpbmdzL3BpbmN0cmwvc3BwY3RsLmg+DQo+ID4gKw0KPiA+ ICsvKiBQbGVhc2UgZG9uJ3QgY2hhbmdlIHRoZSBvcmRlciBvZiB0aGUNCj4gPiArICogZm9sbG93 aW5nIGRlZmluZXMuIFRoZXkgYXJlIGJhc2VkIG9uDQo+ID4gKyAqIG9yZGVyIG9mIGNvbnRyb2wg cmVnaXN0ZXIgZGVmaW5lIG9mDQo+ID4gKyAqIE1PT04xIH4gTU9PTjQgcmVnaXN0ZXJzLg0KPiA+ ICsgKi8NCj4gPiArI2RlZmluZSBNVVhGX0wyU1dfQ0xLX09VVAkJMA0KPiA+ICsjZGVmaW5lIE1V WEZfTDJTV19NQUNfU01JX01EQwkJMQ0KPiA+ICsjZGVmaW5lIE1VWEZfTDJTV19MRURfRkxBU0gw CQkyDQo+ID4gKyNkZWZpbmUgTVVYRl9MMlNXX0xFRF9GTEFTSDEJCTMNCj4gPiArI2RlZmluZSBN VVhGX0wyU1dfTEVEX09OMAkJNA0KPiA+ICsjZGVmaW5lIE1VWEZfTDJTV19MRURfT04xCQk1DQo+ ID4gKyNkZWZpbmUgTVVYRl9MMlNXX01BQ19TTUlfTURJTwkJNg0KPiA+ICsjZGVmaW5lIE1VWEZf TDJTV19QMF9NQUNfUk1JSV9UWEVOCTcNCj4gPiArI2RlZmluZSBNVVhGX0wyU1dfUDBfTUFDX1JN SUlfVFhEMAk4DQo+ID4gKyNkZWZpbmUgTVVYRl9MMlNXX1AwX01BQ19STUlJX1RYRDEJOQ0KPiA+ ICsjZGVmaW5lIE1VWEZfTDJTV19QMF9NQUNfUk1JSV9DUlNEVgkxMA0KPiA+ICsjZGVmaW5lIE1V WEZfTDJTV19QMF9NQUNfUk1JSV9SWEQwCTExDQo+ID4gKyNkZWZpbmUgTVVYRl9MMlNXX1AwX01B Q19STUlJX1JYRDEJMTINCj4gPiArI2RlZmluZSBNVVhGX0wyU1dfUDBfTUFDX1JNSUlfUlhFUgkx Mw0KPiA+ICsjZGVmaW5lIE1VWEZfTDJTV19QMV9NQUNfUk1JSV9UWEVOCTE0DQo+ID4gKyNkZWZp bmUgTVVYRl9MMlNXX1AxX01BQ19STUlJX1RYRDAJMTUNCj4gPiArI2RlZmluZSBNVVhGX0wyU1df UDFfTUFDX1JNSUlfVFhEMQkxNg0KPiA+ICsjZGVmaW5lIE1VWEZfTDJTV19QMV9NQUNfUk1JSV9D UlNEVgkxNw0KPiA+ICsjZGVmaW5lIE1VWEZfTDJTV19QMV9NQUNfUk1JSV9SWEQwCTE4DQo+ID4g KyNkZWZpbmUgTVVYRl9MMlNXX1AxX01BQ19STUlJX1JYRDEJMTkNCj4gPiArI2RlZmluZSBNVVhG X0wyU1dfUDFfTUFDX1JNSUlfUlhFUgkyMA0KPiA+ICsjZGVmaW5lIE1VWEZfREFJU1lfTU9ERQkJ CTIxDQo+ID4gKyNkZWZpbmUgTVVYRl9TRElPX0NMSwkJCTIyDQo+ID4gKyNkZWZpbmUgTVVYRl9T RElPX0NNRAkJCTIzDQo+ID4gKyNkZWZpbmUgTVVYRl9TRElPX0QwCQkJMjQNCj4gPiArI2RlZmlu ZSBNVVhGX1NESU9fRDEJCQkyNQ0KPiA+ICsjZGVmaW5lIE1VWEZfU0RJT19EMgkJCTI2DQo+ID4g KyNkZWZpbmUgTVVYRl9TRElPX0QzCQkJMjcNCj4gPiArI2RlZmluZSBNVVhGX1BXTTAJCQkyOA0K PiA+ICsjZGVmaW5lIE1VWEZfUFdNMQkJCTI5DQo+ID4gKyNkZWZpbmUgTVVYRl9QV00yCQkJMzAN Cj4gPiArI2RlZmluZSBNVVhGX1BXTTMJCQkzMQ0KPiA+ICsjZGVmaW5lIE1VWEZfUFdNNAkJCTMy DQo+ID4gKyNkZWZpbmUgTVVYRl9QV001CQkJMzMNCj4gPiArI2RlZmluZSBNVVhGX1BXTTYJCQkz NA0KPiA+ICsjZGVmaW5lIE1VWEZfUFdNNwkJCTM1DQo+ID4gKyNkZWZpbmUgTVVYRl9JQ00wX0QJ CQkzNg0KPiA+ICsjZGVmaW5lIE1VWEZfSUNNMV9ECQkJMzcNCj4gPiArI2RlZmluZSBNVVhGX0lD TTJfRAkJCTM4DQo+ID4gKyNkZWZpbmUgTVVYRl9JQ00zX0QJCQkzOQ0KPiA+ICsjZGVmaW5lIE1V WEZfSUNNMF9DTEsJCQk0MA0KPiA+ICsjZGVmaW5lIE1VWEZfSUNNMV9DTEsJCQk0MQ0KPiA+ICsj ZGVmaW5lIE1VWEZfSUNNMl9DTEsJCQk0Mg0KPiA+ICsjZGVmaW5lIE1VWEZfSUNNM19DTEsJCQk0 Mw0KPiA+ICsjZGVmaW5lIE1VWEZfU1BJTTBfSU5UCQkJNDQNCj4gPiArI2RlZmluZSBNVVhGX1NQ SU0wX0NMSwkJCTQ1DQo+ID4gKyNkZWZpbmUgTVVYRl9TUElNMF9FTgkJCTQ2DQo+ID4gKyNkZWZp bmUgTVVYRl9TUElNMF9ETwkJCTQ3DQo+ID4gKyNkZWZpbmUgTVVYRl9TUElNMF9ESQkJCTQ4DQo+ ID4gKyNkZWZpbmUgTVVYRl9TUElNMV9JTlQJCQk0OQ0KPiA+ICsjZGVmaW5lIE1VWEZfU1BJTTFf Q0xLCQkJNTANCj4gPiArI2RlZmluZSBNVVhGX1NQSU0xX0VOCQkJNTENCj4gPiArI2RlZmluZSBN VVhGX1NQSU0xX0RPCQkJNTINCj4gPiArI2RlZmluZSBNVVhGX1NQSU0xX0RJCQkJNTMNCj4gPiAr I2RlZmluZSBNVVhGX1NQSU0yX0lOVAkJCTU0DQo+ID4gKyNkZWZpbmUgTVVYRl9TUElNMl9DTEsJ CQk1NQ0KPiA+ICsjZGVmaW5lIE1VWEZfU1BJTTJfRU4JCQk1Ng0KPiA+ICsjZGVmaW5lIE1VWEZf U1BJTTJfRE8JCQk1Nw0KPiA+ICsjZGVmaW5lIE1VWEZfU1BJTTJfREkJCQk1OA0KPiA+ICsjZGVm aW5lIE1VWEZfU1BJTTNfSU5UCQkJNTkNCj4gPiArI2RlZmluZSBNVVhGX1NQSU0zX0NMSwkJCTYw DQo+ID4gKyNkZWZpbmUgTVVYRl9TUElNM19FTgkJCTYxDQo+ID4gKyNkZWZpbmUgTVVYRl9TUElN M19ETwkJCTYyDQo+ID4gKyNkZWZpbmUgTVVYRl9TUElNM19ESQkJCTYzDQo+ID4gKyNkZWZpbmUg TVVYRl9TUEkwU19JTlQJCQk2NA0KPiA+ICsjZGVmaW5lIE1VWEZfU1BJMFNfQ0xLCQkJNjUNCj4g PiArI2RlZmluZSBNVVhGX1NQSTBTX0VOCQkJNjYNCj4gPiArI2RlZmluZSBNVVhGX1NQSTBTX0RP CQkJNjcNCj4gPiArI2RlZmluZSBNVVhGX1NQSTBTX0RJCQkJNjgNCj4gPiArI2RlZmluZSBNVVhG X1NQSTFTX0lOVAkJCTY5DQo+ID4gKyNkZWZpbmUgTVVYRl9TUEkxU19DTEsJCQk3MA0KPiA+ICsj ZGVmaW5lIE1VWEZfU1BJMVNfRU4JCQk3MQ0KPiA+ICsjZGVmaW5lIE1VWEZfU1BJMVNfRE8JCQk3 Mg0KPiA+ICsjZGVmaW5lIE1VWEZfU1BJMVNfREkJCQk3Mw0KPiA+ICsjZGVmaW5lIE1VWEZfU1BJ MlNfSU5UCQkJNzQNCj4gPiArI2RlZmluZSBNVVhGX1NQSTJTX0NMSwkJCTc1DQo+ID4gKyNkZWZp bmUgTVVYRl9TUEkyU19FTgkJCTc2DQo+ID4gKyNkZWZpbmUgTVVYRl9TUEkyU19ETwkJCTc3DQo+ ID4gKyNkZWZpbmUgTVVYRl9TUEkyU19ESQkJCTc4DQo+ID4gKyNkZWZpbmUgTVVYRl9TUEkzU19J TlQJCQk3OQ0KPiA+ICsjZGVmaW5lIE1VWEZfU1BJM1NfQ0xLCQkJODANCj4gPiArI2RlZmluZSBN VVhGX1NQSTNTX0VOCQkJODENCj4gPiArI2RlZmluZSBNVVhGX1NQSTNTX0RPCQkJODINCj4gPiAr I2RlZmluZSBNVVhGX1NQSTNTX0RJCQkJODMNCj4gPiArI2RlZmluZSBNVVhGX0kyQ00wX0NMSwkJ CTg0DQo+ID4gKyNkZWZpbmUgTVVYRl9JMkNNMF9EQVQJCQk4NQ0KPiA+ICsjZGVmaW5lIE1VWEZf STJDTTFfQ0xLCQkJODYNCj4gPiArI2RlZmluZSBNVVhGX0kyQ00xX0RBVAkJCTg3DQo+ID4gKyNk ZWZpbmUgTVVYRl9JMkNNMl9DTEsJCQk4OA0KPiA+ICsjZGVmaW5lIE1VWEZfSTJDTTJfREFUCQkJ ODkNCj4gPiArI2RlZmluZSBNVVhGX0kyQ00zX0NMSwkJCTkwDQo+ID4gKyNkZWZpbmUgTVVYRl9J MkNNM19EQVQJCQk5MQ0KPiA+ICsjZGVmaW5lIE1VWEZfVUExX1RYCQkJOTINCj4gPiArI2RlZmlu ZSBNVVhGX1VBMV9SWAkJCTkzDQo+ID4gKyNkZWZpbmUgTVVYRl9VQTFfQ1RTCQkJOTQNCj4gPiAr I2RlZmluZSBNVVhGX1VBMV9SVFMJCQk5NQ0KPiA+ICsjZGVmaW5lIE1VWEZfVUEyX1RYCQkJOTYN Cj4gPiArI2RlZmluZSBNVVhGX1VBMl9SWAkJCTk3DQo+ID4gKyNkZWZpbmUgTVVYRl9VQTJfQ1RT CQkJOTgNCj4gPiArI2RlZmluZSBNVVhGX1VBMl9SVFMJCQk5OQ0KPiA+ICsjZGVmaW5lIE1VWEZf VUEzX1RYCQkJMTAwDQo+ID4gKyNkZWZpbmUgTVVYRl9VQTNfUlgJCQkxMDENCj4gPiArI2RlZmlu ZSBNVVhGX1VBM19DVFMJCQkxMDINCj4gPiArI2RlZmluZSBNVVhGX1VBM19SVFMJCQkxMDMNCj4g PiArI2RlZmluZSBNVVhGX1VBNF9UWAkJCTEwNA0KPiA+ICsjZGVmaW5lIE1VWEZfVUE0X1JYCQkJ MTA1DQo+ID4gKyNkZWZpbmUgTVVYRl9VQTRfQ1RTCQkJMTA2DQo+ID4gKyNkZWZpbmUgTVVYRl9V QTRfUlRTCQkJMTA3DQo+ID4gKyNkZWZpbmUgTVVYRl9USU1FUjBfSU5UCQkJMTA4DQo+ID4gKyNk ZWZpbmUgTVVYRl9USU1FUjFfSU5UCQkJMTA5DQo+ID4gKyNkZWZpbmUgTVVYRl9USU1FUjJfSU5U CQkJMTEwDQo+ID4gKyNkZWZpbmUgTVVYRl9USU1FUjNfSU5UCQkJMTExDQo+ID4gKyNkZWZpbmUg TVVYRl9HUElPX0lOVDAJCQkxMTINCj4gPiArI2RlZmluZSBNVVhGX0dQSU9fSU5UMQkJCTExMw0K PiA+ICsjZGVmaW5lIE1VWEZfR1BJT19JTlQyCQkJMTE0DQo+ID4gKyNkZWZpbmUgTVVYRl9HUElP X0lOVDMJCQkxMTUNCj4gPiArI2RlZmluZSBNVVhGX0dQSU9fSU5UNAkJCTExNg0KPiA+ICsjZGVm aW5lIE1VWEZfR1BJT19JTlQ1CQkJMTE3DQo+ID4gKyNkZWZpbmUgTVVYRl9HUElPX0lOVDYJCQkx MTgNCj4gPiArI2RlZmluZSBNVVhGX0dQSU9fSU5UNwkJCTExOQ0KPiA+ICsNCj4gPiArI2RlZmlu ZSBHUk9QX1NQSV9GTEFTSAkJCTEyMA0KPiA+ICsjZGVmaW5lIEdST1BfU1BJX0ZMQVNIXzRCSVQJ CTEyMQ0KPiA+ICsjZGVmaW5lIEdST1BfU1BJX05BTkQJCQkxMjINCj4gPiArI2RlZmluZSBHUk9Q X0NBUkQwX0VNTUMJCQkxMjMNCj4gPiArI2RlZmluZSBHUk9QX1NEX0NBUkQJCQkxMjQNCj4gPiAr I2RlZmluZSBHUk9QX1VBMAkJCTEyNQ0KPiA+ICsjZGVmaW5lIEdST1BfQUNISVBfREVCVUcJCTEy Ng0KPiA+ICsjZGVmaW5lIEdST1BfQUNISVBfVUEyQVhJCQkxMjcNCj4gPiArI2RlZmluZSBHUk9Q X0ZQR0FfSUZYCQkJMTI4DQo+ID4gKyNkZWZpbmUgR1JPUF9IRE1JX1RYCQkJMTI5DQo+ID4gKyNk ZWZpbmUgR1JPUF9BVURfRVhUX0FEQ19JRlgwCQkxMzANCj4gPiArI2RlZmluZSBHUk9QX0FVRF9F WFRfREFDX0lGWDAJCTEzMQ0KPiA+ICsjZGVmaW5lIEdST1BfU1BESUZfUlgJCQkxMzINCj4gPiAr I2RlZmluZSBHUk9QX1NQRElGX1RYCQkJMTMzDQo+ID4gKyNkZWZpbmUgR1JPUF9URE1UWF9JRlgw CQkJMTM0DQo+ID4gKyNkZWZpbmUgR1JPUF9URE1SWF9JRlgwCQkJMTM1DQo+ID4gKyNkZWZpbmUg R1JPUF9QRE1SWF9JRlgwCQkJMTM2DQo+ID4gKyNkZWZpbmUgR1JPUF9QQ01fSUVDX1RYCQkJMTM3 DQo+ID4gKyNkZWZpbmUgR1JPUF9MQ0RJRgkJCTEzOA0KPiA+ICsjZGVmaW5lIEdST1BfRFZEX0RT UF9ERUJVRwkJMTM5DQo+ID4gKyNkZWZpbmUgR1JPUF9JMkNfREVCVUcJCQkxNDANCj4gPiArI2Rl ZmluZSBHUk9QX0kyQ19TTEFWRQkJCTE0MQ0KPiA+ICsjZGVmaW5lIEdST1BfV0FLRVVQCQkJMTQy DQo+ID4gKyNkZWZpbmUgR1JPUF9VQVJUMkFYSQkJCTE0Mw0KPiA+ICsjZGVmaW5lIEdST1BfVVNC MF9JMkMJCQkxNDQNCj4gPiArI2RlZmluZSBHUk9QX1VTQjFfSTJDCQkJMTQ1DQo+ID4gKyNkZWZp bmUgR1JPUF9VU0IwX09URwkJCTE0Ng0KPiA+ICsjZGVmaW5lIEdST1BfVVNCMV9PVEcJCQkxNDcN Cj4gPiArI2RlZmluZSBHUk9QX1VQSFkwX0RFQlVHCQkxNDgNCj4gPiArI2RlZmluZSBHUk9QX1VQ SFkxX0RFQlVHCQkxNDkNCj4gPiArI2RlZmluZSBHUk9QX1VQSFkwX0VYVAkJCTE1MA0KPiA+ICsj ZGVmaW5lIEdST1BfUFJPQkVfUE9SVAkJCTE1MQ0KPiA+ICsNCj4gPiArI2VuZGlmDQo+ID4gZGlm ZiAtLWdpdCBhL2luY2x1ZGUvZHQtYmluZGluZ3MvcGluY3RybC9zcHBjdGwuaA0KPiA+IGIvaW5j bHVkZS9kdC1iaW5kaW5ncy9waW5jdHJsL3NwcGN0bC5oDQo+ID4gbmV3IGZpbGUgbW9kZSAxMDA2 NDQNCj4gPiBpbmRleCAwMDAwMDAwLi44YmY1NDU3DQo+ID4gLS0tIC9kZXYvbnVsbA0KPiA+ICsr KyBiL2luY2x1ZGUvZHQtYmluZGluZ3MvcGluY3RybC9zcHBjdGwuaA0KPiA+IEBAIC0wLDAgKzEs MzAgQEANCj4gPiArLyogU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IChHUEwtMi4wLW9ubHkgT1Ig QlNELTItQ2xhdXNlKSAqLw0KPiA+ICsvKiBTdW5wbHVzIGR0LWJpbmRpbmdzIFBpbmN0cmwgaGVh ZGVyIGZpbGUNCj4gPiArICogQ29weXJpZ2h0IChDKSBTdW5wbHVzIFRlY2ggLyBUaWJibyBUZWNo Lg0KPiA+ICsgKiBBdXRob3I6IER2b3JraW4gRG1pdHJ5IDxkdm9ya2luQHRpYmJvLmNvbT4gICov DQo+ID4gKw0KPiA+ICsjaWZuZGVmIF9fRFRfQklORElOR1NfUElOQ1RSTF9TUFBDVExfSF9fICNk ZWZpbmUNCj4gPiArX19EVF9CSU5ESU5HU19QSU5DVFJMX1NQUENUTF9IX18NCj4gPiArDQo+ID4g KyNkZWZpbmUgSU9QX0dfTUFTVEUJCSgweDAxIDw8IDApDQo+ID4gKyNkZWZpbmUgSU9QX0dfRklS U1QJCSgweDAxIDw8IDEpDQo+ID4gKw0KPiA+ICsjZGVmaW5lIFNQUENUTF9QQ1RMX0dfUE1VWAko MHgwMCAgICAgICAgfCBJT1BfR19NQVNURSkNCj4gPiArI2RlZmluZSBTUFBDVExfUENUTF9HX0dQ SU8JKElPUF9HX0ZJUlNUIHwgSU9QX0dfTUFTVEUpDQo+ID4gKyNkZWZpbmUgU1BQQ1RMX1BDVExf R19JT1BQCShJT1BfR19GSVJTVCB8IDB4MDApDQo+ID4gKw0KPiA+ICsjZGVmaW5lIFNQUENUTF9Q Q1RMX0xfT1VUCSgweDAxIDw8IDApCS8qIE91dHB1dCBMT1cgICAgICAgICovDQo+ID4gKyNkZWZp bmUgU1BQQ1RMX1BDVExfTF9PVTEJKDB4MDEgPDwgMSkJLyogT3V0cHV0IEhJR0ggICAgICAgKi8N Cj4gPiArI2RlZmluZSBTUFBDVExfUENUTF9MX0lOVgkoMHgwMSA8PCAyKQkvKiBJbnB1dCBJbnZl cnQgICAgICAqLw0KPiA+ICsjZGVmaW5lIFNQUENUTF9QQ1RMX0xfT05WCSgweDAxIDw8IDMpCS8q IE91dHB1dCBJbnZlcnQgICAgICovDQo+ID4gKyNkZWZpbmUgU1BQQ1RMX1BDVExfTF9PRFIJKDB4 MDEgPDwgNCkJLyogT3V0cHV0IE9wZW4gRHJhaW4gKi8NCj4gPiArDQo+ID4gKy8qDQo+ID4gKyAq IHBhY2sgaW50byAzMi1iaXQgdmFsdWU6DQo+ID4gKyAqIHBpbiMoOGJpdCksIHR5cCg4Yml0KSwg ZnVuY3Rpb24oOGJpdCksIGZsYWcoOGJpdCkgICovDQo+ID4gKyNkZWZpbmUgU1BQQ1RMX0lPUEFE KHBpbiwgdHlwLCBmdW4sIGZsZykJKCgocGluKSA8PCAyNCkgfCAoKHR5cCkgPDwgMTYpIHwgXA0K PiA+ICsJCQkJCQkoKGZ1bikgPDwgOCkgfCAoZmxnKSkNCj4gPiArDQo+ID4gKyNlbmRpZg0KPiA+ IC0tDQo+ID4gMi43LjQNCj4gPg0KPiA+DQo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DD3C4C433EF for ; Mon, 27 Dec 2021 17:38:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Brvb+UEYkQyCDwluGfHtEWHS6s1NWXPFxZ1mUMDTDGE=; b=nBuMrCiowaloxC WTbjubBwKYVJPALYsdcu0oAr8VX6mgXiULWD2Ge9nbTMn7eZB59ygdXLTrWMiwA0fWVOAQHY1CJF3 Z9jshdkQl5hsLLN4jFftr+f8lZQcKGittemnfHwFOHcb99kg+l5OpF/guBvsFtKtkyhbvPsnDu9UF dspW8Fr740yKHtK58YYra/Fc286F6UOYtD4+1vwcMbESa/j8SScLADuXBiAG9SLspqWCEXnWm1R2m O0QujuPy7cEM09d1D2uXxYG6ywWfRMAidXQlYiuDSNVg9YIM9jrtg+23GqRuK5q+FGz3tfZmK0E6W XtlTu7mBkUjdSwuA++UQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n1twA-00H9LH-0V; Mon, 27 Dec 2021 17:37:30 +0000 Received: from mswedge1.sunplus.com ([60.248.182.113] helo=mg.sunplus.com) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n1tw2-00H9Ii-VY for linux-arm-kernel@lists.infradead.org; Mon, 27 Dec 2021 17:37:27 +0000 X-MailGates: (flag:3,DYNAMIC,RELAY,NOHOST:PASS)(compute_score:DELIVER,40 ,3) Received: from 172.17.9.112 by mg01.sunplus.com with MailGates ESMTP Server V5.0(4599:0:AUTH_RELAY) (envelope-from ); Tue, 28 Dec 2021 01:36:59 +0800 (CST) Received: from sphcmbx02.sunplus.com.tw (172.17.9.112) by sphcmbx02.sunplus.com.tw (172.17.9.112) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Tue, 28 Dec 2021 01:36:59 +0800 Received: from sphcmbx02.sunplus.com.tw ([fe80::fd3d:ad1a:de2a:18bd]) by sphcmbx02.sunplus.com.tw ([fe80::fd3d:ad1a:de2a:18bd%14]) with mapi id 15.00.1497.026; Tue, 28 Dec 2021 01:36:59 +0800 From: =?big5?B?V2VsbHMgTHUgp2aq2sTL?= To: Rob Herring , Wells Lu CC: "linus.walleij@linaro.org" , "linux-gpio@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "dvorkin@tibbo.com" Subject: RE: [PATCH v5 1/2] dt-bindings: pinctrl: Add dt-bindings for Sunplus SP7021 Thread-Topic: [PATCH v5 1/2] dt-bindings: pinctrl: Add dt-bindings for Sunplus SP7021 Thread-Index: AQHX+JsIGEz+1S7LlUitkhzfzPTvr6xGATGAgACWILA= Date: Mon, 27 Dec 2021 17:36:59 +0000 Message-ID: <54d148935bb84a64894872c07196e99d@sphcmbx02.sunplus.com.tw> References: <1640331779-18277-1-git-send-email-wellslutw@gmail.com> <1640331779-18277-2-git-send-email-wellslutw@gmail.com> In-Reply-To: Accept-Language: zh-TW, en-US Content-Language: zh-TW X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [172.25.108.39] MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211227_093723_512016_C09D4A99 X-CRM114-Status: GOOD ( 36.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Rob, Thanks a lot for review. Please see my replies below: > > Add dt-bindings header files and documentation for Sunplus SP7021 SoC. > > > > Signed-off-by: Wells Lu > > --- > > Changes in V5 > > - Removed "GPIOXT2" registers > > > > .../bindings/pinctrl/sunplus,sp7021-pinctrl.yaml | 373 +++++++++++++++++++++ > > MAINTAINERS | 9 + > > include/dt-bindings/pinctrl/sppctl-sp7021.h | 171 ++++++++++ > > include/dt-bindings/pinctrl/sppctl.h | 30 ++ > > 4 files changed, 583 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml > > create mode 100644 include/dt-bindings/pinctrl/sppctl-sp7021.h > > create mode 100644 include/dt-bindings/pinctrl/sppctl.h > > > > diff --git > > a/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yam > > l > > b/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yam > > l > > new file mode 100644 > > index 0000000..2672169 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl > > +++ .yaml > > @@ -0,0 +1,373 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # Copyright > > +(C) Sunplus Co., Ltd. > > +%YAML 1.2 > > +--- > > +$id: > > +http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Sunplus SP7021 Pin Controller Device Tree Bindings > > + > > +maintainers: > > + - Dvorkin Dmitry > > + - Wells Lu > > + > > +description: | > > + The Sunplus SP7021 pin controller is used to control SoC pins. > > +Please > > + refer to pinctrl-bindings.txt in this directory for details of the > > +common > > + pinctrl bindings used by client devices. > > + > > + SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to > > + 98. All are multiplexed with some special function pins. SP7021 has > > + 3 types of special function pins: > > + > > + (1) function-group pins: > > + Ex 1 (SPI-NOR flash): > > + If control-field SPI_FLASH_SEL is set to 1, GPIO 83, 84, 86 and 87 > > + will be pins of SPI-NOR flash. If it is set to 2, GPIO 76, 78, 79 > > + and 81 will be pins of SPI-NOR flash. > > + > > + Ex 2 (UART_0): > > + If control-bit UA0_SEL is set to 1, GPIO 88 and 89 will be TX and > > + RX pins of UART_0 (UART channel 0). > > + > > + Ex 3 (eMMC): > > + If control-bit EMMC_SEL is set to 1, GPIO 72, 73, 74, 75, 76, 77, > > + 78, 79, 80, 81 will be pins of an eMMC device. > > + > > + Properties "function" and "groups" are used to select function-group > > + pins. > > + > > + (2) fully pin-mux (like phone exchange mux) pins: > > + GPIO 8 to 71 are 'fully pin-mux' pins. Any pins of peripherals of > > + SP7021 (ex: UART_1, UART_2, UART_3, UART_4, I2C_0, I2C_1, and etc.) > > + can be routed to any pins of fully pin-mux pins. > > + > > + Ex 1 (UART channel 1): > > + If control-field UA1_TX_SEL is set to 3, TX pin of UART_1 will be > > + routed to GPIO 10 (3 - 1 + 8 = 10). > > + If control-field UA1_RX_SEL is set to 4, RX pin of UART_1 will be > > + routed to GPIO 11 (4 - 1 + 8 = 11). > > + If control-field UA1_RTS_SEL is set to 5, RTS pin of UART_1 will > > + be routed to GPIO 12 (5 - 1 + 8 = 12). > > + If control-field UA1_CTS_SEL is set to 6, CTS pin of UART_1 will > > + be routed to GPIO 13 (6 - 1 + 8 = 13). > > + > > + Ex 2 (I2C channel 0): > > + If control-field I2C0_CLK_SEL is set to 20, CLK pin of I2C_0 will > > + be routed to GPIO 27 (20 - 1 + 8 = 27). > > + If control-field I2C0_DATA_SEL is set to 21, DATA pin of I2C_0 > > + will be routed to GPIO 28 (21 - 1 + 9 = 28). > > + > > + Totally, SP7021 has 120 peripheral pins. The peripheral pins can be > > + routed to any of 64 'fully pin-mux' pins. > > + > > + (3) I/O processor pins > > + SP7021 has a built-in I/O processor. > > + Any GPIO pins (GPIO 0 to 98) can be set to pins of I/O processor. > > + > > + Vendor property "sunplus,pins" is used to select "fully pin-mux" > > + pins, "I/O processor pins" and "digital GPIO" pins. > > + > > + The device node of pin controller of Sunplus SP7021 has following > > + properties. > > + > > +properties: > > + compatible: > > + const: sunplus,sp7021-pctl > > + > > + gpio-controller: true > > + > > + '#gpio-cells': > > + const: 2 > > + > > + reg: > > + items: > > + - description: the MOON2 registers > > + - description: the GPIOXT registers > > + - description: the FIRST registers > > + - description: the MOON1 registers > > + > > + reg-names: > > + items: > > + - const: moon2 > > + - const: gpioxt > > + - const: first > > + - const: moon1 > > + > > + clocks: > > + maxItems: 1 > > + > > + resets: > > + maxItems: 1 > > + > > +patternProperties: > > + '-pins$': > > + type: object > > + description: | > > + A pinctrl node should contain at least one subnodes representing the > > + pins or function-pins group available on the machine. Each subnode > > + will list the pins it needs, and how they should be configured. > > + > > + Pinctrl node's client devices use subnodes for desired pin > > + configuration. Client device subnodes use below standard properties. > > Need a $ref to pinmux-node.yaml I'll add "$ref to pinmux-node.yaml" next patch. > > + > > + properties: > > + sunplus,pins: > > Can't you just use 'pins' here? No, property "sunplus,pins" defined here is different from standard property "pins". Mr. Linus Walleij asked me to add "sunplus," prefix. > > + description: | > > + Define 'sunplus,pins' which are used by pinctrl node's client > > + device. > > + > > + It consists of one or more integers which represents the config > > + setting for corresponding pin. Each integer defines a individual > > + pin in which: > > + > > + Bit 32~24: defines GPIO number. Its range is 0 ~ 98. > > + Bit 23~16: defines types: (1) fully pin-mux pins > > + (2) IO processor pins > > + (3) digital GPIO pins > > + Bit 15~8: defines pins of peripherals (which are defined in > > + 'include/dt-binging/pinctrl/sppctl.h'). > > + Bit 7~0: defines types or initial-state of digital GPIO pins. > > + > > + Please use macro SPPCTL_IOPAD to define the integers for pins. > > + > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > + > > + function: > > + description: | > > + Define pin-function which is used by pinctrl node's client device. > > + The name should be one of string in the following enumeration. > > + $ref: "/schemas/types.yaml#/definitions/string" > > + enum: [ SPI_FLASH, SPI_FLASH_4BIT, SPI_NAND, CARD0_EMMC, SD_CARD, > > + UA0, FPGA_IFX, HDMI_TX, LCDIF, USB0_OTG, USB1_OTG ] > > + > > + groups: > > + description: | > > + Define pin-group in a specified pin-function. > > + The name should be one of string in the following enumeration. > > + $ref: "/schemas/types.yaml#/definitions/string" > > + enum: [ SPI_FLASH1, SPI_FLASH2, SPI_FLASH_4BIT1, SPI_FLASH_4BIT2, > > + SPI_NAND, CARD0_EMMC, SD_CARD, UA0, FPGA_IFX, HDMI_TX1, > > + HDMI_TX2, HDMI_TX3, LCDIF, USB0_OTG, USB1_OTG ] > > + > > + sunplus,zero_func: > > Don't use '_' in property names. I'll rename it to "sunplus,zerofunc" next patch. > > + description: | > > + This is a vendor specific property. It is used to disable pins > > + which are not used by pinctrl node's client device. > > + Some pins may be enabled by boot-loader. We can use this > > + property to disable them. > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > IMO, disabled pins should be unused by the board design, not ones the bootloader failed > to disable. I am sorry. I don't understand this comment. Could I have more explanation? What is IMO? The property "sunplus,zerofunc" is used to disable pins which are enabled by boot-loader. For example, boot-loader, U-Boot, enables a set of I2C pins. The I2C pins keep enabled when Linux boot up. We can use "sunplus,zerofunc" to disable the I2C pins in Linux. > > + > > + additionalProperties: false > > + > > + allOf: > > + - if: > > + properties: > > + function: > > + enum: > > + - SPI_FLASH > > + then: > > + properties: > > + groups: > > + enum: > > + - SPI_FLASH1 > > + - SPI_FLASH2 > > + - if: > > + properties: > > + function: > > + enum: > > + - SPI_FLASH_4BIT > > + then: > > + properties: > > + groups: > > + enum: > > + - SPI_FLASH_4BIT1 > > + - SPI_FLASH_4BIT2 > > + - if: > > + properties: > > + function: > > + enum: > > + - SPI_NAND > > + then: > > + properties: > > + groups: > > + enum: > > + - SPI_NAND > > + - if: > > + properties: > > + function: > > + enum: > > + - CARD0_EMMC > > + then: > > + properties: > > + groups: > > + enum: > > + - CARD0_EMMC > > + - if: > > + properties: > > + function: > > + enum: > > + - SD_CARD > > + then: > > + properties: > > + groups: > > + enum: > > + - SD_CARD > > + - if: > > + properties: > > + function: > > + enum: > > + - UA0 > > + then: > > + properties: > > + groups: > > + enum: > > + - UA0 > > + - if: > > + properties: > > + function: > > + enum: > > + - FPGA_IFX > > + then: > > + properties: > > + groups: > > + enum: > > + - FPGA_IFX > > + - if: > > + properties: > > + function: > > + enum: > > + - HDMI_TX > > + then: > > + properties: > > + groups: > > + enum: > > + - HDMI_TX1 > > + - HDMI_TX2 > > + - HDMI_TX3 > > + - if: > > + properties: > > + function: > > + enum: > > + - LCDIF > > + then: > > + properties: > > + groups: > > + enum: > > + - LCDIF > > + - if: > > + properties: > > + function: > > + enum: > > + - USB0_OTG > > + then: > > + properties: > > + groups: > > + enum: > > + - USB0_OTG > > + - if: > > + properties: > > + function: > > + enum: > > + - USB1_OTG > > + then: > > + properties: > > + groups: > > + enum: > > + - USB1_OTG > > + > > +required: > > + - compatible > > + - reg > > + - reg-names > > + - "#gpio-cells" > > + - gpio-controller > > + - clocks > > + - resets > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + > > + pinctl@9c000100 { > > + compatible = "sunplus,sp7021-pctl"; > > + reg = <0x9c000100 0x100>, <0x9c000300 0x100>, > > + <0x9c0032e4 0x1c>, <0x9c000080 0x20>; > > + reg-names = "moon2", "gpioxt", "first", "moon1"; > > + gpio-controller; > > + #gpio-cells = <2>; > > + clocks = <&clkc 0x83>; > > + resets = <&rstc 0x73>; > > + > > + uart0-pins { > > + function = "UA0"; > > + groups = "UA0"; > > + }; > > + > > + spinand0-pins { > > + function = "SPI_NAND"; > > + groups = "SPI_NAND"; > > + }; > > + > > + uart1-pins { > > + sunplus,pins = < > > + SPPCTL_IOPAD(11, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0) > > + SPPCTL_IOPAD(10, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0) > > + >; > > + }; > > + > > + uart2-pins { > > + sunplus,pins = < > > + SPPCTL_IOPAD(20, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0) > > + SPPCTL_IOPAD(21, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0) > > + SPPCTL_IOPAD(22, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RTS, 0) > > + SPPCTL_IOPAD(23, SPPCTL_PCTL_G_PMUX, MUXF_UA1_CTS, 0) > > + >; > > + }; > > + > > + emmc-pins { > > + function = "CARD0_EMMC"; > > + groups = "CARD0_EMMC"; > > + }; > > + > > + sdcard-pins { > > + function = "SD_CARD"; > > + groups = "SD_CARD"; > > + sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >; > > + }; > > + > > + hdmi_A_tx1-pins { > > + function = "HDMI_TX"; > > + groups = "HDMI_TX1"; > > + }; > > + hdmi_A_tx2-pins { > > + function = "HDMI_TX"; > > + groups = "HDMI_TX2"; > > + }; > > + hdmi_A_tx3-pins { > > + function = "HDMI_TX"; > > + groups = "HDMI_TX3"; > > + }; > > + > > + ethernet-pins { > > + sunplus,pins = < > > + SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0) > > + SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0) > > + SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0) > > + SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0) > > + SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0) > > + SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0) > > + SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0) > > + SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0) > > + SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0) > > + >; > > + sunplus,zero_func = < > > + MUXF_L2SW_LED_FLASH0 > > + MUXF_L2SW_LED_ON0 > > + MUXF_L2SW_P0_MAC_RMII_RXER > > + >; > > + }; > > + }; > > +... > > diff --git a/MAINTAINERS b/MAINTAINERS index 8912b2c..6b1cfc2 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -15127,6 +15127,15 @@ L: linux-omap@vger.kernel.org > > S: Maintained > > F: drivers/pinctrl/pinctrl-single.c > > > > +PIN CONTROLLER - SUNPLUS / TIBBO > > +M: Dvorkin Dmitry > > +M: Wells Lu > > +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) > > +S: Maintained > > +W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview > > +F: Documentation/devicetree/bindings/pinctrl/sunplus,* > > +F: include/dt-bindings/pinctrl/sppctl* > > + > > PKTCDVD DRIVER > > M: linux-block@vger.kernel.org > > S: Orphan > > diff --git a/include/dt-bindings/pinctrl/sppctl-sp7021.h > > b/include/dt-bindings/pinctrl/sppctl-sp7021.h > > new file mode 100644 > > index 0000000..8299ca1 > > --- /dev/null > > +++ b/include/dt-bindings/pinctrl/sppctl-sp7021.h > > @@ -0,0 +1,171 @@ > > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > > +/* Sunplus SP7021 dt-bindings Pinctrl header file > > + * Copyright (C) Sunplus Tech/Tibbo Tech. > > + * Author: Dvorkin Dmitry */ > > + > > +#ifndef __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__ > > +#define __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__ > > + > > +#include > > + > > +/* Please don't change the order of the > > + * following defines. They are based on > > + * order of control register define of > > + * MOON1 ~ MOON4 registers. > > + */ > > +#define MUXF_L2SW_CLK_OUT 0 > > +#define MUXF_L2SW_MAC_SMI_MDC 1 > > +#define MUXF_L2SW_LED_FLASH0 2 > > +#define MUXF_L2SW_LED_FLASH1 3 > > +#define MUXF_L2SW_LED_ON0 4 > > +#define MUXF_L2SW_LED_ON1 5 > > +#define MUXF_L2SW_MAC_SMI_MDIO 6 > > +#define MUXF_L2SW_P0_MAC_RMII_TXEN 7 > > +#define MUXF_L2SW_P0_MAC_RMII_TXD0 8 > > +#define MUXF_L2SW_P0_MAC_RMII_TXD1 9 > > +#define MUXF_L2SW_P0_MAC_RMII_CRSDV 10 > > +#define MUXF_L2SW_P0_MAC_RMII_RXD0 11 > > +#define MUXF_L2SW_P0_MAC_RMII_RXD1 12 > > +#define MUXF_L2SW_P0_MAC_RMII_RXER 13 > > +#define MUXF_L2SW_P1_MAC_RMII_TXEN 14 > > +#define MUXF_L2SW_P1_MAC_RMII_TXD0 15 > > +#define MUXF_L2SW_P1_MAC_RMII_TXD1 16 > > +#define MUXF_L2SW_P1_MAC_RMII_CRSDV 17 > > +#define MUXF_L2SW_P1_MAC_RMII_RXD0 18 > > +#define MUXF_L2SW_P1_MAC_RMII_RXD1 19 > > +#define MUXF_L2SW_P1_MAC_RMII_RXER 20 > > +#define MUXF_DAISY_MODE 21 > > +#define MUXF_SDIO_CLK 22 > > +#define MUXF_SDIO_CMD 23 > > +#define MUXF_SDIO_D0 24 > > +#define MUXF_SDIO_D1 25 > > +#define MUXF_SDIO_D2 26 > > +#define MUXF_SDIO_D3 27 > > +#define MUXF_PWM0 28 > > +#define MUXF_PWM1 29 > > +#define MUXF_PWM2 30 > > +#define MUXF_PWM3 31 > > +#define MUXF_PWM4 32 > > +#define MUXF_PWM5 33 > > +#define MUXF_PWM6 34 > > +#define MUXF_PWM7 35 > > +#define MUXF_ICM0_D 36 > > +#define MUXF_ICM1_D 37 > > +#define MUXF_ICM2_D 38 > > +#define MUXF_ICM3_D 39 > > +#define MUXF_ICM0_CLK 40 > > +#define MUXF_ICM1_CLK 41 > > +#define MUXF_ICM2_CLK 42 > > +#define MUXF_ICM3_CLK 43 > > +#define MUXF_SPIM0_INT 44 > > +#define MUXF_SPIM0_CLK 45 > > +#define MUXF_SPIM0_EN 46 > > +#define MUXF_SPIM0_DO 47 > > +#define MUXF_SPIM0_DI 48 > > +#define MUXF_SPIM1_INT 49 > > +#define MUXF_SPIM1_CLK 50 > > +#define MUXF_SPIM1_EN 51 > > +#define MUXF_SPIM1_DO 52 > > +#define MUXF_SPIM1_DI 53 > > +#define MUXF_SPIM2_INT 54 > > +#define MUXF_SPIM2_CLK 55 > > +#define MUXF_SPIM2_EN 56 > > +#define MUXF_SPIM2_DO 57 > > +#define MUXF_SPIM2_DI 58 > > +#define MUXF_SPIM3_INT 59 > > +#define MUXF_SPIM3_CLK 60 > > +#define MUXF_SPIM3_EN 61 > > +#define MUXF_SPIM3_DO 62 > > +#define MUXF_SPIM3_DI 63 > > +#define MUXF_SPI0S_INT 64 > > +#define MUXF_SPI0S_CLK 65 > > +#define MUXF_SPI0S_EN 66 > > +#define MUXF_SPI0S_DO 67 > > +#define MUXF_SPI0S_DI 68 > > +#define MUXF_SPI1S_INT 69 > > +#define MUXF_SPI1S_CLK 70 > > +#define MUXF_SPI1S_EN 71 > > +#define MUXF_SPI1S_DO 72 > > +#define MUXF_SPI1S_DI 73 > > +#define MUXF_SPI2S_INT 74 > > +#define MUXF_SPI2S_CLK 75 > > +#define MUXF_SPI2S_EN 76 > > +#define MUXF_SPI2S_DO 77 > > +#define MUXF_SPI2S_DI 78 > > +#define MUXF_SPI3S_INT 79 > > +#define MUXF_SPI3S_CLK 80 > > +#define MUXF_SPI3S_EN 81 > > +#define MUXF_SPI3S_DO 82 > > +#define MUXF_SPI3S_DI 83 > > +#define MUXF_I2CM0_CLK 84 > > +#define MUXF_I2CM0_DAT 85 > > +#define MUXF_I2CM1_CLK 86 > > +#define MUXF_I2CM1_DAT 87 > > +#define MUXF_I2CM2_CLK 88 > > +#define MUXF_I2CM2_DAT 89 > > +#define MUXF_I2CM3_CLK 90 > > +#define MUXF_I2CM3_DAT 91 > > +#define MUXF_UA1_TX 92 > > +#define MUXF_UA1_RX 93 > > +#define MUXF_UA1_CTS 94 > > +#define MUXF_UA1_RTS 95 > > +#define MUXF_UA2_TX 96 > > +#define MUXF_UA2_RX 97 > > +#define MUXF_UA2_CTS 98 > > +#define MUXF_UA2_RTS 99 > > +#define MUXF_UA3_TX 100 > > +#define MUXF_UA3_RX 101 > > +#define MUXF_UA3_CTS 102 > > +#define MUXF_UA3_RTS 103 > > +#define MUXF_UA4_TX 104 > > +#define MUXF_UA4_RX 105 > > +#define MUXF_UA4_CTS 106 > > +#define MUXF_UA4_RTS 107 > > +#define MUXF_TIMER0_INT 108 > > +#define MUXF_TIMER1_INT 109 > > +#define MUXF_TIMER2_INT 110 > > +#define MUXF_TIMER3_INT 111 > > +#define MUXF_GPIO_INT0 112 > > +#define MUXF_GPIO_INT1 113 > > +#define MUXF_GPIO_INT2 114 > > +#define MUXF_GPIO_INT3 115 > > +#define MUXF_GPIO_INT4 116 > > +#define MUXF_GPIO_INT5 117 > > +#define MUXF_GPIO_INT6 118 > > +#define MUXF_GPIO_INT7 119 > > + > > +#define GROP_SPI_FLASH 120 > > +#define GROP_SPI_FLASH_4BIT 121 > > +#define GROP_SPI_NAND 122 > > +#define GROP_CARD0_EMMC 123 > > +#define GROP_SD_CARD 124 > > +#define GROP_UA0 125 > > +#define GROP_ACHIP_DEBUG 126 > > +#define GROP_ACHIP_UA2AXI 127 > > +#define GROP_FPGA_IFX 128 > > +#define GROP_HDMI_TX 129 > > +#define GROP_AUD_EXT_ADC_IFX0 130 > > +#define GROP_AUD_EXT_DAC_IFX0 131 > > +#define GROP_SPDIF_RX 132 > > +#define GROP_SPDIF_TX 133 > > +#define GROP_TDMTX_IFX0 134 > > +#define GROP_TDMRX_IFX0 135 > > +#define GROP_PDMRX_IFX0 136 > > +#define GROP_PCM_IEC_TX 137 > > +#define GROP_LCDIF 138 > > +#define GROP_DVD_DSP_DEBUG 139 > > +#define GROP_I2C_DEBUG 140 > > +#define GROP_I2C_SLAVE 141 > > +#define GROP_WAKEUP 142 > > +#define GROP_UART2AXI 143 > > +#define GROP_USB0_I2C 144 > > +#define GROP_USB1_I2C 145 > > +#define GROP_USB0_OTG 146 > > +#define GROP_USB1_OTG 147 > > +#define GROP_UPHY0_DEBUG 148 > > +#define GROP_UPHY1_DEBUG 149 > > +#define GROP_UPHY0_EXT 150 > > +#define GROP_PROBE_PORT 151 > > + > > +#endif > > diff --git a/include/dt-bindings/pinctrl/sppctl.h > > b/include/dt-bindings/pinctrl/sppctl.h > > new file mode 100644 > > index 0000000..8bf5457 > > --- /dev/null > > +++ b/include/dt-bindings/pinctrl/sppctl.h > > @@ -0,0 +1,30 @@ > > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > > +/* Sunplus dt-bindings Pinctrl header file > > + * Copyright (C) Sunplus Tech / Tibbo Tech. > > + * Author: Dvorkin Dmitry */ > > + > > +#ifndef __DT_BINDINGS_PINCTRL_SPPCTL_H__ #define > > +__DT_BINDINGS_PINCTRL_SPPCTL_H__ > > + > > +#define IOP_G_MASTE (0x01 << 0) > > +#define IOP_G_FIRST (0x01 << 1) > > + > > +#define SPPCTL_PCTL_G_PMUX (0x00 | IOP_G_MASTE) > > +#define SPPCTL_PCTL_G_GPIO (IOP_G_FIRST | IOP_G_MASTE) > > +#define SPPCTL_PCTL_G_IOPP (IOP_G_FIRST | 0x00) > > + > > +#define SPPCTL_PCTL_L_OUT (0x01 << 0) /* Output LOW */ > > +#define SPPCTL_PCTL_L_OU1 (0x01 << 1) /* Output HIGH */ > > +#define SPPCTL_PCTL_L_INV (0x01 << 2) /* Input Invert */ > > +#define SPPCTL_PCTL_L_ONV (0x01 << 3) /* Output Invert */ > > +#define SPPCTL_PCTL_L_ODR (0x01 << 4) /* Output Open Drain */ > > + > > +/* > > + * pack into 32-bit value: > > + * pin#(8bit), typ(8bit), function(8bit), flag(8bit) */ > > +#define SPPCTL_IOPAD(pin, typ, fun, flg) (((pin) << 24) | ((typ) << 16) | \ > > + ((fun) << 8) | (flg)) > > + > > +#endif > > -- > > 2.7.4 > > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel