From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42650) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0qQa-00017c-0h for qemu-devel@nongnu.org; Fri, 05 Jun 2015 08:08:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0qQU-0007Lq-OO for qemu-devel@nongnu.org; Fri, 05 Jun 2015 08:08:47 -0400 Received: from mail.emea.novell.com ([130.57.118.101]:33584) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0qJZ-0004A1-OH for qemu-devel@nongnu.org; Fri, 05 Jun 2015 08:01:34 -0400 Message-Id: <5571ABBA0200007800081543@mail.emea.novell.com> Date: Fri, 05 Jun 2015 13:01:30 +0100 From: "Jan Beulich" References: <5571AA3B020000780008152E@mail.emea.novell.com> In-Reply-To: <5571AA3B020000780008152E@mail.emea.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part497D608A.2__=" Subject: [Qemu-devel] [PATCH 2/6] xen/MSI-X: drive maskall and enable bits through hypercalls List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: xen-devel , Stefano Stabellini This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part497D608A.2__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Particularly the maskall bit has to be under exclusive hypervisor control (and since they live in the same config space field, the enable bit has to follow suit). Use the replacement hypercall interfaces. Signed-off-by: Jan Beulich --- a/qemu/upstream/hw/xen/xen_pt.h +++ b/qemu/upstream/hw/xen/xen_pt.h @@ -181,6 +181,7 @@ typedef struct XenPTMSIXEntry { typedef struct XenPTMSIX { uint32_t ctrl_offset; bool enabled; + bool maskall; int total_entries; int bar_index; uint64_t table_base; @@ -293,7 +294,9 @@ int xen_pt_msix_init(XenPCIPassthroughSt void xen_pt_msix_delete(XenPCIPassthroughState *s); int xen_pt_msix_update(XenPCIPassthroughState *s); int xen_pt_msix_update_remap(XenPCIPassthroughState *s, int bar_index); +void xen_pt_msix_enable(XenPCIPassthroughState *s); void xen_pt_msix_disable(XenPCIPassthroughState *s); +int xen_pt_msix_maskall(XenPCIPassthroughState *s, bool mask); =20 static inline bool xen_pt_has_msix_mapping(XenPCIPassthroughState *s, int = bar) { --- a/qemu/upstream/hw/xen/xen_pt_config_init.c +++ b/qemu/upstream/hw/xen/xen_pt_config_init.c @@ -1436,32 +1436,58 @@ static int xen_pt_msixctrl_reg_write(Xen uint16_t dev_value, uint16_t = valid_mask) { XenPTRegInfo *reg =3D cfg_entry->reg; - uint16_t writable_mask =3D 0; + uint16_t writable_mask, value; uint16_t throughable_mask =3D get_throughable_mask(s, reg, valid_mask)= ; int debug_msix_enabled_old; =20 /* modify emulate register */ writable_mask =3D reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, = writable_mask); + value =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); + cfg_entry->data =3D value; =20 /* create value for writing to I/O device register */ *val =3D XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); =20 + debug_msix_enabled_old =3D s->msix->enabled; + /* update MSI-X */ - if ((*val & PCI_MSIX_FLAGS_ENABLE) - && !(*val & PCI_MSIX_FLAGS_MASKALL)) { + if ((value & PCI_MSIX_FLAGS_ENABLE) + && !(value & PCI_MSIX_FLAGS_MASKALL)) { + if (!s->msix->enabled) { + if (!s->msix->maskall) { + xen_pt_msix_maskall(s, true); + } + xen_pt_msix_enable(s); + } xen_pt_msix_update(s); - } else if (!(*val & PCI_MSIX_FLAGS_ENABLE) && s->msix->enabled) { - xen_pt_msix_disable(s); + s->msix->enabled =3D true; + s->msix->maskall =3D false; + xen_pt_msix_maskall(s, false); + } else if (s->msix->enabled) { + if (!(value & PCI_MSIX_FLAGS_ENABLE)) { + xen_pt_msix_disable(s); + s->msix->enabled =3D false; + } else if (!s->msix->maskall) { + s->msix->maskall =3D true; + xen_pt_msix_maskall(s, true); + } } =20 - debug_msix_enabled_old =3D s->msix->enabled; - s->msix->enabled =3D !!(*val & PCI_MSIX_FLAGS_ENABLE); if (s->msix->enabled !=3D debug_msix_enabled_old) { XEN_PT_LOG(&s->dev, "%s MSI-X\n", s->msix->enabled ? "enable" : "disable"); } =20 + xen_host_pci_get_word(&s->real_device, s->msix->ctrl_offset, = &dev_value); + + if (s->msix->enabled && !(dev_value & PCI_MSIX_FLAGS_ENABLE)) { + XEN_PT_ERR(&s->dev, "MSI-X unexpectedly disabled\n"); + } else if ((dev_value & PCI_MSIX_FLAGS_ENABLE) && + s->msix->maskall && + !(dev_value & PCI_MSIX_FLAGS_MASKALL)) { + XEN_PT_ERR(&s->dev, "MSI-X unexpectedly unmasked\n"); + } + return 0; } =20 @@ -1483,9 +1509,12 @@ static XenPTRegInfo xen_pt_emu_reg_msix[ .offset =3D PCI_MSI_FLAGS, .size =3D 2, .init_val =3D 0x0000, - .res_mask =3D 0x3800, - .ro_mask =3D 0x07FF, - .emu_mask =3D 0x0000, + /* This must not be split into res_mask (0x3800) and ro_mask = (0x07FF) + * because even in permissive mode there must not be any write = back + * to this register. + */ + .ro_mask =3D 0x3FFF, + .emu_mask =3D 0xC000, .init =3D xen_pt_msixctrl_reg_init, .u.w.read =3D xen_pt_word_reg_read, .u.w.write =3D xen_pt_msixctrl_reg_write, --- a/qemu/upstream/hw/xen/xen_pt_msi.c +++ b/qemu/upstream/hw/xen/xen_pt_msi.c @@ -301,8 +301,11 @@ static int msix_set_enable(XenPCIPassthr return -1; } =20 - return msi_msix_enable(s, s->msix->ctrl_offset, PCI_MSIX_FLAGS_ENABLE,= - enabled); + return xc_physdev_msix_enable(xen_xc, s->real_device.domain, + s->real_device.bus, + PCI_DEVFN(s->real_device.dev, + s->real_device.func), + enabled); } =20 static int xen_pt_msix_update_one(XenPCIPassthroughState *s, int = entry_nr) @@ -361,6 +364,11 @@ int xen_pt_msix_update(XenPCIPassthrough return 0; } =20 +void xen_pt_msix_enable(XenPCIPassthroughState *s) +{ + msix_set_enable(s, true); +} + void xen_pt_msix_disable(XenPCIPassthroughState *s) { int i =3D 0; @@ -378,6 +386,15 @@ void xen_pt_msix_disable(XenPCIPassthrou } } =20 +int xen_pt_msix_maskall(XenPCIPassthroughState *s, bool mask) +{ + return xc_physdev_msix_mask_all(xen_xc, s->real_device.domain, + s->real_device.bus, + PCI_DEVFN(s->real_device.dev, + s->real_device.func), + mask); +} + int xen_pt_msix_update_remap(XenPCIPassthroughState *s, int bar_index) { XenPTMSIXEntry *entry; --=__Part497D608A.2__= Content-Type: text/plain; name="qemu-MSI-X-enable-maskall.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="qemu-MSI-X-enable-maskall.patch" xen/MSI-X: drive maskall and enable bits through hypercalls=0A=0AParticular= ly the maskall bit has to be under exclusive hypervisor=0Acontrol (and = since they live in the same config space field, the=0Aenable bit has to = follow suit). Use the replacement hypercall=0Ainterfaces.=0A=0ASigned-off-b= y: Jan Beulich =0A=0A--- a/qemu/upstream/hw/xen/xen_pt.h= =0A+++ b/qemu/upstream/hw/xen/xen_pt.h=0A@@ -181,6 +181,7 @@ typedef = struct XenPTMSIXEntry {=0A typedef struct XenPTMSIX {=0A uint32_t = ctrl_offset;=0A bool enabled;=0A+ bool maskall;=0A int = total_entries;=0A int bar_index;=0A uint64_t table_base;=0A@@ = -293,7 +294,9 @@ int xen_pt_msix_init(XenPCIPassthroughSt=0A void = xen_pt_msix_delete(XenPCIPassthroughState *s);=0A int xen_pt_msix_update(Xe= nPCIPassthroughState *s);=0A int xen_pt_msix_update_remap(XenPCIPassthrough= State *s, int bar_index);=0A+void xen_pt_msix_enable(XenPCIPassthroughState= *s);=0A void xen_pt_msix_disable(XenPCIPassthroughState *s);=0A+int = xen_pt_msix_maskall(XenPCIPassthroughState *s, bool mask);=0A =0A static = inline bool xen_pt_has_msix_mapping(XenPCIPassthroughState *s, int bar)=0A = {=0A--- a/qemu/upstream/hw/xen/xen_pt_config_init.c=0A+++ b/qemu/upstream/h= w/xen/xen_pt_config_init.c=0A@@ -1436,32 +1436,58 @@ static int xen_pt_msix= ctrl_reg_write(Xen=0A uint16_t = dev_value, uint16_t valid_mask)=0A {=0A XenPTRegInfo *reg =3D = cfg_entry->reg;=0A- uint16_t writable_mask =3D 0;=0A+ uint16_t = writable_mask, value;=0A uint16_t throughable_mask =3D get_throughable_= mask(s, reg, valid_mask);=0A int debug_msix_enabled_old;=0A =0A /* = modify emulate register */=0A writable_mask =3D reg->emu_mask & = ~reg->ro_mask & valid_mask;=0A- cfg_entry->data =3D XEN_PT_MERGE_VALUE(*= val, cfg_entry->data, writable_mask);=0A+ value =3D XEN_PT_MERGE_VALUE(*= val, cfg_entry->data, writable_mask);=0A+ cfg_entry->data =3D value;=0A = =0A /* create value for writing to I/O device register */=0A *val = =3D XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);=0A =0A+ = debug_msix_enabled_old =3D s->msix->enabled;=0A+=0A /* update MSI-X = */=0A- if ((*val & PCI_MSIX_FLAGS_ENABLE)=0A- && !(*val & = PCI_MSIX_FLAGS_MASKALL)) {=0A+ if ((value & PCI_MSIX_FLAGS_ENABLE)=0A+ = && !(value & PCI_MSIX_FLAGS_MASKALL)) {=0A+ if (!s->msix->enab= led) {=0A+ if (!s->msix->maskall) {=0A+ = xen_pt_msix_maskall(s, true);=0A+ }=0A+ xen_pt_msix_e= nable(s);=0A+ }=0A xen_pt_msix_update(s);=0A- } else if = (!(*val & PCI_MSIX_FLAGS_ENABLE) && s->msix->enabled) {=0A- = xen_pt_msix_disable(s);=0A+ s->msix->enabled =3D true;=0A+ = s->msix->maskall =3D false;=0A+ xen_pt_msix_maskall(s, false);=0A+ = } else if (s->msix->enabled) {=0A+ if (!(value & PCI_MSIX_FLAGS_EN= ABLE)) {=0A+ xen_pt_msix_disable(s);=0A+ s->msix->ena= bled =3D false;=0A+ } else if (!s->msix->maskall) {=0A+ = s->msix->maskall =3D true;=0A+ xen_pt_msix_maskall(s, true);=0A+= }=0A }=0A =0A- debug_msix_enabled_old =3D s->msix->enabled;= =0A- s->msix->enabled =3D !!(*val & PCI_MSIX_FLAGS_ENABLE);=0A if = (s->msix->enabled !=3D debug_msix_enabled_old) {=0A XEN_PT_LOG(&s->= dev, "%s MSI-X\n",=0A s->msix->enabled ? "enable" : = "disable");=0A }=0A =0A+ xen_host_pci_get_word(&s->real_device, = s->msix->ctrl_offset, &dev_value);=0A+=0A+ if (s->msix->enabled && = !(dev_value & PCI_MSIX_FLAGS_ENABLE)) {=0A+ XEN_PT_ERR(&s->dev, = "MSI-X unexpectedly disabled\n");=0A+ } else if ((dev_value & PCI_MSIX_F= LAGS_ENABLE) &&=0A+ s->msix->maskall &&=0A+ = !(dev_value & PCI_MSIX_FLAGS_MASKALL)) {=0A+ XEN_PT_ERR(&s->dev, = "MSI-X unexpectedly unmasked\n");=0A+ }=0A+=0A return 0;=0A }=0A = =0A@@ -1483,9 +1509,12 @@ static XenPTRegInfo xen_pt_emu_reg_msix[=0A = .offset =3D PCI_MSI_FLAGS,=0A .size =3D 2,=0A = .init_val =3D 0x0000,=0A- .res_mask =3D 0x3800,=0A- = .ro_mask =3D 0x07FF,=0A- .emu_mask =3D 0x0000,=0A+ /* = This must not be split into res_mask (0x3800) and ro_mask (0x07FF)=0A+ = * because even in permissive mode there must not be any write back=0A+ = * to this register.=0A+ */=0A+ .ro_mask =3D = 0x3FFF,=0A+ .emu_mask =3D 0xC000,=0A .init =3D = xen_pt_msixctrl_reg_init,=0A .u.w.read =3D xen_pt_word_reg_read,= =0A .u.w.write =3D xen_pt_msixctrl_reg_write,=0A--- a/qemu/upstrea= m/hw/xen/xen_pt_msi.c=0A+++ b/qemu/upstream/hw/xen/xen_pt_msi.c=0A@@ = -301,8 +301,11 @@ static int msix_set_enable(XenPCIPassthr=0A = return -1;=0A }=0A =0A- return msi_msix_enable(s, s->msix->ctrl_offs= et, PCI_MSIX_FLAGS_ENABLE,=0A- enabled);=0A+ = return xc_physdev_msix_enable(xen_xc, s->real_device.domain,=0A+ = s->real_device.bus,=0A+ = PCI_DEVFN(s->real_device.dev,=0A+ = s->real_device.func),=0A+ = enabled);=0A }=0A =0A static int xen_pt_msix_update_one(XenPCIPassthroughSt= ate *s, int entry_nr)=0A@@ -361,6 +364,11 @@ int xen_pt_msix_update(XenPCIP= assthrough=0A return 0;=0A }=0A =0A+void xen_pt_msix_enable(XenPCIPasst= hroughState *s)=0A+{=0A+ msix_set_enable(s, true);=0A+}=0A+=0A void = xen_pt_msix_disable(XenPCIPassthroughState *s)=0A {=0A int i =3D = 0;=0A@@ -378,6 +386,15 @@ void xen_pt_msix_disable(XenPCIPassthrou=0A = }=0A }=0A =0A+int xen_pt_msix_maskall(XenPCIPassthroughState *s, bool = mask)=0A+{=0A+ return xc_physdev_msix_mask_all(xen_xc, s->real_device.do= main,=0A+ s->real_device.bus,=0A+ = PCI_DEVFN(s->real_device.dev,=0A+ = s->real_device.func),=0A+ = mask);=0A+}=0A+=0A int xen_pt_msix_update_remap(XenPCIPa= ssthroughState *s, int bar_index)=0A {=0A XenPTMSIXEntry *entry;=0A --=__Part497D608A.2__=-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH 2/6] xen/MSI-X: drive maskall and enable bits through hypercalls Date: Fri, 05 Jun 2015 13:01:30 +0100 Message-ID: <5571ABBA0200007800081543@mail.emea.novell.com> References: <5571AA3B020000780008152E@mail.emea.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part497D608A.1__=" Return-path: Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Z0qJa-0008J9-Q5 for xen-devel@lists.xenproject.org; Fri, 05 Jun 2015 12:01:35 +0000 In-Reply-To: <5571AA3B020000780008152E@mail.emea.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: qemu-devel@nongnu.org Cc: xen-devel , Stefano Stabellini List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part497D608A.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Particularly the maskall bit has to be under exclusive hypervisor control (and since they live in the same config space field, the enable bit has to follow suit). Use the replacement hypercall interfaces. Signed-off-by: Jan Beulich --- a/qemu/upstream/hw/xen/xen_pt.h +++ b/qemu/upstream/hw/xen/xen_pt.h @@ -181,6 +181,7 @@ typedef struct XenPTMSIXEntry { typedef struct XenPTMSIX { uint32_t ctrl_offset; bool enabled; + bool maskall; int total_entries; int bar_index; uint64_t table_base; @@ -293,7 +294,9 @@ int xen_pt_msix_init(XenPCIPassthroughSt void xen_pt_msix_delete(XenPCIPassthroughState *s); int xen_pt_msix_update(XenPCIPassthroughState *s); int xen_pt_msix_update_remap(XenPCIPassthroughState *s, int bar_index); +void xen_pt_msix_enable(XenPCIPassthroughState *s); void xen_pt_msix_disable(XenPCIPassthroughState *s); +int xen_pt_msix_maskall(XenPCIPassthroughState *s, bool mask); =20 static inline bool xen_pt_has_msix_mapping(XenPCIPassthroughState *s, int = bar) { --- a/qemu/upstream/hw/xen/xen_pt_config_init.c +++ b/qemu/upstream/hw/xen/xen_pt_config_init.c @@ -1436,32 +1436,58 @@ static int xen_pt_msixctrl_reg_write(Xen uint16_t dev_value, uint16_t = valid_mask) { XenPTRegInfo *reg =3D cfg_entry->reg; - uint16_t writable_mask =3D 0; + uint16_t writable_mask, value; uint16_t throughable_mask =3D get_throughable_mask(s, reg, valid_mask)= ; int debug_msix_enabled_old; =20 /* modify emulate register */ writable_mask =3D reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, = writable_mask); + value =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); + cfg_entry->data =3D value; =20 /* create value for writing to I/O device register */ *val =3D XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); =20 + debug_msix_enabled_old =3D s->msix->enabled; + /* update MSI-X */ - if ((*val & PCI_MSIX_FLAGS_ENABLE) - && !(*val & PCI_MSIX_FLAGS_MASKALL)) { + if ((value & PCI_MSIX_FLAGS_ENABLE) + && !(value & PCI_MSIX_FLAGS_MASKALL)) { + if (!s->msix->enabled) { + if (!s->msix->maskall) { + xen_pt_msix_maskall(s, true); + } + xen_pt_msix_enable(s); + } xen_pt_msix_update(s); - } else if (!(*val & PCI_MSIX_FLAGS_ENABLE) && s->msix->enabled) { - xen_pt_msix_disable(s); + s->msix->enabled =3D true; + s->msix->maskall =3D false; + xen_pt_msix_maskall(s, false); + } else if (s->msix->enabled) { + if (!(value & PCI_MSIX_FLAGS_ENABLE)) { + xen_pt_msix_disable(s); + s->msix->enabled =3D false; + } else if (!s->msix->maskall) { + s->msix->maskall =3D true; + xen_pt_msix_maskall(s, true); + } } =20 - debug_msix_enabled_old =3D s->msix->enabled; - s->msix->enabled =3D !!(*val & PCI_MSIX_FLAGS_ENABLE); if (s->msix->enabled !=3D debug_msix_enabled_old) { XEN_PT_LOG(&s->dev, "%s MSI-X\n", s->msix->enabled ? "enable" : "disable"); } =20 + xen_host_pci_get_word(&s->real_device, s->msix->ctrl_offset, = &dev_value); + + if (s->msix->enabled && !(dev_value & PCI_MSIX_FLAGS_ENABLE)) { + XEN_PT_ERR(&s->dev, "MSI-X unexpectedly disabled\n"); + } else if ((dev_value & PCI_MSIX_FLAGS_ENABLE) && + s->msix->maskall && + !(dev_value & PCI_MSIX_FLAGS_MASKALL)) { + XEN_PT_ERR(&s->dev, "MSI-X unexpectedly unmasked\n"); + } + return 0; } =20 @@ -1483,9 +1509,12 @@ static XenPTRegInfo xen_pt_emu_reg_msix[ .offset =3D PCI_MSI_FLAGS, .size =3D 2, .init_val =3D 0x0000, - .res_mask =3D 0x3800, - .ro_mask =3D 0x07FF, - .emu_mask =3D 0x0000, + /* This must not be split into res_mask (0x3800) and ro_mask = (0x07FF) + * because even in permissive mode there must not be any write = back + * to this register. + */ + .ro_mask =3D 0x3FFF, + .emu_mask =3D 0xC000, .init =3D xen_pt_msixctrl_reg_init, .u.w.read =3D xen_pt_word_reg_read, .u.w.write =3D xen_pt_msixctrl_reg_write, --- a/qemu/upstream/hw/xen/xen_pt_msi.c +++ b/qemu/upstream/hw/xen/xen_pt_msi.c @@ -301,8 +301,11 @@ static int msix_set_enable(XenPCIPassthr return -1; } =20 - return msi_msix_enable(s, s->msix->ctrl_offset, PCI_MSIX_FLAGS_ENABLE,= - enabled); + return xc_physdev_msix_enable(xen_xc, s->real_device.domain, + s->real_device.bus, + PCI_DEVFN(s->real_device.dev, + s->real_device.func), + enabled); } =20 static int xen_pt_msix_update_one(XenPCIPassthroughState *s, int = entry_nr) @@ -361,6 +364,11 @@ int xen_pt_msix_update(XenPCIPassthrough return 0; } =20 +void xen_pt_msix_enable(XenPCIPassthroughState *s) +{ + msix_set_enable(s, true); +} + void xen_pt_msix_disable(XenPCIPassthroughState *s) { int i =3D 0; @@ -378,6 +386,15 @@ void xen_pt_msix_disable(XenPCIPassthrou } } =20 +int xen_pt_msix_maskall(XenPCIPassthroughState *s, bool mask) +{ + return xc_physdev_msix_mask_all(xen_xc, s->real_device.domain, + s->real_device.bus, + PCI_DEVFN(s->real_device.dev, + s->real_device.func), + mask); +} + int xen_pt_msix_update_remap(XenPCIPassthroughState *s, int bar_index) { XenPTMSIXEntry *entry; --=__Part497D608A.1__= Content-Type: text/plain; name="qemu-MSI-X-enable-maskall.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="qemu-MSI-X-enable-maskall.patch" xen/MSI-X: drive maskall and enable bits through hypercalls=0A=0AParticular= ly the maskall bit has to be under exclusive hypervisor=0Acontrol (and = since they live in the same config space field, the=0Aenable bit has to = follow suit). Use the replacement hypercall=0Ainterfaces.=0A=0ASigned-off-b= y: Jan Beulich =0A=0A--- a/qemu/upstream/hw/xen/xen_pt.h= =0A+++ b/qemu/upstream/hw/xen/xen_pt.h=0A@@ -181,6 +181,7 @@ typedef = struct XenPTMSIXEntry {=0A typedef struct XenPTMSIX {=0A uint32_t = ctrl_offset;=0A bool enabled;=0A+ bool maskall;=0A int = total_entries;=0A int bar_index;=0A uint64_t table_base;=0A@@ = -293,7 +294,9 @@ int xen_pt_msix_init(XenPCIPassthroughSt=0A void = xen_pt_msix_delete(XenPCIPassthroughState *s);=0A int xen_pt_msix_update(Xe= nPCIPassthroughState *s);=0A int xen_pt_msix_update_remap(XenPCIPassthrough= State *s, int bar_index);=0A+void xen_pt_msix_enable(XenPCIPassthroughState= *s);=0A void xen_pt_msix_disable(XenPCIPassthroughState *s);=0A+int = xen_pt_msix_maskall(XenPCIPassthroughState *s, bool mask);=0A =0A static = inline bool xen_pt_has_msix_mapping(XenPCIPassthroughState *s, int bar)=0A = {=0A--- a/qemu/upstream/hw/xen/xen_pt_config_init.c=0A+++ b/qemu/upstream/h= w/xen/xen_pt_config_init.c=0A@@ -1436,32 +1436,58 @@ static int xen_pt_msix= ctrl_reg_write(Xen=0A uint16_t = dev_value, uint16_t valid_mask)=0A {=0A XenPTRegInfo *reg =3D = cfg_entry->reg;=0A- uint16_t writable_mask =3D 0;=0A+ uint16_t = writable_mask, value;=0A uint16_t throughable_mask =3D get_throughable_= mask(s, reg, valid_mask);=0A int debug_msix_enabled_old;=0A =0A /* = modify emulate register */=0A writable_mask =3D reg->emu_mask & = ~reg->ro_mask & valid_mask;=0A- cfg_entry->data =3D XEN_PT_MERGE_VALUE(*= val, cfg_entry->data, writable_mask);=0A+ value =3D XEN_PT_MERGE_VALUE(*= val, cfg_entry->data, writable_mask);=0A+ cfg_entry->data =3D value;=0A = =0A /* create value for writing to I/O device register */=0A *val = =3D XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);=0A =0A+ = debug_msix_enabled_old =3D s->msix->enabled;=0A+=0A /* update MSI-X = */=0A- if ((*val & PCI_MSIX_FLAGS_ENABLE)=0A- && !(*val & = PCI_MSIX_FLAGS_MASKALL)) {=0A+ if ((value & PCI_MSIX_FLAGS_ENABLE)=0A+ = && !(value & PCI_MSIX_FLAGS_MASKALL)) {=0A+ if (!s->msix->enab= led) {=0A+ if (!s->msix->maskall) {=0A+ = xen_pt_msix_maskall(s, true);=0A+ }=0A+ xen_pt_msix_e= nable(s);=0A+ }=0A xen_pt_msix_update(s);=0A- } else if = (!(*val & PCI_MSIX_FLAGS_ENABLE) && s->msix->enabled) {=0A- = xen_pt_msix_disable(s);=0A+ s->msix->enabled =3D true;=0A+ = s->msix->maskall =3D false;=0A+ xen_pt_msix_maskall(s, false);=0A+ = } else if (s->msix->enabled) {=0A+ if (!(value & PCI_MSIX_FLAGS_EN= ABLE)) {=0A+ xen_pt_msix_disable(s);=0A+ s->msix->ena= bled =3D false;=0A+ } else if (!s->msix->maskall) {=0A+ = s->msix->maskall =3D true;=0A+ xen_pt_msix_maskall(s, true);=0A+= }=0A }=0A =0A- debug_msix_enabled_old =3D s->msix->enabled;= =0A- s->msix->enabled =3D !!(*val & PCI_MSIX_FLAGS_ENABLE);=0A if = (s->msix->enabled !=3D debug_msix_enabled_old) {=0A XEN_PT_LOG(&s->= dev, "%s MSI-X\n",=0A s->msix->enabled ? "enable" : = "disable");=0A }=0A =0A+ xen_host_pci_get_word(&s->real_device, = s->msix->ctrl_offset, &dev_value);=0A+=0A+ if (s->msix->enabled && = !(dev_value & PCI_MSIX_FLAGS_ENABLE)) {=0A+ XEN_PT_ERR(&s->dev, = "MSI-X unexpectedly disabled\n");=0A+ } else if ((dev_value & PCI_MSIX_F= LAGS_ENABLE) &&=0A+ s->msix->maskall &&=0A+ = !(dev_value & PCI_MSIX_FLAGS_MASKALL)) {=0A+ XEN_PT_ERR(&s->dev, = "MSI-X unexpectedly unmasked\n");=0A+ }=0A+=0A return 0;=0A }=0A = =0A@@ -1483,9 +1509,12 @@ static XenPTRegInfo xen_pt_emu_reg_msix[=0A = .offset =3D PCI_MSI_FLAGS,=0A .size =3D 2,=0A = .init_val =3D 0x0000,=0A- .res_mask =3D 0x3800,=0A- = .ro_mask =3D 0x07FF,=0A- .emu_mask =3D 0x0000,=0A+ /* = This must not be split into res_mask (0x3800) and ro_mask (0x07FF)=0A+ = * because even in permissive mode there must not be any write back=0A+ = * to this register.=0A+ */=0A+ .ro_mask =3D = 0x3FFF,=0A+ .emu_mask =3D 0xC000,=0A .init =3D = xen_pt_msixctrl_reg_init,=0A .u.w.read =3D xen_pt_word_reg_read,= =0A .u.w.write =3D xen_pt_msixctrl_reg_write,=0A--- a/qemu/upstrea= m/hw/xen/xen_pt_msi.c=0A+++ b/qemu/upstream/hw/xen/xen_pt_msi.c=0A@@ = -301,8 +301,11 @@ static int msix_set_enable(XenPCIPassthr=0A = return -1;=0A }=0A =0A- return msi_msix_enable(s, s->msix->ctrl_offs= et, PCI_MSIX_FLAGS_ENABLE,=0A- enabled);=0A+ = return xc_physdev_msix_enable(xen_xc, s->real_device.domain,=0A+ = s->real_device.bus,=0A+ = PCI_DEVFN(s->real_device.dev,=0A+ = s->real_device.func),=0A+ = enabled);=0A }=0A =0A static int xen_pt_msix_update_one(XenPCIPassthroughSt= ate *s, int entry_nr)=0A@@ -361,6 +364,11 @@ int xen_pt_msix_update(XenPCIP= assthrough=0A return 0;=0A }=0A =0A+void xen_pt_msix_enable(XenPCIPasst= hroughState *s)=0A+{=0A+ msix_set_enable(s, true);=0A+}=0A+=0A void = xen_pt_msix_disable(XenPCIPassthroughState *s)=0A {=0A int i =3D = 0;=0A@@ -378,6 +386,15 @@ void xen_pt_msix_disable(XenPCIPassthrou=0A = }=0A }=0A =0A+int xen_pt_msix_maskall(XenPCIPassthroughState *s, bool = mask)=0A+{=0A+ return xc_physdev_msix_mask_all(xen_xc, s->real_device.do= main,=0A+ s->real_device.bus,=0A+ = PCI_DEVFN(s->real_device.dev,=0A+ = s->real_device.func),=0A+ = mask);=0A+}=0A+=0A int xen_pt_msix_update_remap(XenPCIPa= ssthroughState *s, int bar_index)=0A {=0A XenPTMSIXEntry *entry;=0A --=__Part497D608A.1__= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel --=__Part497D608A.1__=--