From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40583) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0qKj-0008GV-3G for qemu-devel@nongnu.org; Fri, 05 Jun 2015 08:02:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0qKf-0004h1-S8 for qemu-devel@nongnu.org; Fri, 05 Jun 2015 08:02:45 -0400 Received: from mail.emea.novell.com ([130.57.118.101]:54638) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0qKf-0004gq-E1 for qemu-devel@nongnu.org; Fri, 05 Jun 2015 08:02:41 -0400 Message-Id: <5571AC000200007800081567@mail.emea.novell.com> Date: Fri, 05 Jun 2015 13:02:40 +0100 From: "Jan Beulich" References: <5571AA3B020000780008152E@mail.emea.novell.com> In-Reply-To: <5571AA3B020000780008152E@mail.emea.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part33071AF0.2__=" Subject: [Qemu-devel] [PATCH 3/6] xen/MSI-X: really enforce alignment List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: xen-devel , Stefano Stabellini This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part33071AF0.2__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline The way the generic infrastructure works the intention of not allowing unaligned accesses can't be achieved by simply setting .unaligned to false. The benefit is that we can now replace the conditionals in {get,set}_entry_value() by assert()-s. Signed-off-by: Jan Beulich --- a/qemu/upstream/hw/xen/xen_pt_msi.c +++ b/qemu/upstream/hw/xen/xen_pt_msi.c @@ -421,16 +421,14 @@ int xen_pt_msix_update_remap(XenPCIPasst =20 static uint32_t get_entry_value(XenPTMSIXEntry *e, int offset) { - return !(offset % sizeof(*e->latch)) - ? e->latch[offset / sizeof(*e->latch)] : 0; + assert(!(offset % sizeof(*e->latch))); + return e->latch[offset / sizeof(*e->latch)]; } =20 static void set_entry_value(XenPTMSIXEntry *e, int offset, uint32_t val) { - if (!(offset % sizeof(*e->latch))) - { - e->latch[offset / sizeof(*e->latch)] =3D val; - } + assert(!(offset % sizeof(*e->latch))); + e->latch[offset / sizeof(*e->latch)] =3D val; } =20 static void pci_msix_write(void *opaque, hwaddr addr, @@ -496,6 +494,12 @@ static uint64_t pci_msix_read(void *opaq } } =20 +static bool pci_msix_accepts(void *opaque, hwaddr addr, + unsigned size, bool is_write) +{ + return !(addr & (size - 1)); +} + static const MemoryRegionOps pci_msix_ops =3D { .read =3D pci_msix_read, .write =3D pci_msix_write, @@ -504,7 +508,13 @@ static const MemoryRegionOps pci_msix_op .min_access_size =3D 4, .max_access_size =3D 4, .unaligned =3D false, + .accepts =3D pci_msix_accepts }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false + } }; =20 int xen_pt_msix_init(XenPCIPassthroughState *s, uint32_t base) --=__Part33071AF0.2__= Content-Type: text/plain; name="qemu-MSI-X-force-align.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="qemu-MSI-X-force-align.patch" xen/MSI-X: really enforce alignment=0A=0AThe way the generic infrastructure= works the intention of not allowing=0Aunaligned accesses can't be = achieved by simply setting .unaligned to=0Afalse. The benefit is that we = can now replace the conditionals in=0A{get,set}_entry_value() by assert()-s= .=0A=0ASigned-off-by: Jan Beulich =0A=0A--- a/qemu/upstr= eam/hw/xen/xen_pt_msi.c=0A+++ b/qemu/upstream/hw/xen/xen_pt_msi.c=0A@@ = -421,16 +421,14 @@ int xen_pt_msix_update_remap(XenPCIPasst=0A =0A static = uint32_t get_entry_value(XenPTMSIXEntry *e, int offset)=0A {=0A- return = !(offset % sizeof(*e->latch))=0A- ? e->latch[offset / sizeof(*e->= latch)] : 0;=0A+ assert(!(offset % sizeof(*e->latch)));=0A+ return = e->latch[offset / sizeof(*e->latch)];=0A }=0A =0A static void set_entry_val= ue(XenPTMSIXEntry *e, int offset, uint32_t val)=0A {=0A- if (!(offset % = sizeof(*e->latch)))=0A- {=0A- e->latch[offset / sizeof(*e->latch)= ] =3D val;=0A- }=0A+ assert(!(offset % sizeof(*e->latch)));=0A+ = e->latch[offset / sizeof(*e->latch)] =3D val;=0A }=0A =0A static void = pci_msix_write(void *opaque, hwaddr addr,=0A@@ -496,6 +494,12 @@ static = uint64_t pci_msix_read(void *opaq=0A }=0A }=0A =0A+static bool = pci_msix_accepts(void *opaque, hwaddr addr,=0A+ = unsigned size, bool is_write)=0A+{=0A+ return !(addr & (size - = 1));=0A+}=0A+=0A static const MemoryRegionOps pci_msix_ops =3D {=0A = .read =3D pci_msix_read,=0A .write =3D pci_msix_write,=0A@@ -504,7 = +508,13 @@ static const MemoryRegionOps pci_msix_op=0A .min_access_= size =3D 4,=0A .max_access_size =3D 4,=0A .unaligned =3D = false,=0A+ .accepts =3D pci_msix_accepts=0A },=0A+ .impl =3D = {=0A+ .min_access_size =3D 4,=0A+ .max_access_size =3D = 4,=0A+ .unaligned =3D false=0A+ }=0A };=0A =0A int xen_pt_msix_in= it(XenPCIPassthroughState *s, uint32_t base)=0A --=__Part33071AF0.2__=-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH 3/6] xen/MSI-X: really enforce alignment Date: Fri, 05 Jun 2015 13:02:40 +0100 Message-ID: <5571AC000200007800081567@mail.emea.novell.com> References: <5571AA3B020000780008152E@mail.emea.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part33071AF0.1__=" Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Z0qKg-0008Oy-C1 for xen-devel@lists.xenproject.org; Fri, 05 Jun 2015 12:02:42 +0000 In-Reply-To: <5571AA3B020000780008152E@mail.emea.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: qemu-devel@nongnu.org Cc: xen-devel , Stefano Stabellini List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part33071AF0.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline The way the generic infrastructure works the intention of not allowing unaligned accesses can't be achieved by simply setting .unaligned to false. The benefit is that we can now replace the conditionals in {get,set}_entry_value() by assert()-s. Signed-off-by: Jan Beulich --- a/qemu/upstream/hw/xen/xen_pt_msi.c +++ b/qemu/upstream/hw/xen/xen_pt_msi.c @@ -421,16 +421,14 @@ int xen_pt_msix_update_remap(XenPCIPasst =20 static uint32_t get_entry_value(XenPTMSIXEntry *e, int offset) { - return !(offset % sizeof(*e->latch)) - ? e->latch[offset / sizeof(*e->latch)] : 0; + assert(!(offset % sizeof(*e->latch))); + return e->latch[offset / sizeof(*e->latch)]; } =20 static void set_entry_value(XenPTMSIXEntry *e, int offset, uint32_t val) { - if (!(offset % sizeof(*e->latch))) - { - e->latch[offset / sizeof(*e->latch)] =3D val; - } + assert(!(offset % sizeof(*e->latch))); + e->latch[offset / sizeof(*e->latch)] =3D val; } =20 static void pci_msix_write(void *opaque, hwaddr addr, @@ -496,6 +494,12 @@ static uint64_t pci_msix_read(void *opaq } } =20 +static bool pci_msix_accepts(void *opaque, hwaddr addr, + unsigned size, bool is_write) +{ + return !(addr & (size - 1)); +} + static const MemoryRegionOps pci_msix_ops =3D { .read =3D pci_msix_read, .write =3D pci_msix_write, @@ -504,7 +508,13 @@ static const MemoryRegionOps pci_msix_op .min_access_size =3D 4, .max_access_size =3D 4, .unaligned =3D false, + .accepts =3D pci_msix_accepts }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false + } }; =20 int xen_pt_msix_init(XenPCIPassthroughState *s, uint32_t base) --=__Part33071AF0.1__= Content-Type: text/plain; name="qemu-MSI-X-force-align.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="qemu-MSI-X-force-align.patch" xen/MSI-X: really enforce alignment=0A=0AThe way the generic infrastructure= works the intention of not allowing=0Aunaligned accesses can't be = achieved by simply setting .unaligned to=0Afalse. The benefit is that we = can now replace the conditionals in=0A{get,set}_entry_value() by assert()-s= .=0A=0ASigned-off-by: Jan Beulich =0A=0A--- a/qemu/upstr= eam/hw/xen/xen_pt_msi.c=0A+++ b/qemu/upstream/hw/xen/xen_pt_msi.c=0A@@ = -421,16 +421,14 @@ int xen_pt_msix_update_remap(XenPCIPasst=0A =0A static = uint32_t get_entry_value(XenPTMSIXEntry *e, int offset)=0A {=0A- return = !(offset % sizeof(*e->latch))=0A- ? e->latch[offset / sizeof(*e->= latch)] : 0;=0A+ assert(!(offset % sizeof(*e->latch)));=0A+ return = e->latch[offset / sizeof(*e->latch)];=0A }=0A =0A static void set_entry_val= ue(XenPTMSIXEntry *e, int offset, uint32_t val)=0A {=0A- if (!(offset % = sizeof(*e->latch)))=0A- {=0A- e->latch[offset / sizeof(*e->latch)= ] =3D val;=0A- }=0A+ assert(!(offset % sizeof(*e->latch)));=0A+ = e->latch[offset / sizeof(*e->latch)] =3D val;=0A }=0A =0A static void = pci_msix_write(void *opaque, hwaddr addr,=0A@@ -496,6 +494,12 @@ static = uint64_t pci_msix_read(void *opaq=0A }=0A }=0A =0A+static bool = pci_msix_accepts(void *opaque, hwaddr addr,=0A+ = unsigned size, bool is_write)=0A+{=0A+ return !(addr & (size - = 1));=0A+}=0A+=0A static const MemoryRegionOps pci_msix_ops =3D {=0A = .read =3D pci_msix_read,=0A .write =3D pci_msix_write,=0A@@ -504,7 = +508,13 @@ static const MemoryRegionOps pci_msix_op=0A .min_access_= size =3D 4,=0A .max_access_size =3D 4,=0A .unaligned =3D = false,=0A+ .accepts =3D pci_msix_accepts=0A },=0A+ .impl =3D = {=0A+ .min_access_size =3D 4,=0A+ .max_access_size =3D = 4,=0A+ .unaligned =3D false=0A+ }=0A };=0A =0A int xen_pt_msix_in= it(XenPCIPassthroughState *s, uint32_t base)=0A --=__Part33071AF0.1__= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel --=__Part33071AF0.1__=--