* [PATCH] arm64: dts: add device tree for ARM SMM-A53x2 on LogicTile Express 20MG
@ 2015-06-09 15:38 Kristina Martsenko
2015-06-10 8:58 ` Liviu Dudau
0 siblings, 1 reply; 9+ messages in thread
From: Kristina Martsenko @ 2015-06-09 15:38 UTC (permalink / raw
To: linux-arm-kernel
Add a DTS file for the MP2 Cortex-A53 Soft Macrocell Model implemented
on a LogicTile Express 20MG (V2F-1XV7) daughterboard. This is based on
the version that's currently available from the ARM DTS repository [1].
[1] git://linux-arm.org/arm-dts.git
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
---
MAINTAINERS | 1 +
arch/arm64/boot/dts/arm/Makefile | 1 +
.../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 196 +++++++++++++++++++++
3 files changed, 198 insertions(+)
create mode 100644 arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
diff --git a/MAINTAINERS b/MAINTAINERS
index 9180f46..1fb07e0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1613,6 +1613,7 @@ M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/boot/dts/vexpress*
+F: arch/arm64/boot/dts/arm/vexpress*
F: arch/arm/mach-vexpress/
F: */*/vexpress*
F: */*/*/vexpress*
diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
index c5c98b9..bb3c072 100644
--- a/arch/arm64/boot/dts/arm/Makefile
+++ b/arch/arm64/boot/dts/arm/Makefile
@@ -1,6 +1,7 @@
dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
new file mode 100644
index 0000000..bbe28aa
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
@@ -0,0 +1,196 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * LogicTile Express 20MG
+ * V2F-1XV7
+ *
+ * Cortex-A53 (2 cores) Soft Macrocell Model
+ *
+ * HBI-0247C
+ */
+
+/dts-v1/;
+
+/* In use by spinning secondaries */
+/memreserve/ 0x80000000 0x00010000;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "V2F-1XV7 Cortex-A53x2 SMM";
+ arm,hbi = <0x247>;
+ arm,vexpress,site = <0xf>;
+ compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen {
+ stdout-path = "serial0:38400n8";
+ };
+
+ aliases {
+ serial0 = &v2m_serial0;
+ serial1 = &v2m_serial1;
+ serial2 = &v2m_serial2;
+ serial3 = &v2m_serial3;
+ i2c0 = &v2m_i2c_dvi;
+ i2c1 = &v2m_i2c_pcie;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x8000fff8>;
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
+ };
+
+ gic: interrupt-controller at 2c001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0x2c001000 0 0x1000>,
+ <0 0x2c002000 0 0x2000>,
+ <0 0x2c004000 0 0x2000>,
+ <0 0x2c006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dcc {
+ compatible = "arm,vexpress,config-bus";
+ arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+ smbclk: osc at 4 {
+ /* SMC clock */
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 4>;
+ freq-range = <40000000 40000000>;
+ #clock-cells = <0>;
+ clock-output-names = "smclk";
+ };
+
+ volt at 0 {
+ /* VIO to expansion board above */
+ compatible = "arm,vexpress-volt";
+ arm,vexpress-sysreg,func = <2 0>;
+ regulator-name = "VIO_UP";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ volt at 1 {
+ /* 12V from power connector J6 */
+ compatible = "arm,vexpress-volt";
+ arm,vexpress-sysreg,func = <2 1>;
+ regulator-name = "12";
+ regulator-always-on;
+ };
+
+ temp at 0 {
+ /* FPGA temperature */
+ compatible = "arm,vexpress-temp";
+ arm,vexpress-sysreg,func = <4 0>;
+ label = "FPGA";
+ };
+ };
+
+ smb {
+ compatible = "simple-bus";
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0x08000000 0x04000000>,
+ <1 0 0 0x14000000 0x04000000>,
+ <2 0 0 0x18000000 0x04000000>,
+ <3 0 0 0x1c000000 0x04000000>,
+ <4 0 0 0x0c000000 0x04000000>,
+ <5 0 0 0x10000000 0x04000000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 63>;
+ interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+
+ /include/ "../../../../arm/boot/dts/vexpress-v2m-rs1.dtsi"
+ };
+};
--
2.1.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH] arm64: dts: add device tree for ARM SMM-A53x2 on LogicTile Express 20MG
2015-06-09 15:38 [PATCH] arm64: dts: add device tree for ARM SMM-A53x2 on LogicTile Express 20MG Kristina Martsenko
@ 2015-06-10 8:58 ` Liviu Dudau
2015-06-10 9:12 ` Mark Rutland
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Liviu Dudau @ 2015-06-10 8:58 UTC (permalink / raw
To: linux-arm-kernel
Hi Kristina,
On Tue, Jun 09, 2015 at 04:38:31PM +0100, Kristina Martsenko wrote:
> Add a DTS file for the MP2 Cortex-A53 Soft Macrocell Model implemented
> on a LogicTile Express 20MG (V2F-1XV7) daughterboard. This is based on
> the version that's currently available from the ARM DTS repository [1].
>
> [1] git://linux-arm.org/arm-dts.git
I thought the plan was to keep new DTs in this repository, not to add
them into the kernel. Has this changed?
>
> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
> ---
> MAINTAINERS | 1 +
> arch/arm64/boot/dts/arm/Makefile | 1 +
> .../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 196 +++++++++++++++++++++
> 3 files changed, 198 insertions(+)
> create mode 100644 arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9180f46..1fb07e0 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1613,6 +1613,7 @@ M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
> S: Maintained
> F: arch/arm/boot/dts/vexpress*
> +F: arch/arm64/boot/dts/arm/vexpress*
> F: arch/arm/mach-vexpress/
> F: */*/vexpress*
> F: */*/*/vexpress*
You might want to Cc Lorenzo on this patch if you add him as maintainer :)
> diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
> index c5c98b9..bb3c072 100644
> --- a/arch/arm64/boot/dts/arm/Makefile
> +++ b/arch/arm64/boot/dts/arm/Makefile
> @@ -1,6 +1,7 @@
> dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb
> dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb
> dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
> +dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
>
> always := $(dtb-y)
> subdir-y := $(dts-dirs)
> diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
> new file mode 100644
> index 0000000..bbe28aa
> --- /dev/null
> +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
> @@ -0,0 +1,196 @@
> +/*
> + * ARM Ltd. Versatile Express
> + *
> + * LogicTile Express 20MG
> + * V2F-1XV7
> + *
> + * Cortex-A53 (2 cores) Soft Macrocell Model
> + *
> + * HBI-0247C
> + */
> +
> +/dts-v1/;
> +
> +/* In use by spinning secondaries */
> +/memreserve/ 0x80000000 0x00010000;
Where does the kernel get loaded to? If 0x80000000 is the start of memory and the kernel is
loaded at 0x80000 offset as usual, then that memory is protected anyway.
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + model = "V2F-1XV7 Cortex-A53x2 SMM";
> + arm,hbi = <0x247>;
> + arm,vexpress,site = <0xf>;
> + compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen {
> + stdout-path = "serial0:38400n8";
> + };
> +
> + aliases {
> + serial0 = &v2m_serial0;
> + serial1 = &v2m_serial1;
> + serial2 = &v2m_serial2;
> + serial3 = &v2m_serial3;
> + i2c0 = &v2m_i2c_dvi;
> + i2c1 = &v2m_i2c_pcie;
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0 0>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0 1>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0x0 0x8000fff8>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + L2_0: l2-cache0 {
> + compatible = "cache";
> + };
> + };
> +
> + memory at 80000000 {
> + device_type = "memory";
> + reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
> + };
> +
> + gic: interrupt-controller at 2c001000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0 0x2c001000 0 0x1000>,
> + <0 0x2c002000 0 0x2000>,
> + <0 0x2c004000 0 0x2000>,
> + <0 0x2c006000 0 0x2000>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + dcc {
> + compatible = "arm,vexpress,config-bus";
> + arm,vexpress,config-bridge = <&v2m_sysreg>;
> +
> + smbclk: osc at 4 {
> + /* SMC clock */
> + compatible = "arm,vexpress-osc";
> + arm,vexpress-sysreg,func = <1 4>;
> + freq-range = <40000000 40000000>;
> + #clock-cells = <0>;
> + clock-output-names = "smclk";
> + };
> +
> + volt at 0 {
> + /* VIO to expansion board above */
> + compatible = "arm,vexpress-volt";
> + arm,vexpress-sysreg,func = <2 0>;
> + regulator-name = "VIO_UP";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + volt at 1 {
> + /* 12V from power connector J6 */
> + compatible = "arm,vexpress-volt";
> + arm,vexpress-sysreg,func = <2 1>;
> + regulator-name = "12";
> + regulator-always-on;
> + };
> +
> + temp at 0 {
> + /* FPGA temperature */
> + compatible = "arm,vexpress-temp";
> + arm,vexpress-sysreg,func = <4 0>;
> + label = "FPGA";
> + };
> + };
> +
> + smb {
> + compatible = "simple-bus";
> +
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0x08000000 0x04000000>,
> + <1 0 0 0x14000000 0x04000000>,
> + <2 0 0 0x18000000 0x04000000>,
> + <3 0 0 0x1c000000 0x04000000>,
> + <4 0 0 0x0c000000 0x04000000>,
> + <5 0 0 0x10000000 0x04000000>;
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 63>;
> + interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> +
> + /include/ "../../../../arm/boot/dts/vexpress-v2m-rs1.dtsi"
Patch looks OK to me even if I'm not too keen on including DTSi files from
a "different" arch directory.
Best regards,
Liviu
> + };
> +};
> --
> 2.1.4
>
--
====================
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
?\_(?)_/?
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH] arm64: dts: add device tree for ARM SMM-A53x2 on LogicTile Express 20MG
2015-06-10 8:58 ` Liviu Dudau
@ 2015-06-10 9:12 ` Mark Rutland
2015-06-10 9:27 ` Liviu Dudau
2015-06-10 9:20 ` Marc Zyngier
2015-06-11 14:12 ` Kristina Martsenko
2 siblings, 1 reply; 9+ messages in thread
From: Mark Rutland @ 2015-06-10 9:12 UTC (permalink / raw
To: linux-arm-kernel
On Wed, Jun 10, 2015 at 09:58:25AM +0100, Liviu Dudau wrote:
> Hi Kristina,
>
> On Tue, Jun 09, 2015 at 04:38:31PM +0100, Kristina Martsenko wrote:
> > Add a DTS file for the MP2 Cortex-A53 Soft Macrocell Model implemented
> > on a LogicTile Express 20MG (V2F-1XV7) daughterboard. This is based on
> > the version that's currently available from the ARM DTS repository [1].
> >
> > [1] git://linux-arm.org/arm-dts.git
>
> I thought the plan was to keep new DTs in this repository, not to add
> them into the kernel. Has this changed?
>
> >
> > Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
> > ---
> > MAINTAINERS | 1 +
> > arch/arm64/boot/dts/arm/Makefile | 1 +
> > .../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 196 +++++++++++++++++++++
> > 3 files changed, 198 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 9180f46..1fb07e0 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -1613,6 +1613,7 @@ M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
> > S: Maintained
> > F: arch/arm/boot/dts/vexpress*
> > +F: arch/arm64/boot/dts/arm/vexpress*
> > F: arch/arm/mach-vexpress/
> > F: */*/vexpress*
> > F: */*/*/vexpress*
>
> You might want to Cc Lorenzo on this patch if you add him as maintainer :)
>
> > diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
> > index c5c98b9..bb3c072 100644
> > --- a/arch/arm64/boot/dts/arm/Makefile
> > +++ b/arch/arm64/boot/dts/arm/Makefile
> > @@ -1,6 +1,7 @@
> > dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb
> > dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb
> > dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
> > +dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
> >
> > always := $(dtb-y)
> > subdir-y := $(dts-dirs)
> > diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
> > new file mode 100644
> > index 0000000..bbe28aa
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
> > @@ -0,0 +1,196 @@
> > +/*
> > + * ARM Ltd. Versatile Express
> > + *
> > + * LogicTile Express 20MG
> > + * V2F-1XV7
> > + *
> > + * Cortex-A53 (2 cores) Soft Macrocell Model
> > + *
> > + * HBI-0247C
> > + */
> > +
> > +/dts-v1/;
> > +
> > +/* In use by spinning secondaries */
> > +/memreserve/ 0x80000000 0x00010000;
>
> Where does the kernel get loaded to? If 0x80000000 is the start of memory and the kernel is
> loaded at 0x80000 offset as usual, then that memory is protected anyway.
That's simply not true. The kernel may use _any_ memory which is
described to it and not explicitly reserved.
We only reserve the kernel's static image (see arm64_memblock_init),
which does not cover that region. We can easily map that memory and
allocate it to something.
While we used to place page tables in the end of that region, we only
reserved the page tables, and it was problematic because you had no idea
how much of that memory the kernel might use.
Regardless, DTs should not rely on Linux implementation details like
magic implicit reservations.
Mark.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH] arm64: dts: add device tree for ARM SMM-A53x2 on LogicTile Express 20MG
2015-06-10 8:58 ` Liviu Dudau
2015-06-10 9:12 ` Mark Rutland
@ 2015-06-10 9:20 ` Marc Zyngier
2015-06-11 14:12 ` Kristina Martsenko
2 siblings, 0 replies; 9+ messages in thread
From: Marc Zyngier @ 2015-06-10 9:20 UTC (permalink / raw
To: linux-arm-kernel
Hi Liviu,
On 10/06/15 09:58, Liviu Dudau wrote:
> Hi Kristina,
>
> On Tue, Jun 09, 2015 at 04:38:31PM +0100, Kristina Martsenko wrote:
>> Add a DTS file for the MP2 Cortex-A53 Soft Macrocell Model implemented
>> on a LogicTile Express 20MG (V2F-1XV7) daughterboard. This is based on
>> the version that's currently available from the ARM DTS repository [1].
>>
>> [1] git://linux-arm.org/arm-dts.git
[...]
>> +
>> + /include/ "../../../../arm/boot/dts/vexpress-v2m-rs1.dtsi"
>
> Patch looks OK to me even if I'm not too keen on including DTSi files from
> a "different" arch directory.
Well, we do that for the code as well (see how KVM is build on all
architectures). I agree that this is not very nice, but so far the
alternative (symbolic links) is a lot worse.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH] arm64: dts: add device tree for ARM SMM-A53x2 on LogicTile Express 20MG
2015-06-10 9:12 ` Mark Rutland
@ 2015-06-10 9:27 ` Liviu Dudau
2015-06-10 9:39 ` Mark Rutland
0 siblings, 1 reply; 9+ messages in thread
From: Liviu Dudau @ 2015-06-10 9:27 UTC (permalink / raw
To: linux-arm-kernel
On Wed, Jun 10, 2015 at 10:12:34AM +0100, Mark Rutland wrote:
> On Wed, Jun 10, 2015 at 09:58:25AM +0100, Liviu Dudau wrote:
> > Hi Kristina,
> >
> > On Tue, Jun 09, 2015 at 04:38:31PM +0100, Kristina Martsenko wrote:
> > > Add a DTS file for the MP2 Cortex-A53 Soft Macrocell Model implemented
> > > on a LogicTile Express 20MG (V2F-1XV7) daughterboard. This is based on
> > > the version that's currently available from the ARM DTS repository [1].
> > >
> > > [1] git://linux-arm.org/arm-dts.git
> >
> > I thought the plan was to keep new DTs in this repository, not to add
> > them into the kernel. Has this changed?
> >
> > >
> > > Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
> > > ---
> > > MAINTAINERS | 1 +
> > > arch/arm64/boot/dts/arm/Makefile | 1 +
> > > .../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 196 +++++++++++++++++++++
> > > 3 files changed, 198 insertions(+)
> > > create mode 100644 arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
> > >
> > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > index 9180f46..1fb07e0 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -1613,6 +1613,7 @@ M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > > L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
> > > S: Maintained
> > > F: arch/arm/boot/dts/vexpress*
> > > +F: arch/arm64/boot/dts/arm/vexpress*
> > > F: arch/arm/mach-vexpress/
> > > F: */*/vexpress*
> > > F: */*/*/vexpress*
> >
> > You might want to Cc Lorenzo on this patch if you add him as maintainer :)
> >
> > > diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
> > > index c5c98b9..bb3c072 100644
> > > --- a/arch/arm64/boot/dts/arm/Makefile
> > > +++ b/arch/arm64/boot/dts/arm/Makefile
> > > @@ -1,6 +1,7 @@
> > > dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb
> > > dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb
> > > dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
> > > +dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
> > >
> > > always := $(dtb-y)
> > > subdir-y := $(dts-dirs)
> > > diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
> > > new file mode 100644
> > > index 0000000..bbe28aa
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
> > > @@ -0,0 +1,196 @@
> > > +/*
> > > + * ARM Ltd. Versatile Express
> > > + *
> > > + * LogicTile Express 20MG
> > > + * V2F-1XV7
> > > + *
> > > + * Cortex-A53 (2 cores) Soft Macrocell Model
> > > + *
> > > + * HBI-0247C
> > > + */
> > > +
> > > +/dts-v1/;
> > > +
> > > +/* In use by spinning secondaries */
> > > +/memreserve/ 0x80000000 0x00010000;
> >
> > Where does the kernel get loaded to? If 0x80000000 is the start of memory and the kernel is
> > loaded at 0x80000 offset as usual, then that memory is protected anyway.
>
> That's simply not true. The kernel may use _any_ memory which is
> described to it and not explicitly reserved.
>
> We only reserve the kernel's static image (see arm64_memblock_init),
> which does not cover that region. We can easily map that memory and
> allocate it to something.
>
> While we used to place page tables in the end of that region, we only
> reserved the page tables, and it was problematic because you had no idea
> how much of that memory the kernel might use.
>
> Regardless, DTs should not rely on Linux implementation details like
> magic implicit reservations.
Things might have changed since v3.18 but I remember having a hell of a time trying to
access memory that was at the bottom of address space before the kernel start image.
But I agree that things should be explicitly stated in the DT.
Question for Kristina now: why spin method and not PSCI for this CoreTile?
Best regards,
Liviu
>
> Mark.
>
--
====================
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
?\_(?)_/?
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH] arm64: dts: add device tree for ARM SMM-A53x2 on LogicTile Express 20MG
2015-06-10 9:27 ` Liviu Dudau
@ 2015-06-10 9:39 ` Mark Rutland
2015-06-10 9:59 ` Pawel Moll
0 siblings, 1 reply; 9+ messages in thread
From: Mark Rutland @ 2015-06-10 9:39 UTC (permalink / raw
To: linux-arm-kernel
> > > > +/* In use by spinning secondaries */
> > > > +/memreserve/ 0x80000000 0x00010000;
> > >
> > > Where does the kernel get loaded to? If 0x80000000 is the start of memory and the kernel is
> > > loaded at 0x80000 offset as usual, then that memory is protected anyway.
> >
> > That's simply not true. The kernel may use _any_ memory which is
> > described to it and not explicitly reserved.
> >
> > We only reserve the kernel's static image (see arm64_memblock_init),
> > which does not cover that region. We can easily map that memory and
> > allocate it to something.
> >
> > While we used to place page tables in the end of that region, we only
> > reserved the page tables, and it was problematic because you had no idea
> > how much of that memory the kernel might use.
> >
> > Regardless, DTs should not rely on Linux implementation details like
> > magic implicit reservations.
>
> Things might have changed since v3.18 but I remember having a hell of a time trying to
> access memory that was at the bottom of address space before the kernel start image.
Memory more than 0x80000 bytes below the kernel wouldn't have been
mapped because of the way the linear map is built, which might have been
your issue. This is an implementation detail which _will_ change (see
Ard's patches) and should not be relied upon.
> But I agree that things should be explicitly stated in the DT.
>
> Question for Kristina now: why spin method and not PSCI for this CoreTile?
Unfortunately the boot monitor only ever implemented spin-table. If
you're offering to port and maintain ARM Trusted Firmware, we can look
at having the DT report PSCI. ;)
Ideally we'd avoid placing the enable-method in the DTS at all, but I
believe the boot monitor isn't smart enough to fix that up.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH] arm64: dts: add device tree for ARM SMM-A53x2 on LogicTile Express 20MG
2015-06-10 9:39 ` Mark Rutland
@ 2015-06-10 9:59 ` Pawel Moll
2015-06-10 10:11 ` Mark Rutland
0 siblings, 1 reply; 9+ messages in thread
From: Pawel Moll @ 2015-06-10 9:59 UTC (permalink / raw
To: linux-arm-kernel
On Wed, 2015-06-10 at 10:39 +0100, Mark Rutland wrote:
> Ideally we'd avoid placing the enable-method in the DTS at all, but I
> believe the boot monitor isn't smart enough to fix that up.
You would be surprised how intelligent these animals can be :-P
8<--------------
case CPU:
err = safdt_insert_prop(safdt, "enable-method",
"spin-table", 11);
if (err)
break;
addr = fdt_uint64(parser->cpu_release_addr);
err = safdt_insert_prop(safdt, "cpu-release-addr", &addr, 8);
8<---------------
Pawe?
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH] arm64: dts: add device tree for ARM SMM-A53x2 on LogicTile Express 20MG
2015-06-10 9:59 ` Pawel Moll
@ 2015-06-10 10:11 ` Mark Rutland
0 siblings, 0 replies; 9+ messages in thread
From: Mark Rutland @ 2015-06-10 10:11 UTC (permalink / raw
To: linux-arm-kernel
On Wed, Jun 10, 2015 at 10:59:20AM +0100, Pawel Moll wrote:
> On Wed, 2015-06-10 at 10:39 +0100, Mark Rutland wrote:
> > Ideally we'd avoid placing the enable-method in the DTS at all, but I
> > believe the boot monitor isn't smart enough to fix that up.
>
> You would be surprised how intelligent these animals can be :-P
>
> 8<--------------
> case CPU:
> err = safdt_insert_prop(safdt, "enable-method",
> "spin-table", 11);
> if (err)
> break;
> addr = fdt_uint64(parser->cpu_release_addr);
> err = safdt_insert_prop(safdt, "cpu-release-addr", &addr, 8);
> 8<---------------
Sounds like we can get rid of the enable-method and cpu-release-addr
then.
Mark.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH] arm64: dts: add device tree for ARM SMM-A53x2 on LogicTile Express 20MG
2015-06-10 8:58 ` Liviu Dudau
2015-06-10 9:12 ` Mark Rutland
2015-06-10 9:20 ` Marc Zyngier
@ 2015-06-11 14:12 ` Kristina Martsenko
2 siblings, 0 replies; 9+ messages in thread
From: Kristina Martsenko @ 2015-06-11 14:12 UTC (permalink / raw
To: linux-arm-kernel
Hi Liviu,
On 10/06/15 09:58, Liviu Dudau wrote:
> Hi Kristina,
>
> On Tue, Jun 09, 2015 at 04:38:31PM +0100, Kristina Martsenko wrote:
>> Add a DTS file for the MP2 Cortex-A53 Soft Macrocell Model implemented
>> on a LogicTile Express 20MG (V2F-1XV7) daughterboard. This is based on
>> the version that's currently available from the ARM DTS repository [1].
>>
>> [1] git://linux-arm.org/arm-dts.git
>
> I thought the plan was to keep new DTs in this repository, not to add
> them into the kernel. Has this changed?
There doesn't seem to be a plan, and all new DTs are being merged into
the kernel. So for the time being it's better to have this one in the
kernel as well.
Thanks for the review, I'll send a v2.
Kristina
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2015-06-11 14:12 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-06-09 15:38 [PATCH] arm64: dts: add device tree for ARM SMM-A53x2 on LogicTile Express 20MG Kristina Martsenko
2015-06-10 8:58 ` Liviu Dudau
2015-06-10 9:12 ` Mark Rutland
2015-06-10 9:27 ` Liviu Dudau
2015-06-10 9:39 ` Mark Rutland
2015-06-10 9:59 ` Pawel Moll
2015-06-10 10:11 ` Mark Rutland
2015-06-10 9:20 ` Marc Zyngier
2015-06-11 14:12 ` Kristina Martsenko
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