From mboxrd@z Thu Jan 1 00:00:00 1970 From: marc.zyngier@arm.com (Marc Zyngier) Date: Wed, 17 Jun 2015 13:39:39 +0100 Subject: [PATCH 04/10] KVM: arm/arm64: vgic: Allow HW irq to be encoded in LR In-Reply-To: <55815FA5.4010203@linaro.org> References: <1433783045-8002-1-git-send-email-marc.zyngier@arm.com> <1433783045-8002-5-git-send-email-marc.zyngier@arm.com> <55815FA5.4010203@linaro.org> Message-ID: <55816A8B.3070803@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 17/06/15 12:53, Eric Auger wrote: > On 06/08/2015 07:03 PM, Marc Zyngier wrote: >> Now that struct vgic_lr supports the LR_HW bit and carries a hwirq >> field, we can encode that information into the list registers. >> >> This patch provides implementations for both GICv2 and GICv3. >> >> Signed-off-by: Marc Zyngier >> --- >> include/linux/irqchip/arm-gic-v3.h | 3 +++ >> include/linux/irqchip/arm-gic.h | 3 ++- >> virt/kvm/arm/vgic-v2.c | 16 +++++++++++++++- >> virt/kvm/arm/vgic-v3.c | 21 ++++++++++++++++++--- >> 4 files changed, 38 insertions(+), 5 deletions(-) >> >> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h >> index ffbc034..cf637d6 100644 >> --- a/include/linux/irqchip/arm-gic-v3.h >> +++ b/include/linux/irqchip/arm-gic-v3.h >> @@ -268,9 +268,12 @@ >> >> #define ICH_LR_EOI (1UL << 41) >> #define ICH_LR_GROUP (1UL << 60) >> +#define ICH_LR_HW (1UL << 61) >> #define ICH_LR_STATE (3UL << 62) >> #define ICH_LR_PENDING_BIT (1UL << 62) >> #define ICH_LR_ACTIVE_BIT (1UL << 63) >> +#define ICH_LR_PHYS_ID_SHIFT 32 >> +#define ICH_LR_PHYS_ID_MASK (0x3ffUL << ICH_LR_PHYS_ID_SHIFT) >> >> #define ICH_MISR_EOI (1 << 0) >> #define ICH_MISR_U (1 << 1) >> diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h >> index 9de976b..ca88dad 100644 >> --- a/include/linux/irqchip/arm-gic.h >> +++ b/include/linux/irqchip/arm-gic.h >> @@ -71,11 +71,12 @@ >> >> #define GICH_LR_VIRTUALID (0x3ff << 0) >> #define GICH_LR_PHYSID_CPUID_SHIFT (10) >> -#define GICH_LR_PHYSID_CPUID (7 << GICH_LR_PHYSID_CPUID_SHIFT) >> +#define GICH_LR_PHYSID_CPUID (0x3ff << GICH_LR_PHYSID_CPUID_SHIFT) >> #define GICH_LR_STATE (3 << 28) >> #define GICH_LR_PENDING_BIT (1 << 28) >> #define GICH_LR_ACTIVE_BIT (1 << 29) >> #define GICH_LR_EOI (1 << 19) >> +#define GICH_LR_HW (1 << 31) >> >> #define GICH_VMCR_CTRL_SHIFT 0 >> #define GICH_VMCR_CTRL_MASK (0x21f << GICH_VMCR_CTRL_SHIFT) >> diff --git a/virt/kvm/arm/vgic-v2.c b/virt/kvm/arm/vgic-v2.c >> index f9b9c7c..8d7b04d 100644 >> --- a/virt/kvm/arm/vgic-v2.c >> +++ b/virt/kvm/arm/vgic-v2.c >> @@ -48,6 +48,10 @@ static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr) >> lr_desc.state |= LR_STATE_ACTIVE; >> if (val & GICH_LR_EOI) >> lr_desc.state |= LR_EOI_INT; >> + if (val & GICH_LR_HW) { >> + lr_desc.state |= LR_HW; >> + lr_desc.hwirq = (val & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT; >> + } >> >> return lr_desc; >> } >> @@ -55,7 +59,9 @@ static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr) >> static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr, >> struct vgic_lr lr_desc) >> { >> - u32 lr_val = (lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT) | lr_desc.irq; >> + u32 lr_val; >> + >> + lr_val = lr_desc.irq; >> >> if (lr_desc.state & LR_STATE_PENDING) >> lr_val |= GICH_LR_PENDING_BIT; >> @@ -64,6 +70,14 @@ static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr, >> if (lr_desc.state & LR_EOI_INT) >> lr_val |= GICH_LR_EOI; >> >> + if (lr_desc.state & LR_HW) { >> + lr_val |= GICH_LR_HW; >> + lr_val |= (u32)lr_desc.hwirq << GICH_LR_PHYSID_CPUID_SHIFT; > > shouldn't we test somewhere that the hwirq is between 16 and 1019. Else > behavior is unpredictable according to v2 spec. when queuing into the LR > we currently check the linux irq vlr.irq >= VGIC_NR_SGIS if I am not wrong. This is actually implicit. vgic_map_phys_irq() takes a parameter (irq) that is the Linux view of the hwirq we're dealing with (we fetch this hwirq by traversing the irq_data list associated with irq). SGIs are not part of the set of interrupts that can be mapped to a Linux irq (their usage is completely private to the two GIC drivers). Note that GICv3 allows SGIs to be set as a physical interrupt in an LR though, but this is not a feature we use so far. > besides Reviewed-by: Eric Auger Thanks! M. -- Jazz is not dead. It just smells funny... From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Subject: Re: [PATCH 04/10] KVM: arm/arm64: vgic: Allow HW irq to be encoded in LR Date: Wed, 17 Jun 2015 13:39:39 +0100 Message-ID: <55816A8B.3070803@arm.com> References: <1433783045-8002-1-git-send-email-marc.zyngier@arm.com> <1433783045-8002-5-git-send-email-marc.zyngier@arm.com> <55815FA5.4010203@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <55815FA5.4010203@linaro.org> Sender: kvm-owner@vger.kernel.org To: Eric Auger , "kvm@vger.kernel.org" , "kvmarm@lists.cs.columbia.edu" , "linux-arm-kernel@lists.infradead.org" Cc: Christoffer Dall , =?windows-1252?Q?Alex?= =?windows-1252?Q?_Benn=E9e?= , Andre Przywara List-Id: kvmarm@lists.cs.columbia.edu On 17/06/15 12:53, Eric Auger wrote: > On 06/08/2015 07:03 PM, Marc Zyngier wrote: >> Now that struct vgic_lr supports the LR_HW bit and carries a hwirq >> field, we can encode that information into the list registers. >> >> This patch provides implementations for both GICv2 and GICv3. >> >> Signed-off-by: Marc Zyngier >> --- >> include/linux/irqchip/arm-gic-v3.h | 3 +++ >> include/linux/irqchip/arm-gic.h | 3 ++- >> virt/kvm/arm/vgic-v2.c | 16 +++++++++++++++- >> virt/kvm/arm/vgic-v3.c | 21 ++++++++++++++++++--- >> 4 files changed, 38 insertions(+), 5 deletions(-) >> >> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h >> index ffbc034..cf637d6 100644 >> --- a/include/linux/irqchip/arm-gic-v3.h >> +++ b/include/linux/irqchip/arm-gic-v3.h >> @@ -268,9 +268,12 @@ >> >> #define ICH_LR_EOI (1UL << 41) >> #define ICH_LR_GROUP (1UL << 60) >> +#define ICH_LR_HW (1UL << 61) >> #define ICH_LR_STATE (3UL << 62) >> #define ICH_LR_PENDING_BIT (1UL << 62) >> #define ICH_LR_ACTIVE_BIT (1UL << 63) >> +#define ICH_LR_PHYS_ID_SHIFT 32 >> +#define ICH_LR_PHYS_ID_MASK (0x3ffUL << ICH_LR_PHYS_ID_SHIFT) >> >> #define ICH_MISR_EOI (1 << 0) >> #define ICH_MISR_U (1 << 1) >> diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h >> index 9de976b..ca88dad 100644 >> --- a/include/linux/irqchip/arm-gic.h >> +++ b/include/linux/irqchip/arm-gic.h >> @@ -71,11 +71,12 @@ >> >> #define GICH_LR_VIRTUALID (0x3ff << 0) >> #define GICH_LR_PHYSID_CPUID_SHIFT (10) >> -#define GICH_LR_PHYSID_CPUID (7 << GICH_LR_PHYSID_CPUID_SHIFT) >> +#define GICH_LR_PHYSID_CPUID (0x3ff << GICH_LR_PHYSID_CPUID_SHIFT) >> #define GICH_LR_STATE (3 << 28) >> #define GICH_LR_PENDING_BIT (1 << 28) >> #define GICH_LR_ACTIVE_BIT (1 << 29) >> #define GICH_LR_EOI (1 << 19) >> +#define GICH_LR_HW (1 << 31) >> >> #define GICH_VMCR_CTRL_SHIFT 0 >> #define GICH_VMCR_CTRL_MASK (0x21f << GICH_VMCR_CTRL_SHIFT) >> diff --git a/virt/kvm/arm/vgic-v2.c b/virt/kvm/arm/vgic-v2.c >> index f9b9c7c..8d7b04d 100644 >> --- a/virt/kvm/arm/vgic-v2.c >> +++ b/virt/kvm/arm/vgic-v2.c >> @@ -48,6 +48,10 @@ static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr) >> lr_desc.state |= LR_STATE_ACTIVE; >> if (val & GICH_LR_EOI) >> lr_desc.state |= LR_EOI_INT; >> + if (val & GICH_LR_HW) { >> + lr_desc.state |= LR_HW; >> + lr_desc.hwirq = (val & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT; >> + } >> >> return lr_desc; >> } >> @@ -55,7 +59,9 @@ static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr) >> static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr, >> struct vgic_lr lr_desc) >> { >> - u32 lr_val = (lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT) | lr_desc.irq; >> + u32 lr_val; >> + >> + lr_val = lr_desc.irq; >> >> if (lr_desc.state & LR_STATE_PENDING) >> lr_val |= GICH_LR_PENDING_BIT; >> @@ -64,6 +70,14 @@ static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr, >> if (lr_desc.state & LR_EOI_INT) >> lr_val |= GICH_LR_EOI; >> >> + if (lr_desc.state & LR_HW) { >> + lr_val |= GICH_LR_HW; >> + lr_val |= (u32)lr_desc.hwirq << GICH_LR_PHYSID_CPUID_SHIFT; > > shouldn't we test somewhere that the hwirq is between 16 and 1019. Else > behavior is unpredictable according to v2 spec. when queuing into the LR > we currently check the linux irq vlr.irq >= VGIC_NR_SGIS if I am not wrong. This is actually implicit. vgic_map_phys_irq() takes a parameter (irq) that is the Linux view of the hwirq we're dealing with (we fetch this hwirq by traversing the irq_data list associated with irq). SGIs are not part of the set of interrupts that can be mapped to a Linux irq (their usage is completely private to the two GIC drivers). Note that GICv3 allows SGIs to be set as a physical interrupt in an LR though, but this is not a feature we use so far. > besides Reviewed-by: Eric Auger Thanks! M. -- Jazz is not dead. It just smells funny...