From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43539) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z6oNq-0003wp-6b for qemu-devel@nongnu.org; Sun, 21 Jun 2015 19:10:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z6oNm-0004kv-VY for qemu-devel@nongnu.org; Sun, 21 Jun 2015 19:10:38 -0400 Received: from icp-osb-irony-out2.external.iinet.net.au ([203.59.1.155]:15685) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z6oNm-0004cA-J3 for qemu-devel@nongnu.org; Sun, 21 Jun 2015 19:10:34 -0400 Message-ID: <5587449B.9020401@uclinux.org> Date: Mon, 22 Jun 2015 09:11:23 +1000 From: Greg Ungerer MIME-Version: 1.0 References: <1434721406-25288-1-git-send-email-gerg@uclinux.org> <1434721406-25288-4-git-send-email-gerg@uclinux.org> <55846EF9.20302@vivier.eu> In-Reply-To: <55846EF9.20302@vivier.eu> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v2 3/3] m68k: fix usp processing on interrupt entry and exception exit List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Laurent Vivier , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Hi Laurent, On 20/06/15 05:35, Laurent Vivier wrote: > Le 19/06/2015 15:43, gerg@uclinux.org a écrit : >> From: Greg Ungerer >> >> The action to potentially switch sp register is not occurring at the correct >> point in the interrupt entry or exception exit sequences. >> >> For the interrupt entry case the sp on entry is used to create the stack >> exception frame - but this may well be the user stack pointer, since we >> haven't done the switch yet. Re-order the flow to switch the sp regs then >> use the current sp to create the exception frame. >> >> For the return from exception case the code is unwinding the sp after >> switching sp registers. But it should always unwind the supervisor sp >> first, then carry out any required sp switch. >> >> Note that these problems don't effect operation unless the user sp bit is >> set in the CACR register. Only a single sp is used in the default power up >> state. Previously Linux only used this single sp mode. But modern versions >> of Linux use the user sp mode now, so we need correct behavior for Linux >> to work. >> >> Signed-off-by: Greg Ungerer >> Reviewed-by: Peter Crosthwaite >> --- >> target-m68k/op_helper.c | 7 +++---- >> 1 file changed, 3 insertions(+), 4 deletions(-) > > Reviewed-by: Laurent Vivier Thanks for the reviews. Regards Greg