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Date: Tue, 23 Jun 2015 14:33:25 +0530
From: Vineet Gupta <Vineet.Gupta1@synopsys.com>
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To: Will Deacon <will.deacon@arm.com>,
        Vineet Gupta <Vineet.Gupta1@synopsys.com>
CC: "Peter Zijlstra (Intel)" <peterz@infradead.org>,
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Subject: Re: [PATCH v2 20/28] ARCv2: barriers
References: <20150622133656.GG1583@arm.com> <1435046283-2073-1-git-send-email-vgupta@synopsys.com> <20150623084905.GE31504@arm.com>
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Hi Will,

On Tuesday 23 June 2015 02:19 PM, Will Deacon wrote:
>> +/*
>> > + * MMIO can also get buffered/optimized in micro-arch, so barriers needed
>> > + * Based on ARM model for the typical use case
>> > + *
>> > + *	<writel_relaxed DMA buffer>
>> > + *	<writel MMIO "go" reg>
>> > + *   or:
>> > + *   	<readl MMIO "status" reg>
>> > + *   	<readl_relaxed DMA buffer>
> The writel_relaxed/readl_relaxed parts here would actually just be
> bog-standard loads and stores to an in-memory buffer. I was trying too hard
> to show the barrier semantics and accidentally turned the DMA buffers into
> __iomem regions.

Not sure if I follow you completely :-)

IMHO, It doesn't matter if we are dealing with a typical DMA buffer (cached) or a
buffer descriptor (typically uncached unless there's hardware IO-coh or some
such). Both the cases assume a vanilla ld/st to buffer (using relaxed API) with a
surrounding MMIO access.

> 
> If you fix the comment:

Does this look better ?

- *	<writel_relaxed DMA buffer>
+ *	<writel_relaxed DMA buffer (cached or uncached)>

> 
>   Reviewed-by: Will Deacon <will.deacon@arm.com>
> 
> Sorry for messing you about.

NP.

-Vineet