From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753797AbbGJIaE (ORCPT ); Fri, 10 Jul 2015 04:30:04 -0400 Received: from mx6-11.smtp.antispamcloud.com ([95.211.2.202]:44759 "EHLO mx6-11.smtp.antispamcloud.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753695AbbGJI34 convert rfc822-to-8bit (ORCPT ); Fri, 10 Jul 2015 04:29:56 -0400 Message-ID: <559F824B.70409@topic.nl> Date: Fri, 10 Jul 2015 10:28:59 +0200 From: Mike Looijmans Organization: TOPIC User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Ranjit Waghmode , , , , , , , , , , CC: , , , , , , Subject: Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller References: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> In-Reply-To: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 8BIT X-Originating-IP: [192.168.80.121] X-EXCLAIMER-MD-CONFIG: 9833cda7-5b21-4d34-9a38-8d025ddc3664 X-EXCLAIMER-MD-BIFURCATION-INSTANCE: 0 X-Filter-ID: s0sct1PQhAABKnZB5plbIbbvfIHzQjPVmPLZeVYSu3xU9luQrU+8/8qthi+0Jd/W6KAUC/fjyuDn NXFr4uarw5eco5BqsrGMIC6V7pxVoLcgpNtsjMLpdM11T3IPbAvcZddawS/bKuW+rYU/C8IT4F5p bXKroBz/y1PvNA2QiywrzG03MuuhP3m/69Y1asa0qhdkXgXTeobVjhd2c43Bg0Y3EvdM23dUfR14 3KE/4v+Uju7Mz6o3TMT3RJo5OKqrCqcaqJNBb/BIEGylSSAZuueGC46k7iZFtozlURr2pkvrtg3v JcEUFwz/R8EHyA7eYsXsvFHpTlUoXR3Ya2B9K90AdtZa2mjKb78fw2VXy6dsKx0jN892aQ4DaIRi qMD14MbgQgiceQl8uL8y0m7nhYie4/r3NcmxDfqNg8BUBmqMjnka3qXsSSMAlv9amQ6L7ren9RtR NyYim5e3GD8LGeGDyFWHSOonSbDOzuQUgpSWwieZyauFYqHkIbFa+ipF7zM1lYMxaAWyLlOnNnnm M/4MKPaJmInahF8kF2RcLQhMyIwFl5U4d6UVQrxIHxN5U2Itm39BdCc4FEP6OrUewot947/08hkq gx59xd7vvImzOrJjy1yKKiw83iopLLaiYkB2KcC/UF8DmxaZ4mg50DZQ6OtBjX2dhf8r1xeX6dHd dMxmUDcHQv5a5zaGp8PBOrupYUt9S9HavDLXf+2rEg0sD2jyg7nEo++XBb5Dno6t4hw44E5uL2FJ nhWe2wx0R+BygZvGEbROKZnt1XChvkUqaQSYcfONHtQexdJLC1BRXxKF5tPxTxfD0dMN+t5ZVLTv 9Pzwh+zbciFXRA+ooJmI4wbSR1WkSgn2HTLzIeh5FQiAhUtEiNByG3fYYIcTVgW9/bktU41htiJ8 fk7NkOrLVHUDlAdlaDgBE4OnDq3Z7tqNvjCaWqs2Wy4Mh9wY1VdDrVw0gcE/FXoJm/J+XxEVniih uDwEGDcmr6e3OPRjo+RBF4eg25ZmE5IxjR7LoJIsJUe0JQdQ87wKZo+Uwbo3yRv2NMtDk+J2uBzS dfKggwXnXge+UydFbsUWPrpxJ2nsnL2uDUV7tpt492PMwfcRqNG53byBPkgwbHJvry4N+ovFkFpc BK/U+YjKb4emkX5ueSr5knZEqVTrM4EZ+F9l1/WyLBg0mKuTgAEprJE7zbXfdqPHGJxn2At63m8J XEZ0zOnpexgJhSjxayETuPRa5WfDzenuhDz8ptS5Tx1qtSkX/6+Es/zmaRHHOebZOPPz3vKPMvor TYlGJYus6fY4ocfmWv3Fe9Iziczdq+A= X-Report-Abuse-To: spam@mx99.antispamcloud.com X-Filter-Fingerprint: IFrWXGses7OKB5S5G8/dJXhXyDRoOQM5J3kcUr0HrMvJUWjZ8+qhjyB23tbDuyLOYL8Ff78gYsez 4Rl08xudmXi4esCQ0R1MchVjt7wblGlvhFgW0MjUMRkF5sMCDfftTXNFDzN17hnrWeZYOJvLq0Ic WjZ+XcEjj/7Pkld0zkmvziDInX9WdMov2kn2yXjdwv61T+KDYyYtREgszdyFwv8IxCB3p/oCKvxr eyISh3JGb7OS5oVgiO+kDxZrVPLz3MmEGC2PrUKqLq5WmHK+Nw== X-Originating-IP: 88.159.208.100 X-Spampanel-Domain: topic.nl X-Spampanel-Username: 88.159.208.100 Authentication-Results: antispamcloud.com; auth=pass smtp.auth=88.159.208.100@topic.nl X-Spampanel-Outgoing-Class: ham X-Spampanel-Outgoing-Evidence: Combined (0.00) X-Recommended-Action: accept Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 09-07-15 14:44, Ranjit Waghmode wrote: > This series of patches is to add dual parallel and stacked mode support for > Zynq Ultrascale+ MPSoC GQSPI controller driver. > > These are all very high level changes and expected to make an idea clear. > Comments and suggestions are welcomed. > ... > > What is stacked mode? > --------------------- > ZynqMP GQSPI controller supports stacked mode with following functionalities: > 1) The Generic Quad-SPI controller also supports two SPI flash memories > in a shared bus arrangement to reduce IO pin count. > 2) Separate chip select lines > 3) Shared I/O lines > 4) This mode is targeted for increasing the flash memory and no performance > improvement when compared with single. One could also model the stacked mode as having two distinct flash chips with separate chip selects and shared lines. Merging them into a single storage device can be done on block layer or higher level. This allows the flash chips to be used in any configuration using existing support for concatenating multiple devices. I think this would be a more generic way of doing this. It also allows much more flexibility, for example the devices could be used in a mirror setup, or in combination with additional devices on other controllers. Kind regards, Mike Looijmans System Expert TOPIC Embedded Products Eindhovenseweg 32-C, NL-5683 KH Best Postbus 440, NL-5680 AK Best Telefoon: +31 (0) 499 33 69 79 Telefax: +31 (0) 499 33 69 70 E-mail: mike.looijmans@topicproducts.com Website: www.topicproducts.com Please consider the environment before printing this e-mail From mboxrd@z Thu Jan 1 00:00:00 1970 From: mike.looijmans@topic.nl (Mike Looijmans) Date: Fri, 10 Jul 2015 10:28:59 +0200 Subject: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller In-Reply-To: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> References: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> Message-ID: <559F824B.70409@topic.nl> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org ?On 09-07-15 14:44, Ranjit Waghmode wrote: > This series of patches is to add dual parallel and stacked mode support for > Zynq Ultrascale+ MPSoC GQSPI controller driver. > > These are all very high level changes and expected to make an idea clear. > Comments and suggestions are welcomed. > ... > > What is stacked mode? > --------------------- > ZynqMP GQSPI controller supports stacked mode with following functionalities: > 1) The Generic Quad-SPI controller also supports two SPI flash memories > in a shared bus arrangement to reduce IO pin count. > 2) Separate chip select lines > 3) Shared I/O lines > 4) This mode is targeted for increasing the flash memory and no performance > improvement when compared with single. One could also model the stacked mode as having two distinct flash chips with separate chip selects and shared lines. Merging them into a single storage device can be done on block layer or higher level. This allows the flash chips to be used in any configuration using existing support for concatenating multiple devices. I think this would be a more generic way of doing this. It also allows much more flexibility, for example the devices could be used in a mirror setup, or in combination with additional devices on other controllers. Kind regards, Mike Looijmans System Expert TOPIC Embedded Products Eindhovenseweg 32-C, NL-5683 KH Best Postbus 440, NL-5680 AK Best Telefoon: +31 (0) 499 33 69 79 Telefax: +31 (0) 499 33 69 70 E-mail: mike.looijmans at topicproducts.com Website: www.topicproducts.com Please consider the environment before printing this e-mail