From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752477AbbGKG35 (ORCPT ); Sat, 11 Jul 2015 02:29:57 -0400 Received: from avon.wwwdotorg.org ([70.85.31.133]:43918 "EHLO avon.wwwdotorg.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751471AbbGKG34 (ORCPT ); Sat, 11 Jul 2015 02:29:56 -0400 Message-ID: <55A0A5EB.4090007@wwwdotorg.org> Date: Fri, 10 Jul 2015 23:13:15 -0600 From: Stephen Warren User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Eric Anholt , linux-arm-kernel@lists.infradead.org CC: linux-rpi-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Lee Jones , devicetree@vger.kernel.org, Thomas Gleixner , Jason Cooper , Andrea Merello Subject: Re: [PATCH 4/4] irqchip: Add bcm2836 interrupt controller for Raspberry Pi 2. References: <1436303617-17185-1-git-send-email-eric@anholt.net> <1436303617-17185-5-git-send-email-eric@anholt.net> In-Reply-To: <1436303617-17185-5-git-send-email-eric@anholt.net> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/07/2015 03:13 PM, Eric Anholt wrote: > This interrupt controller is the new root interrupt controller with > the timer, PMU events, and IPIs, and the bcm2835's interrupt > controller is chained off of it to handle the peripherals. > > SMP IPI support was mostly written by Andrea Merello, while I wrote > most of the rest of the IRQ handling. > > Signed-off-by: Andrea Merello > Signed-off-by: Eric Anholt I'd expect the git patch author to be Andrea if he wrote the original patch and you enhanced it. > diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c > +struct arm_local_intc { > + struct irq_domain *domain; > + void __iomem *base; > +}; > + > +static struct arm_local_intc intc __read_mostly; It'd be nice to give everything (types, functions, variables) a consistent symbol prefix; bcm2836_arm_irqchip_ sounds like a good bikeshed to me, but perhaps just propagating the above arm_local_ to the functions too would be good, although that seems to risk symbol name collisions with other ARM SoCs. > +static void bcm2836_mask_per_cpu_irq(unsigned int reg, unsigned int bit) > +{ > + void __iomem *reg_base = intc.base + reg; > + unsigned int i; > + > + for (i = 0; i < 4; i++) Is "4" there the CPU count? Perhaps this should use one of the Linux APIs to query the CPU count rather than hard-coding it? Should per-CPU IRQs automatically be masked on all CPUs at once, or only on the current CPU? A very quick look at the ARM GIC driver implies it doesn't iterate over all CPUs when masking per-CPU IRQs. > +static void bcm2836_mask_gpu_irq(struct irq_data *d) > +{ > +} > + > +static void bcm2836_unmask_gpu_irq(struct irq_data *d) > +{ > +} If the IRQs can't be masked, should these functions actually be implemented? > +static void __exception_irq_entry bcm2836_handle_irq(struct pt_regs *regs) > +{ > + int cpu = smp_processor_id(); > + u32 stat; > + > + stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu); > + if (stat & 0x10) { > + void __iomem *mailbox0 = (intc.base + > + LOCAL_MAILBOX0_CLR0 + 16 * cpu); > + u32 mbox_val = readl(mailbox0); > + u32 ipi = ffs(mbox_val) - 1; > + > + writel(1 << ipi, mailbox0); > + handle_IPI(ipi, regs); Given that bcm2836_send_ipi() is #ifdef CONFIG_SMP, should this code be too? From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: Re: [PATCH 4/4] irqchip: Add bcm2836 interrupt controller for Raspberry Pi 2. Date: Fri, 10 Jul 2015 23:13:15 -0600 Message-ID: <55A0A5EB.4090007@wwwdotorg.org> References: <1436303617-17185-1-git-send-email-eric@anholt.net> <1436303617-17185-5-git-send-email-eric@anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1436303617-17185-5-git-send-email-eric@anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Eric Anholt , linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org, Jason Cooper , Andrea Merello , Lee Jones , linux-kernel@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, Thomas Gleixner List-Id: devicetree@vger.kernel.org On 07/07/2015 03:13 PM, Eric Anholt wrote: > This interrupt controller is the new root interrupt controller with > the timer, PMU events, and IPIs, and the bcm2835's interrupt > controller is chained off of it to handle the peripherals. > > SMP IPI support was mostly written by Andrea Merello, while I wrote > most of the rest of the IRQ handling. > > Signed-off-by: Andrea Merello > Signed-off-by: Eric Anholt I'd expect the git patch author to be Andrea if he wrote the original patch and you enhanced it. > diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c > +struct arm_local_intc { > + struct irq_domain *domain; > + void __iomem *base; > +}; > + > +static struct arm_local_intc intc __read_mostly; It'd be nice to give everything (types, functions, variables) a consistent symbol prefix; bcm2836_arm_irqchip_ sounds like a good bikeshed to me, but perhaps just propagating the above arm_local_ to the functions too would be good, although that seems to risk symbol name collisions with other ARM SoCs. > +static void bcm2836_mask_per_cpu_irq(unsigned int reg, unsigned int bit) > +{ > + void __iomem *reg_base = intc.base + reg; > + unsigned int i; > + > + for (i = 0; i < 4; i++) Is "4" there the CPU count? Perhaps this should use one of the Linux APIs to query the CPU count rather than hard-coding it? Should per-CPU IRQs automatically be masked on all CPUs at once, or only on the current CPU? A very quick look at the ARM GIC driver implies it doesn't iterate over all CPUs when masking per-CPU IRQs. > +static void bcm2836_mask_gpu_irq(struct irq_data *d) > +{ > +} > + > +static void bcm2836_unmask_gpu_irq(struct irq_data *d) > +{ > +} If the IRQs can't be masked, should these functions actually be implemented? > +static void __exception_irq_entry bcm2836_handle_irq(struct pt_regs *regs) > +{ > + int cpu = smp_processor_id(); > + u32 stat; > + > + stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu); > + if (stat & 0x10) { > + void __iomem *mailbox0 = (intc.base + > + LOCAL_MAILBOX0_CLR0 + 16 * cpu); > + u32 mbox_val = readl(mailbox0); > + u32 ipi = ffs(mbox_val) - 1; > + > + writel(1 << ipi, mailbox0); > + handle_IPI(ipi, regs); Given that bcm2836_send_ipi() is #ifdef CONFIG_SMP, should this code be too? From mboxrd@z Thu Jan 1 00:00:00 1970 From: swarren@wwwdotorg.org (Stephen Warren) Date: Fri, 10 Jul 2015 23:13:15 -0600 Subject: [PATCH 4/4] irqchip: Add bcm2836 interrupt controller for Raspberry Pi 2. In-Reply-To: <1436303617-17185-5-git-send-email-eric@anholt.net> References: <1436303617-17185-1-git-send-email-eric@anholt.net> <1436303617-17185-5-git-send-email-eric@anholt.net> Message-ID: <55A0A5EB.4090007@wwwdotorg.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 07/07/2015 03:13 PM, Eric Anholt wrote: > This interrupt controller is the new root interrupt controller with > the timer, PMU events, and IPIs, and the bcm2835's interrupt > controller is chained off of it to handle the peripherals. > > SMP IPI support was mostly written by Andrea Merello, while I wrote > most of the rest of the IRQ handling. > > Signed-off-by: Andrea Merello > Signed-off-by: Eric Anholt I'd expect the git patch author to be Andrea if he wrote the original patch and you enhanced it. > diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c > +struct arm_local_intc { > + struct irq_domain *domain; > + void __iomem *base; > +}; > + > +static struct arm_local_intc intc __read_mostly; It'd be nice to give everything (types, functions, variables) a consistent symbol prefix; bcm2836_arm_irqchip_ sounds like a good bikeshed to me, but perhaps just propagating the above arm_local_ to the functions too would be good, although that seems to risk symbol name collisions with other ARM SoCs. > +static void bcm2836_mask_per_cpu_irq(unsigned int reg, unsigned int bit) > +{ > + void __iomem *reg_base = intc.base + reg; > + unsigned int i; > + > + for (i = 0; i < 4; i++) Is "4" there the CPU count? Perhaps this should use one of the Linux APIs to query the CPU count rather than hard-coding it? Should per-CPU IRQs automatically be masked on all CPUs at once, or only on the current CPU? A very quick look@the ARM GIC driver implies it doesn't iterate over all CPUs when masking per-CPU IRQs. > +static void bcm2836_mask_gpu_irq(struct irq_data *d) > +{ > +} > + > +static void bcm2836_unmask_gpu_irq(struct irq_data *d) > +{ > +} If the IRQs can't be masked, should these functions actually be implemented? > +static void __exception_irq_entry bcm2836_handle_irq(struct pt_regs *regs) > +{ > + int cpu = smp_processor_id(); > + u32 stat; > + > + stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu); > + if (stat & 0x10) { > + void __iomem *mailbox0 = (intc.base + > + LOCAL_MAILBOX0_CLR0 + 16 * cpu); > + u32 mbox_val = readl(mailbox0); > + u32 ipi = ffs(mbox_val) - 1; > + > + writel(1 << ipi, mailbox0); > + handle_IPI(ipi, regs); Given that bcm2836_send_ipi() is #ifdef CONFIG_SMP, should this code be too?