From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Date: Fri, 10 Jul 2015 23:17:58 -0600 Subject: [U-Boot] [PATCH 0/5] dcache support for Raspberry Pi 1 In-Reply-To: <1436003324-8769-1-git-send-email-alexanders83@web.de> References: <1436003324-8769-1-git-send-email-alexanders83@web.de> Message-ID: <55A0A706.3030306@wwwdotorg.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 07/04/2015 03:48 AM, Alexander Stein wrote: > This patchset enables dcache support for Raspberry Pi 1. > First the cache support code was made similar to existing arm1136 code. > The invalidate and flush functions were inprovoed to accept also non-cacheline > aligned addresses. This reduces the cacheline size knowledge from generic > code. As mentioned in some other responses, client code must be aware of the cacheline size, so the cache management code shouldn't try to handle misaligned requests, but should error out. BTW, ALLOC_ALIGN_BUFFER() is probably what you need to fix any misbehaved client code.