From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Date: Fri, 10 Jul 2015 23:21:59 -0600 Subject: [U-Boot] [PATCH 3/5] arm1176/cpu: Align cache flushing addresses to cacheline size In-Reply-To: <1436003324-8769-4-git-send-email-alexanders83@web.de> References: <1436003324-8769-1-git-send-email-alexanders83@web.de> <1436003324-8769-4-git-send-email-alexanders83@web.de> Message-ID: <55A0A7F7.9050205@wwwdotorg.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 07/04/2015 03:48 AM, Alexander Stein wrote: > cache flushing addresses must be cacheline size aligned, so mask the > start and stop address appropriately. As mentioned elsewhere, NAK.