From mboxrd@z Thu Jan  1 00:00:00 1970
From: Julien Grall <julien.grall@citrix.com>
Subject: Re: [PATCH v6 24/31] xen/arm: ITS: Add GICR register
 emulation
Date: Mon, 7 Sep 2015 15:20:24 +0100
Message-ID: <55ED9D28.7050902@citrix.com>
References: <1441019208-2764-1-git-send-email-vijay.kilari@gmail.com>
	<1441019208-2764-25-git-send-email-vijay.kilari@gmail.com>
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To: vijay.kilari@gmail.com, Ian.Campbell@citrix.com, stefano.stabellini@eu.citrix.com, stefano.stabellini@citrix.com, tim@xen.org, xen-devel@lists.xen.org
Cc: Prasun.Kapoor@caviumnetworks.com, Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>, manish.jaggi@caviumnetworks.com
List-Id: xen-devel@lists.xenproject.org

Hi Vijay,

On 31/08/15 12:06, vijay.kilari@gmail.com wrote:
> +static int vgic_v3_gits_lpi_mmio_read(struct vcpu *v, mmio_info_t *info)

[...]

> +    /* Neglect if not LPI. */
> +    if ( offset < FIRST_GIC_LPI )
> +    {
> +        *r = 0;
> +        return 1;
> +    }

[...]

> +static int vgic_v3_gits_lpi_mmio_write(struct vcpu *v, mmio_info_t *info)
> +{

[...]

> +    /* Neglect if not LPI. */
> +    if ( offset < FIRST_GIC_LPI )
> +        return 1;

Based on the spec, those 2 checks are wrong and make impossible to use
LPIs. Please test this patch series before sending it on the ML.

Regards,


-- 
Julien Grall