* [PATCH V2 1/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC
@ 2015-09-11 8:18 ` Chen Feng
0 siblings, 0 replies; 13+ messages in thread
From: Chen Feng @ 2015-09-11 8:18 UTC (permalink / raw
To: puck.chen, p.zabel, linux-kernel, robh+dt, pawel.moll, xuwei5,
haojian.zhuang, zhangfei.gao
Cc: xuyiping, bintian.wang, devicetree, dan.zhao, suzhuangluan, w.f
Add reset controller for hi6220 hikey-board.
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3f03380..3bbc846 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -167,5 +167,12 @@
clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
clock-names = "uartclk", "apb_pclk";
};
+
+ reset_ctrl: reset_ctrl@f7030000 {
+ compatible = "hisilicon,hi6220_reset_ctl";
+ reg = <0x0 0xf7030000 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V2 1/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC
@ 2015-09-11 8:18 ` Chen Feng
0 siblings, 0 replies; 13+ messages in thread
From: Chen Feng @ 2015-09-11 8:18 UTC (permalink / raw
To: puck.chen, p.zabel, linux-kernel, robh+dt, pawel.moll, xuwei5,
haojian.zhuang, zhangfei.gao
Cc: xuyiping, bintian.wang, devicetree, dan.zhao, suzhuangluan, w.f
Add reset controller for hi6220 hikey-board.
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3f03380..3bbc846 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -167,5 +167,12 @@
clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
clock-names = "uartclk", "apb_pclk";
};
+
+ reset_ctrl: reset_ctrl@f7030000 {
+ compatible = "hisilicon,hi6220_reset_ctl";
+ reg = <0x0 0xf7030000 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V2 2/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings
2015-09-11 8:18 ` Chen Feng
@ 2015-09-11 8:18 ` Chen Feng
-1 siblings, 0 replies; 13+ messages in thread
From: Chen Feng @ 2015-09-11 8:18 UTC (permalink / raw
To: puck.chen, p.zabel, linux-kernel, robh+dt, pawel.moll, xuwei5,
haojian.zhuang, zhangfei.gao
Cc: xuyiping, bintian.wang, devicetree, dan.zhao, suzhuangluan, w.f
Add DT bindings documentation for hi6220 SoC reset controller.
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
---
.../bindings/reset/hisilicon,hi6220-reset.txt | 97 ++++++++++++++++++++++
1 file changed, 97 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
new file mode 100644
index 0000000..200dc8e
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
@@ -0,0 +1,97 @@
+Hisilicon System Reset Controller
+======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The reset controller node must be a sub-node of the chip controller
+node on SoCs.
+
+Required properties:
+- compatible: may be "hisilicon,hi6220_reset_ctl"
+- reg: should be register base and length as documented in the
+ datasheet
+- #reset-cells: 1, see below
+
+Example:
+
+ reset_ctrl: reset_ctrl@f7030000 {
+ compatible = "hisilicon,hi6220_reset_ctl";
+ reg = <0x0 0xf7030000 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
+Specifying reset lines connected to IP modules
+==============================================
+example:
+
+ uart1: uart1@..... {
+ ...
+ resets = <&reset_ctrl 0x305>;
+ ...
+ };
+
+The following RESET_INDEX values are valid for hi6220 SoC:
+ PERIPH_RSTDIS0_MMC0 = 0x000,
+ PERIPH_RSTDIS0_MMC1 = 0x001,
+ PERIPH_RSTDIS0_MMC2 = 0x002,
+ PERIPH_RSTDIS0_NANDC = 0x003,
+ PERIPH_RSTDIS0_USBOTG_BUS = 0x004,
+ PERIPH_RSTDIS0_POR_PICOPHY = 0x005,
+ PERIPH_RSTDIS0_USBOTG = 0x006,
+ PERIPH_RSTDIS0_USBOTG_32K = 0x007,
+
+ PERIPH_RSTDIS1_HIFI = 0x100,
+ PERIPH_RSTDIS1_DIGACODEC = 0x105,
+
+ PERIPH_RSTEN2_IPF = 0x200,
+ PERIPH_RSTEN2_SOCP = 0x201,
+ PERIPH_RSTEN2_DMAC = 0x202,
+ PERIPH_RSTEN2_SECENG = 0x203,
+ PERIPH_RSTEN2_ABB = 0x204,
+ PERIPH_RSTEN2_HPM0 = 0x205,
+ PERIPH_RSTEN2_HPM1 = 0x206,
+ PERIPH_RSTEN2_HPM2 = 0x207,
+ PERIPH_RSTEN2_HPM3 = 0x208,
+
+ PERIPH_RSTEN3_CSSYS = 0x300,
+ PERIPH_RSTEN3_I2C0 = 0x301,
+ PERIPH_RSTEN3_I2C1 = 0x302,
+ PERIPH_RSTEN3_I2C2 = 0x303,
+ PERIPH_RSTEN3_I2C3 = 0x304,
+ PERIPH_RSTEN3_UART1 = 0x305,
+ PERIPH_RSTEN3_UART2 = 0x306,
+ PERIPH_RSTEN3_UART3 = 0x307,
+ PERIPH_RSTEN3_UART4 = 0x308,
+ PERIPH_RSTEN3_SSP = 0x309,
+ PERIPH_RSTEN3_PWM = 0x30a,
+ PERIPH_RSTEN3_BLPWM = 0x30b,
+ PERIPH_RSTEN3_TSENSOR = 0x30c,
+ PERIPH_RSTEN3_DAPB = 0x312,
+ PERIPH_RSTEN3_HKADC = 0x313,
+ PERIPH_RSTEN3_CODEC_SSI = 0x314,
+ PERIPH_RSTEN3_PMUSSI1 = 0x316,
+
+ PERIPH_RSTEN8_RS0 = 0x400,
+ PERIPH_RSTEN8_RS2 = 0x401,
+ PERIPH_RSTEN8_RS3 = 0x402,
+ PERIPH_RSTEN8_MS0 = 0x403,
+ PERIPH_RSTEN8_MS2 = 0x405,
+ PERIPH_RSTEN8_XG2RAM0 = 0x406,
+ PERIPH_RSTEN8_X2SRAM_TZMA = 0x407,
+ PERIPH_RSTEN8_SRAM = 0x408,
+ PERIPH_RSTEN8_HARQ = 0x40a,
+ PERIPH_RSTEN8_DDRC = 0x40c,
+ PERIPH_RSTEN8_DDRC_APB = 0x40d,
+ PERIPH_RSTEN8_DDRPACK_APB = 0x40e,
+ PERIPH_RSTEN8_DDRT = 0x411,
+
+ PERIPH_RSDIST9_CARM_DAP = 0x500,
+ PERIPH_RSDIST9_CARM_ATB = 0x501,
+ PERIPH_RSDIST9_CARM_LBUS = 0x502,
+ PERIPH_RSDIST9_CARM_POR = 0x503,
+ PERIPH_RSDIST9_CARM_CORE = 0x504,
+ PERIPH_RSDIST9_CARM_DBG = 0x505,
+ PERIPH_RSDIST9_CARM_L2 = 0x506,
+ PERIPH_RSDIST9_CARM_SOCDBG = 0x507,
+ PERIPH_RSDIST9_CARM_ETM = 0x508,
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V2 2/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings
@ 2015-09-11 8:18 ` Chen Feng
0 siblings, 0 replies; 13+ messages in thread
From: Chen Feng @ 2015-09-11 8:18 UTC (permalink / raw
To: puck.chen, p.zabel, linux-kernel, robh+dt, pawel.moll, xuwei5,
haojian.zhuang, zhangfei.gao
Cc: xuyiping, bintian.wang, devicetree, dan.zhao, suzhuangluan, w.f
Add DT bindings documentation for hi6220 SoC reset controller.
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
---
.../bindings/reset/hisilicon,hi6220-reset.txt | 97 ++++++++++++++++++++++
1 file changed, 97 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
new file mode 100644
index 0000000..200dc8e
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
@@ -0,0 +1,97 @@
+Hisilicon System Reset Controller
+======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The reset controller node must be a sub-node of the chip controller
+node on SoCs.
+
+Required properties:
+- compatible: may be "hisilicon,hi6220_reset_ctl"
+- reg: should be register base and length as documented in the
+ datasheet
+- #reset-cells: 1, see below
+
+Example:
+
+ reset_ctrl: reset_ctrl@f7030000 {
+ compatible = "hisilicon,hi6220_reset_ctl";
+ reg = <0x0 0xf7030000 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
+Specifying reset lines connected to IP modules
+==============================================
+example:
+
+ uart1: uart1@..... {
+ ...
+ resets = <&reset_ctrl 0x305>;
+ ...
+ };
+
+The following RESET_INDEX values are valid for hi6220 SoC:
+ PERIPH_RSTDIS0_MMC0 = 0x000,
+ PERIPH_RSTDIS0_MMC1 = 0x001,
+ PERIPH_RSTDIS0_MMC2 = 0x002,
+ PERIPH_RSTDIS0_NANDC = 0x003,
+ PERIPH_RSTDIS0_USBOTG_BUS = 0x004,
+ PERIPH_RSTDIS0_POR_PICOPHY = 0x005,
+ PERIPH_RSTDIS0_USBOTG = 0x006,
+ PERIPH_RSTDIS0_USBOTG_32K = 0x007,
+
+ PERIPH_RSTDIS1_HIFI = 0x100,
+ PERIPH_RSTDIS1_DIGACODEC = 0x105,
+
+ PERIPH_RSTEN2_IPF = 0x200,
+ PERIPH_RSTEN2_SOCP = 0x201,
+ PERIPH_RSTEN2_DMAC = 0x202,
+ PERIPH_RSTEN2_SECENG = 0x203,
+ PERIPH_RSTEN2_ABB = 0x204,
+ PERIPH_RSTEN2_HPM0 = 0x205,
+ PERIPH_RSTEN2_HPM1 = 0x206,
+ PERIPH_RSTEN2_HPM2 = 0x207,
+ PERIPH_RSTEN2_HPM3 = 0x208,
+
+ PERIPH_RSTEN3_CSSYS = 0x300,
+ PERIPH_RSTEN3_I2C0 = 0x301,
+ PERIPH_RSTEN3_I2C1 = 0x302,
+ PERIPH_RSTEN3_I2C2 = 0x303,
+ PERIPH_RSTEN3_I2C3 = 0x304,
+ PERIPH_RSTEN3_UART1 = 0x305,
+ PERIPH_RSTEN3_UART2 = 0x306,
+ PERIPH_RSTEN3_UART3 = 0x307,
+ PERIPH_RSTEN3_UART4 = 0x308,
+ PERIPH_RSTEN3_SSP = 0x309,
+ PERIPH_RSTEN3_PWM = 0x30a,
+ PERIPH_RSTEN3_BLPWM = 0x30b,
+ PERIPH_RSTEN3_TSENSOR = 0x30c,
+ PERIPH_RSTEN3_DAPB = 0x312,
+ PERIPH_RSTEN3_HKADC = 0x313,
+ PERIPH_RSTEN3_CODEC_SSI = 0x314,
+ PERIPH_RSTEN3_PMUSSI1 = 0x316,
+
+ PERIPH_RSTEN8_RS0 = 0x400,
+ PERIPH_RSTEN8_RS2 = 0x401,
+ PERIPH_RSTEN8_RS3 = 0x402,
+ PERIPH_RSTEN8_MS0 = 0x403,
+ PERIPH_RSTEN8_MS2 = 0x405,
+ PERIPH_RSTEN8_XG2RAM0 = 0x406,
+ PERIPH_RSTEN8_X2SRAM_TZMA = 0x407,
+ PERIPH_RSTEN8_SRAM = 0x408,
+ PERIPH_RSTEN8_HARQ = 0x40a,
+ PERIPH_RSTEN8_DDRC = 0x40c,
+ PERIPH_RSTEN8_DDRC_APB = 0x40d,
+ PERIPH_RSTEN8_DDRPACK_APB = 0x40e,
+ PERIPH_RSTEN8_DDRT = 0x411,
+
+ PERIPH_RSDIST9_CARM_DAP = 0x500,
+ PERIPH_RSDIST9_CARM_ATB = 0x501,
+ PERIPH_RSDIST9_CARM_LBUS = 0x502,
+ PERIPH_RSDIST9_CARM_POR = 0x503,
+ PERIPH_RSDIST9_CARM_CORE = 0x504,
+ PERIPH_RSDIST9_CARM_DBG = 0x505,
+ PERIPH_RSDIST9_CARM_L2 = 0x506,
+ PERIPH_RSDIST9_CARM_SOCDBG = 0x507,
+ PERIPH_RSDIST9_CARM_ETM = 0x508,
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V2 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC
@ 2015-09-11 8:18 ` Chen Feng
0 siblings, 0 replies; 13+ messages in thread
From: Chen Feng @ 2015-09-11 8:18 UTC (permalink / raw
To: puck.chen, p.zabel, linux-kernel, robh+dt, pawel.moll, xuwei5,
haojian.zhuang, zhangfei.gao
Cc: xuyiping, bintian.wang, devicetree, dan.zhao, suzhuangluan, w.f
Add reset driver for hi6220-hikey board,this driver supply deassert
of IP. on hi6220 SoC.
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
---
drivers/reset/Kconfig | 1 +
drivers/reset/Makefile | 1 +
drivers/reset/hisilicon/Kconfig | 5 ++
drivers/reset/hisilicon/Makefile | 1 +
drivers/reset/hisilicon/hi6220_reset.c | 118 +++++++++++++++++++++++++++++++++
5 files changed, 126 insertions(+)
create mode 100644 drivers/reset/hisilicon/Kconfig
create mode 100644 drivers/reset/hisilicon/Makefile
create mode 100644 drivers/reset/hisilicon/hi6220_reset.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 0615f50..df37212 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER
If unsure, say no.
source "drivers/reset/sti/Kconfig"
+source "drivers/reset/hisilicon/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 157d421..331d7b2 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_HISI) += hisilicon/
diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
new file mode 100644
index 0000000..26bf95a
--- /dev/null
+++ b/drivers/reset/hisilicon/Kconfig
@@ -0,0 +1,5 @@
+config COMMON_RESET_HI6220
+ tristate "Hi6220 Reset Driver"
+ depends on (ARCH_HISI && RESET_CONTROLLER)
+ help
+ Build the Hisilicon Hi6220 reset driver.
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
new file mode 100644
index 0000000..c932f86
--- /dev/null
+++ b/drivers/reset/hisilicon/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c
new file mode 100644
index 0000000..097133d
--- /dev/null
+++ b/drivers/reset/hisilicon/hi6220_reset.c
@@ -0,0 +1,118 @@
+/*
+ * Hisilicon Hi6220 reset controller driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Feng Chen <puck.chen@hisilicon.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/reset-controller.h>
+#include <linux/reset.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
+
+#define ASSET_OFFSET 0x300
+#define DEASSET_OFFSET 0x304
+
+struct hi6220_reset_data {
+ spinlock_t reset_lock; /*device spin-lock*/
+ void __iomem *src_base;
+ void __iomem *asset_base;
+ void __iomem *deasset_base;
+ struct reset_controller_dev rc_dev;
+};
+
+static int hi6220_reset_assert(struct reset_controller_dev *rc_dev,
+ unsigned long idx)
+{
+ struct hi6220_reset_data *data = container_of(rc_dev,
+ struct hi6220_reset_data,
+ rc_dev);
+
+ unsigned long flags;
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ spin_lock_irqsave(&data->reset_lock, flags);
+
+ writel(BIT(offset), data->asset_base + (bank * 0x10));
+
+ spin_unlock_irqrestore(&data->reset_lock, flags);
+
+ return 0;
+}
+
+static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev,
+ unsigned long idx)
+{
+ struct hi6220_reset_data *data = container_of(rc_dev,
+ struct hi6220_reset_data,
+ rc_dev);
+
+ unsigned long flags;
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ spin_lock_irqsave(&data->reset_lock, flags);
+
+ writel(BIT(offset), data->deasset_base + (bank * 0x10));
+
+ spin_unlock_irqrestore(&data->reset_lock, flags);
+
+ return 0;
+}
+
+static struct reset_control_ops hi6220_reset_ops = {
+ .assert = hi6220_reset_assert,
+ .deassert = hi6220_reset_deassert,
+};
+
+static int __init hi6220_reset_init(void)
+{
+ int ret;
+ struct device_node *np;
+ struct hi6220_reset_data *data;
+
+ data = kzalloc(sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi6220_reset_ctl");
+ if (!np) {
+ ret = -ENXIO;
+ goto err_alloc;
+ }
+ spin_lock_init(&data->reset_lock);
+ data->src_base = of_iomap(np, 0);
+ if (!data->src_base) {
+ ret = -ENOMEM;
+ goto err_alloc;
+ }
+
+ data->asset_base = data->src_base + ASSET_OFFSET;
+ data->deasset_base = data->src_base + DEASSET_OFFSET;
+ data->rc_dev.owner = THIS_MODULE;
+ data->rc_dev.nr_resets = SZ_4K;
+ data->rc_dev.ops = &hi6220_reset_ops;
+ data->rc_dev.of_node = np;
+
+ if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
+ reset_controller_register(&data->rc_dev);
+
+ return 0;
+
+err_alloc:
+ kfree(data);
+ return ret;
+}
+
+postcore_initcall(hi6220_reset_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V2 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC
@ 2015-09-11 8:18 ` Chen Feng
0 siblings, 0 replies; 13+ messages in thread
From: Chen Feng @ 2015-09-11 8:18 UTC (permalink / raw
To: puck.chen-C8/M+/jPZTeaMJb+Lgu22Q, p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q,
haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
zhangfei.gao-H32Fclmsjq1BDgjK7y7TUQ
Cc: xuyiping-C8/M+/jPZTeaMJb+Lgu22Q,
bintian.wang-hv44wF8Li93QT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
dan.zhao-C8/M+/jPZTeaMJb+Lgu22Q,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q, w.f-hv44wF8Li93QT0dZR+AlfA
Add reset driver for hi6220-hikey board,this driver supply deassert
of IP. on hi6220 SoC.
Signed-off-by: Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
---
drivers/reset/Kconfig | 1 +
drivers/reset/Makefile | 1 +
drivers/reset/hisilicon/Kconfig | 5 ++
drivers/reset/hisilicon/Makefile | 1 +
drivers/reset/hisilicon/hi6220_reset.c | 118 +++++++++++++++++++++++++++++++++
5 files changed, 126 insertions(+)
create mode 100644 drivers/reset/hisilicon/Kconfig
create mode 100644 drivers/reset/hisilicon/Makefile
create mode 100644 drivers/reset/hisilicon/hi6220_reset.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 0615f50..df37212 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER
If unsure, say no.
source "drivers/reset/sti/Kconfig"
+source "drivers/reset/hisilicon/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 157d421..331d7b2 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_HISI) += hisilicon/
diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
new file mode 100644
index 0000000..26bf95a
--- /dev/null
+++ b/drivers/reset/hisilicon/Kconfig
@@ -0,0 +1,5 @@
+config COMMON_RESET_HI6220
+ tristate "Hi6220 Reset Driver"
+ depends on (ARCH_HISI && RESET_CONTROLLER)
+ help
+ Build the Hisilicon Hi6220 reset driver.
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
new file mode 100644
index 0000000..c932f86
--- /dev/null
+++ b/drivers/reset/hisilicon/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c
new file mode 100644
index 0000000..097133d
--- /dev/null
+++ b/drivers/reset/hisilicon/hi6220_reset.c
@@ -0,0 +1,118 @@
+/*
+ * Hisilicon Hi6220 reset controller driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Feng Chen <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/reset-controller.h>
+#include <linux/reset.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
+
+#define ASSET_OFFSET 0x300
+#define DEASSET_OFFSET 0x304
+
+struct hi6220_reset_data {
+ spinlock_t reset_lock; /*device spin-lock*/
+ void __iomem *src_base;
+ void __iomem *asset_base;
+ void __iomem *deasset_base;
+ struct reset_controller_dev rc_dev;
+};
+
+static int hi6220_reset_assert(struct reset_controller_dev *rc_dev,
+ unsigned long idx)
+{
+ struct hi6220_reset_data *data = container_of(rc_dev,
+ struct hi6220_reset_data,
+ rc_dev);
+
+ unsigned long flags;
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ spin_lock_irqsave(&data->reset_lock, flags);
+
+ writel(BIT(offset), data->asset_base + (bank * 0x10));
+
+ spin_unlock_irqrestore(&data->reset_lock, flags);
+
+ return 0;
+}
+
+static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev,
+ unsigned long idx)
+{
+ struct hi6220_reset_data *data = container_of(rc_dev,
+ struct hi6220_reset_data,
+ rc_dev);
+
+ unsigned long flags;
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ spin_lock_irqsave(&data->reset_lock, flags);
+
+ writel(BIT(offset), data->deasset_base + (bank * 0x10));
+
+ spin_unlock_irqrestore(&data->reset_lock, flags);
+
+ return 0;
+}
+
+static struct reset_control_ops hi6220_reset_ops = {
+ .assert = hi6220_reset_assert,
+ .deassert = hi6220_reset_deassert,
+};
+
+static int __init hi6220_reset_init(void)
+{
+ int ret;
+ struct device_node *np;
+ struct hi6220_reset_data *data;
+
+ data = kzalloc(sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ np = of_find_compatible_node(NULL, NULL, "hisilicon,hi6220_reset_ctl");
+ if (!np) {
+ ret = -ENXIO;
+ goto err_alloc;
+ }
+ spin_lock_init(&data->reset_lock);
+ data->src_base = of_iomap(np, 0);
+ if (!data->src_base) {
+ ret = -ENOMEM;
+ goto err_alloc;
+ }
+
+ data->asset_base = data->src_base + ASSET_OFFSET;
+ data->deasset_base = data->src_base + DEASSET_OFFSET;
+ data->rc_dev.owner = THIS_MODULE;
+ data->rc_dev.nr_resets = SZ_4K;
+ data->rc_dev.ops = &hi6220_reset_ops;
+ data->rc_dev.of_node = np;
+
+ if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
+ reset_controller_register(&data->rc_dev);
+
+ return 0;
+
+err_alloc:
+ kfree(data);
+ return ret;
+}
+
+postcore_initcall(hi6220_reset_init);
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH V2 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC
2015-09-11 8:18 ` Chen Feng
(?)
@ 2015-09-11 8:41 ` Arnd Bergmann
2015-09-14 2:02 ` chenfeng
-1 siblings, 1 reply; 13+ messages in thread
From: Arnd Bergmann @ 2015-09-11 8:41 UTC (permalink / raw
To: Chen Feng
Cc: p.zabel, linux-kernel, robh+dt, pawel.moll, xuwei5,
haojian.zhuang, zhangfei.gao, xuyiping, bintian.wang, devicetree,
dan.zhao, suzhuangluan, w.f
On Friday 11 September 2015 16:18:38 Chen Feng wrote:
> +static int __init hi6220_reset_init(void)
> +{
> + int ret;
> + struct device_node *np;
> + struct hi6220_reset_data *data;
> +
> + data = kzalloc(sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi6220_reset_ctl");
> + if (!np) {
> + ret = -ENXIO;
> + goto err_alloc;
> + }
Why is this not a platform driver?
> + if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
> + reset_controller_register(&data->rc_dev);
> +
> + return 0;
The Kconfig symbol already depends on RESET_CONTROLLER, so
the IS_ENABLED() check looks redundant.
Arnd
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V2 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC
2015-09-11 8:18 ` Chen Feng
@ 2015-09-12 6:06 ` xuyiping
-1 siblings, 0 replies; 13+ messages in thread
From: xuyiping @ 2015-09-12 6:06 UTC (permalink / raw
To: Chen Feng, p.zabel, linux-kernel, robh+dt, pawel.moll, xuwei5,
haojian.zhuang, zhangfei.gao
Cc: bintian.wang, devicetree, dan.zhao, suzhuangluan, w.f
On 2015/9/11 16:18, Chen Feng wrote:
> Add reset driver for hi6220-hikey board,this driver supply deassert
> of IP. on hi6220 SoC.
>
> Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
> ---
> drivers/reset/Kconfig | 1 +
> drivers/reset/Makefile | 1 +
> drivers/reset/hisilicon/Kconfig | 5 ++
> drivers/reset/hisilicon/Makefile | 1 +
> drivers/reset/hisilicon/hi6220_reset.c | 118 +++++++++++++++++++++++++++++++++
> 5 files changed, 126 insertions(+)
> create mode 100644 drivers/reset/hisilicon/Kconfig
> create mode 100644 drivers/reset/hisilicon/Makefile
> create mode 100644 drivers/reset/hisilicon/hi6220_reset.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 0615f50..df37212 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER
> If unsure, say no.
>
> source "drivers/reset/sti/Kconfig"
> +source "drivers/reset/hisilicon/Kconfig"
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 157d421..331d7b2 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
> obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
> obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
> obj-$(CONFIG_ARCH_STI) += sti/
> +obj-$(CONFIG_ARCH_HISI) += hisilicon/
> diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
> new file mode 100644
> index 0000000..26bf95a
> --- /dev/null
> +++ b/drivers/reset/hisilicon/Kconfig
> @@ -0,0 +1,5 @@
> +config COMMON_RESET_HI6220
> + tristate "Hi6220 Reset Driver"
> + depends on (ARCH_HISI && RESET_CONTROLLER)
> + help
> + Build the Hisilicon Hi6220 reset driver.
> diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
> new file mode 100644
> index 0000000..c932f86
> --- /dev/null
> +++ b/drivers/reset/hisilicon/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
> diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c
> new file mode 100644
> index 0000000..097133d
> --- /dev/null
> +++ b/drivers/reset/hisilicon/hi6220_reset.c
> @@ -0,0 +1,118 @@
> +/*
> + * Hisilicon Hi6220 reset controller driver
> + *
> + * Copyright (c) 2015 Hisilicon Limited.
> + *
> + * Author: Feng Chen <puck.chen@hisilicon.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/bitops.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/reset-controller.h>
> +#include <linux/reset.h>
> +#include <linux/sizes.h>
> +#include <linux/slab.h>
> +
> +#define ASSET_OFFSET 0x300
> +#define DEASSET_OFFSET 0x304
> +
> +struct hi6220_reset_data {
> + spinlock_t reset_lock; /*device spin-lock*/
> + void __iomem *src_base;
> + void __iomem *asset_base;
> + void __iomem *deasset_base;
> + struct reset_controller_dev rc_dev;
> +};
> +
> +static int hi6220_reset_assert(struct reset_controller_dev *rc_dev,
> + unsigned long idx)
> +{
> + struct hi6220_reset_data *data = container_of(rc_dev,
> + struct hi6220_reset_data,
> + rc_dev);
> +
> + unsigned long flags;
> + int bank = idx >> 8;
> + int offset = idx & 0xff;
> +
> + spin_lock_irqsave(&data->reset_lock, flags);
the spin_lock looks useless.
it is not a "read and write" register.
> + writel(BIT(offset), data->asset_base + (bank * 0x10));
> +
> + spin_unlock_irqrestore(&data->reset_lock, flags);
> +
> + return 0;
> +}
> +
> +static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev,
> + unsigned long idx)
> +{
> + struct hi6220_reset_data *data = container_of(rc_dev,
> + struct hi6220_reset_data,
> + rc_dev);
> +
> + unsigned long flags;
> + int bank = idx >> 8;
> + int offset = idx & 0xff;
no need to check the idx scope ?
> + spin_lock_irqsave(&data->reset_lock, flags);
> +
> + writel(BIT(offset), data->deasset_base + (bank * 0x10));
> +
> + spin_unlock_irqrestore(&data->reset_lock, flags);
> +
> + return 0;
> +}
> +
> +static struct reset_control_ops hi6220_reset_ops = {
> + .assert = hi6220_reset_assert,
> + .deassert = hi6220_reset_deassert,
> +};
> +
> +static int __init hi6220_reset_init(void)
> +{
> + int ret;
> + struct device_node *np;
> + struct hi6220_reset_data *data;
> +
> + data = kzalloc(sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi6220_reset_ctl");
> + if (!np) {
> + ret = -ENXIO;
> + goto err_alloc;
> + }
> + spin_lock_init(&data->reset_lock);
> + data->src_base = of_iomap(np, 0);
> + if (!data->src_base) {
> + ret = -ENOMEM;
> + goto err_alloc;
> + }
> +
> + data->asset_base = data->src_base + ASSET_OFFSET;
> + data->deasset_base = data->src_base + DEASSET_OFFSET;
> + data->rc_dev.owner = THIS_MODULE;
> + data->rc_dev.nr_resets = SZ_4K;
> + data->rc_dev.ops = &hi6220_reset_ops;
> + data->rc_dev.of_node = np;
> +
> + if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
> + reset_controller_register(&data->rc_dev);
> +
> + return 0;
> +
> +err_alloc:
> + kfree(data);
> + return ret;
> +}
> +
> +postcore_initcall(hi6220_reset_init);
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V2 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC
@ 2015-09-12 6:06 ` xuyiping
0 siblings, 0 replies; 13+ messages in thread
From: xuyiping @ 2015-09-12 6:06 UTC (permalink / raw
To: Chen Feng, p.zabel, linux-kernel, robh+dt, pawel.moll, xuwei5,
haojian.zhuang, zhangfei.gao
Cc: bintian.wang, devicetree, dan.zhao, suzhuangluan, w.f
On 2015/9/11 16:18, Chen Feng wrote:
> Add reset driver for hi6220-hikey board,this driver supply deassert
> of IP. on hi6220 SoC.
>
> Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
> ---
> drivers/reset/Kconfig | 1 +
> drivers/reset/Makefile | 1 +
> drivers/reset/hisilicon/Kconfig | 5 ++
> drivers/reset/hisilicon/Makefile | 1 +
> drivers/reset/hisilicon/hi6220_reset.c | 118 +++++++++++++++++++++++++++++++++
> 5 files changed, 126 insertions(+)
> create mode 100644 drivers/reset/hisilicon/Kconfig
> create mode 100644 drivers/reset/hisilicon/Makefile
> create mode 100644 drivers/reset/hisilicon/hi6220_reset.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 0615f50..df37212 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER
> If unsure, say no.
>
> source "drivers/reset/sti/Kconfig"
> +source "drivers/reset/hisilicon/Kconfig"
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 157d421..331d7b2 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
> obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
> obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
> obj-$(CONFIG_ARCH_STI) += sti/
> +obj-$(CONFIG_ARCH_HISI) += hisilicon/
> diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
> new file mode 100644
> index 0000000..26bf95a
> --- /dev/null
> +++ b/drivers/reset/hisilicon/Kconfig
> @@ -0,0 +1,5 @@
> +config COMMON_RESET_HI6220
> + tristate "Hi6220 Reset Driver"
> + depends on (ARCH_HISI && RESET_CONTROLLER)
> + help
> + Build the Hisilicon Hi6220 reset driver.
> diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
> new file mode 100644
> index 0000000..c932f86
> --- /dev/null
> +++ b/drivers/reset/hisilicon/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
> diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c
> new file mode 100644
> index 0000000..097133d
> --- /dev/null
> +++ b/drivers/reset/hisilicon/hi6220_reset.c
> @@ -0,0 +1,118 @@
> +/*
> + * Hisilicon Hi6220 reset controller driver
> + *
> + * Copyright (c) 2015 Hisilicon Limited.
> + *
> + * Author: Feng Chen <puck.chen@hisilicon.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/bitops.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/reset-controller.h>
> +#include <linux/reset.h>
> +#include <linux/sizes.h>
> +#include <linux/slab.h>
> +
> +#define ASSET_OFFSET 0x300
> +#define DEASSET_OFFSET 0x304
> +
> +struct hi6220_reset_data {
> + spinlock_t reset_lock; /*device spin-lock*/
> + void __iomem *src_base;
> + void __iomem *asset_base;
> + void __iomem *deasset_base;
> + struct reset_controller_dev rc_dev;
> +};
> +
> +static int hi6220_reset_assert(struct reset_controller_dev *rc_dev,
> + unsigned long idx)
> +{
> + struct hi6220_reset_data *data = container_of(rc_dev,
> + struct hi6220_reset_data,
> + rc_dev);
> +
> + unsigned long flags;
> + int bank = idx >> 8;
> + int offset = idx & 0xff;
> +
> + spin_lock_irqsave(&data->reset_lock, flags);
the spin_lock looks useless.
it is not a "read and write" register.
> + writel(BIT(offset), data->asset_base + (bank * 0x10));
> +
> + spin_unlock_irqrestore(&data->reset_lock, flags);
> +
> + return 0;
> +}
> +
> +static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev,
> + unsigned long idx)
> +{
> + struct hi6220_reset_data *data = container_of(rc_dev,
> + struct hi6220_reset_data,
> + rc_dev);
> +
> + unsigned long flags;
> + int bank = idx >> 8;
> + int offset = idx & 0xff;
no need to check the idx scope ?
> + spin_lock_irqsave(&data->reset_lock, flags);
> +
> + writel(BIT(offset), data->deasset_base + (bank * 0x10));
> +
> + spin_unlock_irqrestore(&data->reset_lock, flags);
> +
> + return 0;
> +}
> +
> +static struct reset_control_ops hi6220_reset_ops = {
> + .assert = hi6220_reset_assert,
> + .deassert = hi6220_reset_deassert,
> +};
> +
> +static int __init hi6220_reset_init(void)
> +{
> + int ret;
> + struct device_node *np;
> + struct hi6220_reset_data *data;
> +
> + data = kzalloc(sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi6220_reset_ctl");
> + if (!np) {
> + ret = -ENXIO;
> + goto err_alloc;
> + }
> + spin_lock_init(&data->reset_lock);
> + data->src_base = of_iomap(np, 0);
> + if (!data->src_base) {
> + ret = -ENOMEM;
> + goto err_alloc;
> + }
> +
> + data->asset_base = data->src_base + ASSET_OFFSET;
> + data->deasset_base = data->src_base + DEASSET_OFFSET;
> + data->rc_dev.owner = THIS_MODULE;
> + data->rc_dev.nr_resets = SZ_4K;
> + data->rc_dev.ops = &hi6220_reset_ops;
> + data->rc_dev.of_node = np;
> +
> + if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
> + reset_controller_register(&data->rc_dev);
> +
> + return 0;
> +
> +err_alloc:
> + kfree(data);
> + return ret;
> +}
> +
> +postcore_initcall(hi6220_reset_init);
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V2 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC
2015-09-11 8:41 ` Arnd Bergmann
@ 2015-09-14 2:02 ` chenfeng
0 siblings, 0 replies; 13+ messages in thread
From: chenfeng @ 2015-09-14 2:02 UTC (permalink / raw
To: Arnd Bergmann
Cc: p.zabel, linux-kernel, robh+dt, pawel.moll, xuwei5,
haojian.zhuang, zhangfei.gao, xuyiping, bintian.wang, devicetree,
dan.zhao, suzhuangluan, w.f
On 2015/9/11 16:41, Arnd Bergmann wrote:
> On Friday 11 September 2015 16:18:38 Chen Feng wrote:
>> +static int __init hi6220_reset_init(void)
>> +{
>> + int ret;
>> + struct device_node *np;
>> + struct hi6220_reset_data *data;
>> +
>> + data = kzalloc(sizeof(*data), GFP_KERNEL);
>> + if (!data)
>> + return -ENOMEM;
>> +
>> + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi6220_reset_ctl");
>> + if (!np) {
>> + ret = -ENXIO;
>> + goto err_alloc;
>> + }
>
> Why is this not a platform driver?
>
OK,I will change this to a platform driver.
>> + if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
>> + reset_controller_register(&data->rc_dev);
>> +
>> + return 0;
>
> The Kconfig symbol already depends on RESET_CONTROLLER, so
> the IS_ENABLED() check looks redundant.
>
Yes,agree with you.
> Arnd
>
> .
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V2 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC
@ 2015-09-14 2:02 ` chenfeng
0 siblings, 0 replies; 13+ messages in thread
From: chenfeng @ 2015-09-14 2:02 UTC (permalink / raw
To: Arnd Bergmann
Cc: p.zabel, linux-kernel, robh+dt, pawel.moll, xuwei5,
haojian.zhuang, zhangfei.gao, xuyiping, bintian.wang, devicetree,
dan.zhao, suzhuangluan, w.f
On 2015/9/11 16:41, Arnd Bergmann wrote:
> On Friday 11 September 2015 16:18:38 Chen Feng wrote:
>> +static int __init hi6220_reset_init(void)
>> +{
>> + int ret;
>> + struct device_node *np;
>> + struct hi6220_reset_data *data;
>> +
>> + data = kzalloc(sizeof(*data), GFP_KERNEL);
>> + if (!data)
>> + return -ENOMEM;
>> +
>> + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi6220_reset_ctl");
>> + if (!np) {
>> + ret = -ENXIO;
>> + goto err_alloc;
>> + }
>
> Why is this not a platform driver?
>
OK,I will change this to a platform driver.
>> + if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
>> + reset_controller_register(&data->rc_dev);
>> +
>> + return 0;
>
> The Kconfig symbol already depends on RESET_CONTROLLER, so
> the IS_ENABLED() check looks redundant.
>
Yes,agree with you.
> Arnd
>
> .
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V2 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC
@ 2015-09-14 2:02 ` chenfeng
0 siblings, 0 replies; 13+ messages in thread
From: chenfeng @ 2015-09-14 2:02 UTC (permalink / raw
To: xuyiping, p.zabel, linux-kernel, robh+dt, pawel.moll, xuwei5,
haojian.zhuang, zhangfei.gao
Cc: bintian.wang, devicetree, dan.zhao, suzhuangluan, w.f
On 2015/9/12 14:06, xuyiping wrote:
>
>
> On 2015/9/11 16:18, Chen Feng wrote:
>> Add reset driver for hi6220-hikey board,this driver supply deassert
>> of IP. on hi6220 SoC.
>>
>> Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
>> ---
>> drivers/reset/Kconfig | 1 +
>> drivers/reset/Makefile | 1 +
>> drivers/reset/hisilicon/Kconfig | 5 ++
>> drivers/reset/hisilicon/Makefile | 1 +
>> drivers/reset/hisilicon/hi6220_reset.c | 118 +++++++++++++++++++++++++++++++++
>> 5 files changed, 126 insertions(+)
>> create mode 100644 drivers/reset/hisilicon/Kconfig
>> create mode 100644 drivers/reset/hisilicon/Makefile
>> create mode 100644 drivers/reset/hisilicon/hi6220_reset.c
>>
>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>> index 0615f50..df37212 100644
>> --- a/drivers/reset/Kconfig
>> +++ b/drivers/reset/Kconfig
>> @@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER
>> If unsure, say no.
>>
>> source "drivers/reset/sti/Kconfig"
>> +source "drivers/reset/hisilicon/Kconfig"
>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>> index 157d421..331d7b2 100644
>> --- a/drivers/reset/Makefile
>> +++ b/drivers/reset/Makefile
>> @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
>> obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
>> obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
>> obj-$(CONFIG_ARCH_STI) += sti/
>> +obj-$(CONFIG_ARCH_HISI) += hisilicon/
>> diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
>> new file mode 100644
>> index 0000000..26bf95a
>> --- /dev/null
>> +++ b/drivers/reset/hisilicon/Kconfig
>> @@ -0,0 +1,5 @@
>> +config COMMON_RESET_HI6220
>> + tristate "Hi6220 Reset Driver"
>> + depends on (ARCH_HISI && RESET_CONTROLLER)
>> + help
>> + Build the Hisilicon Hi6220 reset driver.
>> diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
>> new file mode 100644
>> index 0000000..c932f86
>> --- /dev/null
>> +++ b/drivers/reset/hisilicon/Makefile
>> @@ -0,0 +1 @@
>> +obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
>> diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c
>> new file mode 100644
>> index 0000000..097133d
>> --- /dev/null
>> +++ b/drivers/reset/hisilicon/hi6220_reset.c
>> @@ -0,0 +1,118 @@
>> +/*
>> + * Hisilicon Hi6220 reset controller driver
>> + *
>> + * Copyright (c) 2015 Hisilicon Limited.
>> + *
>> + * Author: Feng Chen <puck.chen@hisilicon.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/init.h>
>> +#include <linux/bitops.h>
>> +#include <linux/io.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/reset-controller.h>
>> +#include <linux/reset.h>
>> +#include <linux/sizes.h>
>> +#include <linux/slab.h>
>> +
>> +#define ASSET_OFFSET 0x300
>> +#define DEASSET_OFFSET 0x304
>> +
>> +struct hi6220_reset_data {
>> + spinlock_t reset_lock; /*device spin-lock*/
>> + void __iomem *src_base;
>> + void __iomem *asset_base;
>> + void __iomem *deasset_base;
>> + struct reset_controller_dev rc_dev;
>> +};
>> +
>> +static int hi6220_reset_assert(struct reset_controller_dev *rc_dev,
>> + unsigned long idx)
>> +{
>> + struct hi6220_reset_data *data = container_of(rc_dev,
>> + struct hi6220_reset_data,
>> + rc_dev);
>> +
>> + unsigned long flags;
>> + int bank = idx >> 8;
>> + int offset = idx & 0xff;
>> +
>> + spin_lock_irqsave(&data->reset_lock, flags);
>
> the spin_lock looks useless.
>
> it is not a "read and write" register.
>
>> + writel(BIT(offset), data->asset_base + (bank * 0x10));
>> +
>> + spin_unlock_irqrestore(&data->reset_lock, flags);
>> +
>> + return 0;
>> +}
>> +
>> +static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev,
>> + unsigned long idx)
>> +{
>> + struct hi6220_reset_data *data = container_of(rc_dev,
>> + struct hi6220_reset_data,
>> + rc_dev);
>> +
>> + unsigned long flags;
>> + int bank = idx >> 8;
>> + int offset = idx & 0xff;
>
> no need to check the idx scope ?
>
Yes, I think this has already been checked at reset framework.
>> + spin_lock_irqsave(&data->reset_lock, flags);
>> +
>> + writel(BIT(offset), data->deasset_base + (bank * 0x10));
>> +
>> + spin_unlock_irqrestore(&data->reset_lock, flags);
>> +
>> + return 0;
>> +}
>> +
>> +static struct reset_control_ops hi6220_reset_ops = {
>> + .assert = hi6220_reset_assert,
>> + .deassert = hi6220_reset_deassert,
>> +};
>> +
>> +static int __init hi6220_reset_init(void)
>> +{
>> + int ret;
>> + struct device_node *np;
>> + struct hi6220_reset_data *data;
>> +
>> + data = kzalloc(sizeof(*data), GFP_KERNEL);
>> + if (!data)
>> + return -ENOMEM;
>> +
>> + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi6220_reset_ctl");
>> + if (!np) {
>> + ret = -ENXIO;
>> + goto err_alloc;
>> + }
>> + spin_lock_init(&data->reset_lock);
>> + data->src_base = of_iomap(np, 0);
>> + if (!data->src_base) {
>> + ret = -ENOMEM;
>> + goto err_alloc;
>> + }
>> +
>> + data->asset_base = data->src_base + ASSET_OFFSET;
>> + data->deasset_base = data->src_base + DEASSET_OFFSET;
>> + data->rc_dev.owner = THIS_MODULE;
>> + data->rc_dev.nr_resets = SZ_4K;
>> + data->rc_dev.ops = &hi6220_reset_ops;
>> + data->rc_dev.of_node = np;
>> +
>> + if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
>> + reset_controller_register(&data->rc_dev);
>> +
>> + return 0;
>> +
>> +err_alloc:
>
>
>
>> + kfree(data);
>> + return ret;
>> +}
>> +
>> +postcore_initcall(hi6220_reset_init);
>>
>
>
> .
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V2 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC
@ 2015-09-14 2:02 ` chenfeng
0 siblings, 0 replies; 13+ messages in thread
From: chenfeng @ 2015-09-14 2:02 UTC (permalink / raw
To: xuyiping, p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q,
haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
zhangfei.gao-H32Fclmsjq1BDgjK7y7TUQ
Cc: bintian.wang-hv44wF8Li93QT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
dan.zhao-C8/M+/jPZTeaMJb+Lgu22Q,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q, w.f-hv44wF8Li93QT0dZR+AlfA
On 2015/9/12 14:06, xuyiping wrote:
>
>
> On 2015/9/11 16:18, Chen Feng wrote:
>> Add reset driver for hi6220-hikey board,this driver supply deassert
>> of IP. on hi6220 SoC.
>>
>> Signed-off-by: Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
>> ---
>> drivers/reset/Kconfig | 1 +
>> drivers/reset/Makefile | 1 +
>> drivers/reset/hisilicon/Kconfig | 5 ++
>> drivers/reset/hisilicon/Makefile | 1 +
>> drivers/reset/hisilicon/hi6220_reset.c | 118 +++++++++++++++++++++++++++++++++
>> 5 files changed, 126 insertions(+)
>> create mode 100644 drivers/reset/hisilicon/Kconfig
>> create mode 100644 drivers/reset/hisilicon/Makefile
>> create mode 100644 drivers/reset/hisilicon/hi6220_reset.c
>>
>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>> index 0615f50..df37212 100644
>> --- a/drivers/reset/Kconfig
>> +++ b/drivers/reset/Kconfig
>> @@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER
>> If unsure, say no.
>>
>> source "drivers/reset/sti/Kconfig"
>> +source "drivers/reset/hisilicon/Kconfig"
>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>> index 157d421..331d7b2 100644
>> --- a/drivers/reset/Makefile
>> +++ b/drivers/reset/Makefile
>> @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
>> obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
>> obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
>> obj-$(CONFIG_ARCH_STI) += sti/
>> +obj-$(CONFIG_ARCH_HISI) += hisilicon/
>> diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
>> new file mode 100644
>> index 0000000..26bf95a
>> --- /dev/null
>> +++ b/drivers/reset/hisilicon/Kconfig
>> @@ -0,0 +1,5 @@
>> +config COMMON_RESET_HI6220
>> + tristate "Hi6220 Reset Driver"
>> + depends on (ARCH_HISI && RESET_CONTROLLER)
>> + help
>> + Build the Hisilicon Hi6220 reset driver.
>> diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
>> new file mode 100644
>> index 0000000..c932f86
>> --- /dev/null
>> +++ b/drivers/reset/hisilicon/Makefile
>> @@ -0,0 +1 @@
>> +obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
>> diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c
>> new file mode 100644
>> index 0000000..097133d
>> --- /dev/null
>> +++ b/drivers/reset/hisilicon/hi6220_reset.c
>> @@ -0,0 +1,118 @@
>> +/*
>> + * Hisilicon Hi6220 reset controller driver
>> + *
>> + * Copyright (c) 2015 Hisilicon Limited.
>> + *
>> + * Author: Feng Chen <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/init.h>
>> +#include <linux/bitops.h>
>> +#include <linux/io.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/reset-controller.h>
>> +#include <linux/reset.h>
>> +#include <linux/sizes.h>
>> +#include <linux/slab.h>
>> +
>> +#define ASSET_OFFSET 0x300
>> +#define DEASSET_OFFSET 0x304
>> +
>> +struct hi6220_reset_data {
>> + spinlock_t reset_lock; /*device spin-lock*/
>> + void __iomem *src_base;
>> + void __iomem *asset_base;
>> + void __iomem *deasset_base;
>> + struct reset_controller_dev rc_dev;
>> +};
>> +
>> +static int hi6220_reset_assert(struct reset_controller_dev *rc_dev,
>> + unsigned long idx)
>> +{
>> + struct hi6220_reset_data *data = container_of(rc_dev,
>> + struct hi6220_reset_data,
>> + rc_dev);
>> +
>> + unsigned long flags;
>> + int bank = idx >> 8;
>> + int offset = idx & 0xff;
>> +
>> + spin_lock_irqsave(&data->reset_lock, flags);
>
> the spin_lock looks useless.
>
> it is not a "read and write" register.
>
>> + writel(BIT(offset), data->asset_base + (bank * 0x10));
>> +
>> + spin_unlock_irqrestore(&data->reset_lock, flags);
>> +
>> + return 0;
>> +}
>> +
>> +static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev,
>> + unsigned long idx)
>> +{
>> + struct hi6220_reset_data *data = container_of(rc_dev,
>> + struct hi6220_reset_data,
>> + rc_dev);
>> +
>> + unsigned long flags;
>> + int bank = idx >> 8;
>> + int offset = idx & 0xff;
>
> no need to check the idx scope ?
>
Yes, I think this has already been checked at reset framework.
>> + spin_lock_irqsave(&data->reset_lock, flags);
>> +
>> + writel(BIT(offset), data->deasset_base + (bank * 0x10));
>> +
>> + spin_unlock_irqrestore(&data->reset_lock, flags);
>> +
>> + return 0;
>> +}
>> +
>> +static struct reset_control_ops hi6220_reset_ops = {
>> + .assert = hi6220_reset_assert,
>> + .deassert = hi6220_reset_deassert,
>> +};
>> +
>> +static int __init hi6220_reset_init(void)
>> +{
>> + int ret;
>> + struct device_node *np;
>> + struct hi6220_reset_data *data;
>> +
>> + data = kzalloc(sizeof(*data), GFP_KERNEL);
>> + if (!data)
>> + return -ENOMEM;
>> +
>> + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi6220_reset_ctl");
>> + if (!np) {
>> + ret = -ENXIO;
>> + goto err_alloc;
>> + }
>> + spin_lock_init(&data->reset_lock);
>> + data->src_base = of_iomap(np, 0);
>> + if (!data->src_base) {
>> + ret = -ENOMEM;
>> + goto err_alloc;
>> + }
>> +
>> + data->asset_base = data->src_base + ASSET_OFFSET;
>> + data->deasset_base = data->src_base + DEASSET_OFFSET;
>> + data->rc_dev.owner = THIS_MODULE;
>> + data->rc_dev.nr_resets = SZ_4K;
>> + data->rc_dev.ops = &hi6220_reset_ops;
>> + data->rc_dev.of_node = np;
>> +
>> + if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
>> + reset_controller_register(&data->rc_dev);
>> +
>> + return 0;
>> +
>> +err_alloc:
>
>
>
>> + kfree(data);
>> + return ret;
>> +}
>> +
>> +postcore_initcall(hi6220_reset_init);
>>
>
>
> .
>
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^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2015-09-14 2:03 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-09-11 8:18 [PATCH V2 1/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC Chen Feng
2015-09-11 8:18 ` Chen Feng
2015-09-11 8:18 ` [PATCH V2 2/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings Chen Feng
2015-09-11 8:18 ` Chen Feng
2015-09-11 8:18 ` [PATCH V2 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC Chen Feng
2015-09-11 8:18 ` Chen Feng
2015-09-11 8:41 ` Arnd Bergmann
2015-09-14 2:02 ` chenfeng
2015-09-14 2:02 ` chenfeng
2015-09-12 6:06 ` xuyiping
2015-09-12 6:06 ` xuyiping
2015-09-14 2:02 ` chenfeng
2015-09-14 2:02 ` chenfeng
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