From: Dan Williams <dan.j.williams@intel.com>
To: <alison.schofield@intel.com>, Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>
Subject: Re: [PATCH 2/3] cxl/region: Verify target positions using the ordered target list
Date: Tue, 30 Apr 2024 15:59:54 -0700 [thread overview]
Message-ID: <663177ea1ca3_10c21294f5@dwillia2-mobl3.amr.corp.intel.com.notmuch> (raw)
In-Reply-To: <a5121a8d37dd62581015452a77113f88df2ede25.1714159486.git.alison.schofield@intel.com>
alison.schofield@ wrote:
> From: Alison Schofield <alison.schofield@intel.com>
>
> When a root decoder is configured the interleave target list is read
> from the BIOS populated CFMWS structure. Per the CXL spec 3.1 Table
> 9-22 the target list is in interleave order. The CXL driver populates
> its decoder target list in the same order and stores it in 'struct
> cxl_switch_decoder' field "@target: active ordered target list in
> current decoder configuration"
>
> Given the promise of an ordered list, the driver can stop duplicating
> the work of BIOS and simply check target positions against the ordered
> list during region configuration.
>
> The simplified check against the ordered list is presented here.
> A follow-on patch will remove the unused code.
>
> For Modulo arithmetic this is not a fix, only a simplification.
> For XOR arithmetic this is a fix for HB IW of 6,12.
>
> Fixes: f9db85bfec0d ("cxl/acpi: Support CXL XOR Interleave Math (CXIMS)")
> Signed-off-by: Alison Schofield <alison.schofield@intel.com>
> ---
> drivers/cxl/core/region.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 5c186e0a39b9..3c20f8364b26 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -1559,10 +1559,17 @@ static int cxl_region_attach_position(struct cxl_region *cxlr,
> const struct cxl_dport *dport, int pos)
> {
> struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> + struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd;
> + struct cxl_decoder *cxld = &cxlsd->cxld;
> + int iw = cxld->interleave_ways;
> struct cxl_port *iter;
> int rc;
>
> - if (cxlrd->calc_hb(cxlrd, pos) != dport) {
> + if (dev_WARN_ONCE(&cxld->dev, iw != cxlsd->nr_targets,
> + "misconfigured root decoder\n"))
> + return -ENXIO;
This is a nop because root-decoders by definition have all of their
targets covered in the interleave, and the driver passes the CFWMS
interleaves_ways setting directly to the @nr_targets parameter of
cxl_switch_decoder_init().
So drop this warning, which in retrospect was never needed , and it all
gets cleaned up in your next patch.
> +
> + if (dport != cxlrd->cxlsd.target[pos % iw]) {
Looks ok, but I don't understand why this patch is tagged as a fix?
There should be no end user visible change of this conversion, right?
next prev parent reply other threads:[~2024-04-30 23:00 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-26 19:51 [PATCH 0/3] XOR Math Fixups: translation & position alison.schofield
2024-04-26 19:51 ` [PATCH 1/3] cxl/acpi: Restore XOR'd position bits during address translation alison.schofield
2024-04-27 1:07 ` Dan Williams
2024-05-01 3:41 ` Alison Schofield
2024-05-01 5:00 ` Alison Schofield
2024-05-02 4:34 ` Alison Schofield
2024-04-26 19:51 ` [PATCH 2/3] cxl/region: Verify target positions using the ordered target list alison.schofield
2024-04-30 22:59 ` Dan Williams [this message]
2024-05-08 17:30 ` Alison Schofield
2024-04-26 19:51 ` [PATCH 3/3] cxl: Remove defunct code calculating host bridge target positions alison.schofield
2024-04-30 23:04 ` Dan Williams
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