From: "Chun-Jen Tseng (曾俊仁)" <Chun-Jen.Tseng@mediatek.com>
To: "viresh.kumar@linaro.org" <viresh.kumar@linaro.org>,
"AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>,
"rafael@kernel.org" <rafael@kernel.org>,
"myungjoo.ham@samsung.com" <myungjoo.ham@samsung.com>,
"kyungmin.park@samsung.com" <kyungmin.park@samsung.com>,
"cw00.choi@samsung.com" <cw00.choi@samsung.com>,
"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-mediatek@lists.infradead.org"
<linux-mediatek@lists.infradead.org>,
"linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 1/4] cpufreq: mediatek: CCI support SoC , the transition_delay set to 10 ms
Date: Fri, 14 Feb 2025 07:41:01 +0000 [thread overview]
Message-ID: <6b52c51f4046dda5d9aa3726e9be51c746e9c623.camel@mediatek.com> (raw)
In-Reply-To: <9f9a969f-6ce5-4e6c-89bd-51fe121db693@collabora.com>
On Thu, 2024-11-14 at 11:22 +0100, AngeloGioacchino Del Regno wrote:
hi Angelo,
Thanks your review and recommendation.
I will fix this issue on next patch.
BRs,
Mark Tseng
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>
>
> Il 08/11/24 07:39, Mark Tseng ha scritto:
> > SoC with CCI architecture should set transition_delay to 10 ms
> > because
> > cpufreq need to call devfreq notifier in async mode. if delay less
> > than
> > 10 ms, it may get wrong OPP-level in devfreq passive governor.
> >
>
> This means that MediaTek SoCs can change their CPU frequency once
> every
> 10 milliseconds?!?!?!
>
> I don't think that's really the case.
>
> Besides, are you aware that this will have a *huge* impact on either
> power
> consumption or performance?
> We're going from a bunch of microseconds to *multiple* milliseconds
> here.
>
> Regards,
> Angelo
>
next prev parent reply other threads:[~2025-02-14 7:41 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-08 6:39 [PATCH v2 0/4] fixed mediatek-cpufreq has multi policy concurrency issue Mark Tseng
2024-11-08 6:39 ` [PATCH v2 1/4] cpufreq: mediatek: CCI support SoC , the transition_delay set to 10 ms Mark Tseng
2024-11-14 10:22 ` AngeloGioacchino Del Regno
2025-02-14 7:41 ` Chun-Jen Tseng (曾俊仁) [this message]
2024-11-08 6:39 ` [PATCH v2 2/4] cpufreq: mediatek: using global lock avoid race condition Mark Tseng
2024-11-08 6:39 ` [PATCH v2 3/4] cpufreq: mediatek: Add CPUFREQ_ASYNC_NOTIFICATION flag Mark Tseng
2024-11-08 6:39 ` [PATCH v2 4/4] cpufreq: mediatek: data safety protect Mark Tseng
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=6b52c51f4046dda5d9aa3726e9be51c746e9c623.camel@mediatek.com \
--to=chun-jen.tseng@mediatek.com \
--cc=Project_Global_Chrome_Upstream_Group@mediatek.com \
--cc=angelogioacchino.delregno@collabora.com \
--cc=cw00.choi@samsung.com \
--cc=kyungmin.park@samsung.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=linux-pm@vger.kernel.org \
--cc=matthias.bgg@gmail.com \
--cc=myungjoo.ham@samsung.com \
--cc=rafael@kernel.org \
--cc=viresh.kumar@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.