From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752112AbbGOO2U (ORCPT ); Wed, 15 Jul 2015 10:28:20 -0400 Received: from mail-bn1on0087.outbound.protection.outlook.com ([157.56.110.87]:50880 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751468AbbGOO2S convert rfc822-to-8bit (ORCPT ); Wed, 15 Jul 2015 10:28:18 -0400 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; lists.infradead.org; dkim=none (message not signed) header.d=none; From: Ranjit Abhimanyu Waghmode To: Mark Brown CC: Michal Simek , Soren Brinkmann , "dwmw2@infradead.org" , "computersforpeace@gmail.com" , "zajec5@gmail.com" , "marex@denx.de" , "shijie.huang@intel.com" , "juhosg@openwrt.org" , "ben@decadent.org.uk" , "linux-mtd@lists.infradead.org" , "linux-spi@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Harini Katakam , "Punnaiah Choudary Kalluri" , "ran27jit@gmail.com" Subject: RE: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller Thread-Topic: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller Thread-Index: AQHQukU049LhNwab9kGRuWMzGe3Kwp3arNKAgAHtGCA= Date: Wed, 15 Jul 2015 14:12:54 +0000 Message-ID: <7CFCFE83B8145347A1D424EC939F1C3CA7E53D@XAP-PVEXMBX01.xlnx.xilinx.com> References: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> <20150714164005.GE11162@sirena.org.uk> In-Reply-To: <20150714164005.GE11162@sirena.org.uk> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.23.97.32] Content-Type: text/plain; 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How can we really represent the stacked mode in current configuration? Thanks & Regards, Ranjit From mboxrd@z Thu Jan 1 00:00:00 1970 From: ranjit.waghmode@xilinx.com (Ranjit Abhimanyu Waghmode) Date: Wed, 15 Jul 2015 14:12:54 +0000 Subject: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller In-Reply-To: <20150714164005.GE11162@sirena.org.uk> References: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> <20150714164005.GE11162@sirena.org.uk> Message-ID: <7CFCFE83B8145347A1D424EC939F1C3CA7E53D@XAP-PVEXMBX01.xlnx.xilinx.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Mark, > > What is dual parallel mode? > > --------------------------- > > ZynqMP GQSPI controller supports Dual Parallel mode with following > functionalities: > > 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines. > > 2) Chip selects and clock are shared to both the flash devices > > 3) This mode is targeted for faster read/write speed and also doubles the size > > 4) Commands/data can be transmitted/received from both the devices(mirror), > > or only upper or only lower flash memory devices. > > 5) Data arrangement: > > With stripe enabled, > > Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus > > Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus. > > For the SPI code this just seems like SPI with an 8 bit data width. > > > What is stacked mode? > > --------------------- > > ZynqMP GQSPI controller supports stacked mode with following > functionalities: > > 1) The Generic Quad-SPI controller also supports two SPI flash memories > > in a shared bus arrangement to reduce IO pin count. > > 2) Separate chip select lines > > 3) Shared I/O lines > > 4) This mode is targeted for increasing the flash memory and no performance > > improvement when compared with single. > > This is just a normal SPI controller from a SPI point of view. How can we really represent the stacked mode in current configuration? Thanks & Regards, Ranjit From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ranjit Abhimanyu Waghmode Subject: RE: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller Date: Wed, 15 Jul 2015 14:12:54 +0000 Message-ID: <7CFCFE83B8145347A1D424EC939F1C3CA7E53D@XAP-PVEXMBX01.xlnx.xilinx.com> References: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> <20150714164005.GE11162@sirena.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: "marex@denx.de" , Harini Katakam , "ben@decadent.org.uk" , "zajec5@gmail.com" , "linux-kernel@vger.kernel.org" , "linux-spi@vger.kernel.org" , "juhosg@openwrt.org" , Michal Simek , Soren Brinkmann , Punnaiah Choudary Kalluri , "shijie.huang@intel.com" , "linux-mtd@lists.infradead.org" , "ran27jit@gmail.com" , "computersforpeace@gmail.com" , "dwmw2@infradead.org" , "linux-arm-kernel@lists.infradead.org" To: Mark Brown Return-path: In-Reply-To: <20150714164005.GE11162@sirena.org.uk> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org List-Id: linux-spi.vger.kernel.org Hi Mark, > > What is dual parallel mode? > > --------------------------- > > ZynqMP GQSPI controller supports Dual Parallel mode with following > functionalities: > > 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines. > > 2) Chip selects and clock are shared to both the flash devices > > 3) This mode is targeted for faster read/write speed and also doubles the size > > 4) Commands/data can be transmitted/received from both the devices(mirror), > > or only upper or only lower flash memory devices. > > 5) Data arrangement: > > With stripe enabled, > > Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus > > Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus. > > For the SPI code this just seems like SPI with an 8 bit data width. > > > What is stacked mode? > > --------------------- > > ZynqMP GQSPI controller supports stacked mode with following > functionalities: > > 1) The Generic Quad-SPI controller also supports two SPI flash memories > > in a shared bus arrangement to reduce IO pin count. > > 2) Separate chip select lines > > 3) Shared I/O lines > > 4) This mode is targeted for increasing the flash memory and no performance > > improvement when compared with single. > > This is just a normal SPI controller from a SPI point of view. How can we really represent the stacked mode in current configuration? Thanks & Regards, Ranjit