From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754032AbbGPH1q (ORCPT ); Thu, 16 Jul 2015 03:27:46 -0400 Received: from mail-bn1on0086.outbound.protection.outlook.com ([157.56.110.86]:6496 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753789AbbGPH1l convert rfc822-to-8bit (ORCPT ); Thu, 16 Jul 2015 03:27:41 -0400 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; lists.infradead.org; dkim=none (message not signed) header.d=none; From: Ranjit Abhimanyu Waghmode To: Mark Brown CC: Michal Simek , Soren Brinkmann , "dwmw2@infradead.org" , "computersforpeace@gmail.com" , "zajec5@gmail.com" , "marex@denx.de" , "shijie.huang@intel.com" , "juhosg@openwrt.org" , "ben@decadent.org.uk" , "linux-mtd@lists.infradead.org" , "linux-spi@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Harini Katakam , "Punnaiah Choudary Kalluri" , "ran27jit@gmail.com" Subject: RE: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller Thread-Topic: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller Thread-Index: AQHQukU049LhNwab9kGRuWMzGe3Kwp3arNKAgAHtGCD//5qIAIABiFkg Date: Thu, 16 Jul 2015 07:27:34 +0000 Message-ID: <7CFCFE83B8145347A1D424EC939F1C3CA7E758@XAP-PVEXMBX01.xlnx.xilinx.com> References: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> <20150714164005.GE11162@sirena.org.uk> <7CFCFE83B8145347A1D424EC939F1C3CA7E53D@XAP-PVEXMBX01.xlnx.xilinx.com> <20150715160146.GS11162@sirena.org.uk> In-Reply-To: <20150715160146.GS11162@sirena.org.uk> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.23.17.67] Content-Type: text/plain; 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X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(3002001);SRVR:BL2FFO11HUB030;BCL:0;PCL:0;RULEID:;SRVR:BL2FFO11HUB030; X-Forefront-PRVS: 0639027A9E X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1;BL2FFO11HUB030;23:T9hV5q6Hu+Phy1+aGPzxCG1wujF9yitvy8Cz0tJr?= =?us-ascii?Q?ihgtaiX1av4SaawtGP3wm3el/AasjSE6sYkpEJZIXObVriwwtkSV2rGnNmHf?= =?us-ascii?Q?9M8S38fVCeD7lp2nyS3eZRXAvsR7i/NFU64HbeF9E5KcBhlGwlZm/E90dHuE?= =?us-ascii?Q?jxCj2VslVth3CUXpoziqj3iyH9aeltOOiZYgk0aOAF1GwNHBEARy14WRnuIB?= =?us-ascii?Q?ASWLOsEp1wDnhuwi+N01so1M5e8rmAuANBvmo2gxaAEmjPiIi5njUSvUXDdi?= =?us-ascii?Q?z8ABnliccS/f39X8Xp8eWcyesm7yIJ8qMTyOqNufurxMCT3NQPVt1zWm0mC8?= =?us-ascii?Q?IX0Dix6YV6FpJJZWv6ITvdS8pnIgZ6hV0DaFtQXKXSrwYjNtSSDq5uNy0x98?= =?us-ascii?Q?XG5XCtAdn14yGbPsztYeKh1IxThhZTsyosITCuS9qCeoVgm9wQ9pfkFrcobE?= =?us-ascii?Q?Sc4K42B8yEUgnmiFqbgdyxTa2IVcALNDgtjL8CPaYEKR1jhvyb9AdaLmduiX?= =?us-ascii?Q?UKfXdgj9VJiD1yU5yTfPOvbrd9UbXZrZEUx5caCaTSwaWCGFQsZOHmjbv/5t?= =?us-ascii?Q?keb6pILH72Z3TuUi7ZjM6AUblyk3WVJ43u1+laWoZ4tdQN8JKgcVQiM47zBH?= =?us-ascii?Q?ve3ojxFA5IUTmZq8v4c2GkOoQsUmkj2ZgVqqB33O8QeWHhaKgBjAV7wSgf+6?= =?us-ascii?Q?NngQGZB/+pccZbjQzHfDbn1lNICqS5lgGJ2p6gLLQ8siGuAo1TS3xQxMi88r?= =?us-ascii?Q?dJbG4JyB1lv865VFChkl7VH3fEjbF6FNA4JVtvusQsjfCfMK3jzmYqmCe079?= =?us-ascii?Q?FDjhY3FYveGPUipgp/pTDcZt9JOpR9UMKzZFToQpdf86+aJlqByOE5rGpuOy?= =?us-ascii?Q?MxyOvT9k7ggLViopM2D2Ds3wLwL5+SfbE3QtA+2dIItv/l1l5bg+IBhb9bFj?= =?us-ascii?Q?EQ2cZWAYDs+SPxbbozuPMbH9mG64z4BAns/M+or1owWaoX80Ca2Ao8KApyqa?= =?us-ascii?Q?u+g=3D?= X-Microsoft-Exchange-Diagnostics: 1;BL2FFO11HUB030;5:HVispUucFXTJNWSsMyUnrMHMq3NkN6o+e/2An7khndZ9vnD6+FRO6+JIb/hG0V5iSmeYIBlcEqTD72v7v8YZx5OF0JHMPAnUkPM5lnwKZrCKmQ627htoI24yO77DqeQb7/mwXRJk/1gpyl6UGNJThg==;24:Z2w+Z1P7bg9alLQjBZMIwq1UrbmgiTlryV/tSSGgq1oYK/yK8Vi2JUDP/8MG7R0ZiqHt/OgwDzUWHehIJ4PWRek9SNE4uPGlG4cpbIlx2Y4= X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jul 2015 07:27:38.5245 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2FFO11HUB030 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Mark, > > > > What is stacked mode? > > > > --------------------- > > > > ZynqMP GQSPI controller supports stacked mode with following > > > functionalities: > > > > 1) The Generic Quad-SPI controller also supports two SPI flash memories > > > > in a shared bus arrangement to reduce IO pin count. > > > > 2) Separate chip select lines > > > > 3) Shared I/O lines > > > > 4) This mode is targeted for increasing the flash memory and no > performance > > > > improvement when compared with single. > > > > This is just a normal SPI controller from a SPI point of view. > > > How can we really represent the stacked mode in current configuration? > > In the same way as any other controller with two chip selects... there are quite > a few other drivers that provide examples of this, you should look for one that > has hardware control similar to yours. Thanks Mark for your suggestion. But I have minor doubts. For an example take two flashes connected in stacked mode. For user it doesn't matter whether how many flashes are really connected. There will be situation like, single partition is spread across two flashes (partition staring at the end of one flash and continued to the second flash). But it has to be shown contiguous to user. In this scenario, I am not clear how MTD layer will handle the case. It would be great if you could just put some light on it. Regards, Ranjit From mboxrd@z Thu Jan 1 00:00:00 1970 From: ranjit.waghmode@xilinx.com (Ranjit Abhimanyu Waghmode) Date: Thu, 16 Jul 2015 07:27:34 +0000 Subject: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller In-Reply-To: <20150715160146.GS11162@sirena.org.uk> References: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> <20150714164005.GE11162@sirena.org.uk> <7CFCFE83B8145347A1D424EC939F1C3CA7E53D@XAP-PVEXMBX01.xlnx.xilinx.com> <20150715160146.GS11162@sirena.org.uk> Message-ID: <7CFCFE83B8145347A1D424EC939F1C3CA7E758@XAP-PVEXMBX01.xlnx.xilinx.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Mark, > > > > What is stacked mode? > > > > --------------------- > > > > ZynqMP GQSPI controller supports stacked mode with following > > > functionalities: > > > > 1) The Generic Quad-SPI controller also supports two SPI flash memories > > > > in a shared bus arrangement to reduce IO pin count. > > > > 2) Separate chip select lines > > > > 3) Shared I/O lines > > > > 4) This mode is targeted for increasing the flash memory and no > performance > > > > improvement when compared with single. > > > > This is just a normal SPI controller from a SPI point of view. > > > How can we really represent the stacked mode in current configuration? > > In the same way as any other controller with two chip selects... there are quite > a few other drivers that provide examples of this, you should look for one that > has hardware control similar to yours. Thanks Mark for your suggestion. But I have minor doubts. For an example take two flashes connected in stacked mode. For user it doesn't matter whether how many flashes are really connected. There will be situation like, single partition is spread across two flashes (partition staring at the end of one flash and continued to the second flash). But it has to be shown contiguous to user. In this scenario, I am not clear how MTD layer will handle the case. It would be great if you could just put some light on it. Regards, Ranjit From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ranjit Abhimanyu Waghmode Subject: RE: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller Date: Thu, 16 Jul 2015 07:27:34 +0000 Message-ID: <7CFCFE83B8145347A1D424EC939F1C3CA7E758@XAP-PVEXMBX01.xlnx.xilinx.com> References: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> <20150714164005.GE11162@sirena.org.uk> <7CFCFE83B8145347A1D424EC939F1C3CA7E53D@XAP-PVEXMBX01.xlnx.xilinx.com> <20150715160146.GS11162@sirena.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Cc: Michal Simek , Soren Brinkmann , "dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org" , "computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org" , "zajec5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org" , "marex-ynQEQJNshbs@public.gmane.org" , "shijie.huang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org" , "juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org" , "ben-/+tVBieCtBitmTQ+vhA3Yw@public.gmane.org" , "linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Harini Katakam , "Punnaiah Choudary Kalluri" , "ran27jit-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org" To: Mark Brown Return-path: In-Reply-To: <20150715160146.GS11162-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> Content-Language: en-US Sender: linux-spi-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-ID: Hi Mark, > > > > What is stacked mode? > > > > --------------------- > > > > ZynqMP GQSPI controller supports stacked mode with following > > > functionalities: > > > > 1) The Generic Quad-SPI controller also supports two SPI flash memories > > > > in a shared bus arrangement to reduce IO pin count. > > > > 2) Separate chip select lines > > > > 3) Shared I/O lines > > > > 4) This mode is targeted for increasing the flash memory and no > performance > > > > improvement when compared with single. > > > > This is just a normal SPI controller from a SPI point of view. > > > How can we really represent the stacked mode in current configuration? > > In the same way as any other controller with two chip selects... there are quite > a few other drivers that provide examples of this, you should look for one that > has hardware control similar to yours. Thanks Mark for your suggestion. But I have minor doubts. For an example take two flashes connected in stacked mode. For user it doesn't matter whether how many flashes are really connected. There will be situation like, single partition is spread across two flashes (partition staring at the end of one flash and continued to the second flash). But it has to be shown contiguous to user. In this scenario, I am not clear how MTD layer will handle the case. It would be great if you could just put some light on it. Regards, Ranjit -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html