* [PATCH 2/4] ARM: NOMMU: Postpone MPU activation till __after_proc_init
2018-02-12 11:19 [PATCH 0/4] Introduce PMSAv8 memory protection unit Vladimir Murzin
@ 2018-02-12 11:19 ` Vladimir Murzin
0 siblings, 0 replies; 3+ messages in thread
From: Vladimir Murzin @ 2018-02-12 11:19 UTC (permalink / raw
To: linux-arm-kernel
This patch postpone MPU activation till __after_proc_init (which is
placed in .text section) rather than doing it in __setup_mpu. It
allows us ignore used-only-once .head.text section while programming
PMSAv8 MPU (for PMSAv7 it stays covered anyway).
Tested-by: Szemz? Andr?s <sza@esh.hu>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
arch/arm/kernel/head-nommu.S | 45 ++++++++++++++++++++++----------------------
1 file changed, 22 insertions(+), 23 deletions(-)
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index aaa25a6..482936a 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -125,11 +125,24 @@ __secondary_data:
*/
.text
__after_proc_init:
+#ifdef CONFIG_ARM_MPU
+M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB)
+M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB)
+M_CLASS(ldr r3, [r12, 0x50])
+AR_CLASS(mrc p15, 0, r3, c0, c1, 4) @ Read ID_MMFR0
+ and r3, r3, #(MMFR0_PMSA) @ PMSA field
+ teq r3, #(MMFR0_PMSAv7) @ PMSA v7
+#endif
#ifdef CONFIG_CPU_CP15
/*
* CP15 system control register value returned in r0 from
* the CPU init function.
*/
+
+#ifdef CONFIG_ARM_MPU
+ biceq r0, r0, #CR_BR @ Disable the 'default mem-map'
+ orreq r0, r0, #CR_M @ Set SCTRL.M (MPU on)
+#endif
#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
orr r0, r0, #CR_A
#else
@@ -145,7 +158,15 @@ __after_proc_init:
bic r0, r0, #CR_I
#endif
mcr p15, 0, r0, c1, c0, 0 @ write control reg
+ isb
#elif defined (CONFIG_CPU_V7M)
+#ifdef CONFIG_ARM_MPU
+ ldreq r3, [r12, MPU_CTRL]
+ biceq r3, #MPU_CTRL_PRIVDEFENA
+ orreq r3, #MPU_CTRL_ENABLE
+ streq r3, [r12, MPU_CTRL]
+ isb
+#endif
/* For V7M systems we want to modify the CCR similarly to the SCTLR */
#ifdef CONFIG_CPU_DCACHE_DISABLE
bic r0, r0, #V7M_SCB_CCR_DC
@@ -156,9 +177,7 @@ __after_proc_init:
#ifdef CONFIG_CPU_ICACHE_DISABLE
bic r0, r0, #V7M_SCB_CCR_IC
#endif
- movw r3, #:lower16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
- movt r3, #:upper16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
- str r0, [r3]
+ str r0, [r12, V7M_SCB_CCR]
#endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */
ret lr
ENDPROC(__after_proc_init)
@@ -282,19 +301,6 @@ M_CLASS(ldr r0, [r12, #MPU_TYPE])
setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled
3: isb
#endif
-
- /* Enable the MPU */
-AR_CLASS(mrc p15, 0, r0, c1, c0, 0) @ Read SCTLR
-AR_CLASS(bic r0, r0, #CR_BR) @ Disable the 'default mem-map'
-AR_CLASS(orr r0, r0, #CR_M) @ Set SCTRL.M (MPU on)
-AR_CLASS(mcr p15, 0, r0, c1, c0, 0) @ Enable MPU
-
-M_CLASS(ldr r0, [r12, #MPU_CTRL])
-M_CLASS(bic r0, #MPU_CTRL_PRIVDEFENA)
-M_CLASS(orr r0, #MPU_CTRL_ENABLE)
-M_CLASS(str r0, [r12, #MPU_CTRL])
- isb
-
ret lr
ENDPROC(__setup_pmsa_v7)
@@ -352,13 +358,6 @@ ENTRY(__secondary_setup_pmsa_v7)
cmp r4, #0
bgt 1b
- /* Enable the MPU */
- mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
- bic r0, r0, #CR_BR @ Disable the 'default mem-map'
- orr r0, r0, #CR_M @ Set SCTRL.M (MPU on)
- mcr p15, 0, r0, c1, c0, 0 @ Enable MPU
- isb
-
ret lr
ENDPROC(__secondary_setup_pmsa_v7)
--
2.0.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/4] ARM: NOMMU: Postpone MPU activation till __after_proc_init
[not found] <a266d2d9-44dc-16aa-6b35-7bbda080c4ef@kernel.org>
@ 2018-06-18 9:52 ` Vladimir Murzin
2018-06-18 12:43 ` Greg Ungerer
0 siblings, 1 reply; 3+ messages in thread
From: Vladimir Murzin @ 2018-06-18 9:52 UTC (permalink / raw
To: linux-arm-kernel
On 18/06/18 02:20, Greg Ungerer wrote:
> Hi Vladimir,
Hi Greg,
>
> On 12/02/2018 11:19:31, Vladimir Murzin wrote:
>> This patch postpone MPU activation till __after_proc_init (which is
>> placed in .text section) rather than doing it in __setup_mpu. It
>> allows us ignore used-only-once .head.text section while programming
>> PMSAv8 MPU (for PMSAv7 it stays covered anyway).
>>
>> Tested-by: Szemz? Andr?s <sza@xxxxxx>
>> Signed-off-by: Vladimir Murzin <vladimir.murzin@xxxxxxx>
>> ---
>> ?arch/arm/kernel/head-nommu.S | 45 ++++++++++++++++++++++----------------------
>> ?1 file changed, 22 insertions(+), 23 deletions(-)
>>
>> diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
>> index aaa25a6..482936a 100644
>> --- a/arch/arm/kernel/head-nommu.S
>> +++ b/arch/arm/kernel/head-nommu.S
>> @@ -125,11 +125,24 @@ __secondary_data:
>> ? */
>> ???? .text
>> ?__after_proc_init:
>> +#ifdef CONFIG_ARM_MPU
>> +M_CLASS(movw??? r12, #:lower16:BASEADDR_V7M_SCB)
>> +M_CLASS(movt??? r12, #:upper16:BASEADDR_V7M_SCB)
>> +M_CLASS(ldr??? r3, [r12, 0x50])
>> +AR_CLASS(mrc??? p15, 0, r3, c0, c1, 4)????????? @ Read ID_MMFR0
>> +??? and??? r3, r3, #(MMFR0_PMSA)?????????? @ PMSA field
>> +??? teq??? r3, #(MMFR0_PMSAv7)???????????? @ PMSA v7
>> +#endif
>> ?#ifdef CONFIG_CPU_CP15
>> ???? /*
>> ????? * CP15 system control register value returned in r0 from
>> ????? * the CPU init function.
>> ????? */
>> +
>> +#ifdef CONFIG_ARM_MPU
>> +??? biceq??? r0, r0, #CR_BR??????????? @ Disable the 'default mem-map'
>> +??? orreq??? r0, r0, #CR_M??????????? @ Set SCTRL.M (MPU on)
>> +#endif
>> ?#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
>> ???? orr??? r0, r0, #CR_A
>> ?#else
>> @@ -145,7 +158,15 @@ __after_proc_init:
>> ???? bic??? r0, r0, #CR_I
>> ?#endif
>> ???? mcr??? p15, 0, r0, c1, c0, 0??????? @ write control reg
>> +??? isb
>
> This is causing breakage for me when building with my patches to
> support the old Versatile platform in no-MMU mode:
>
> ? AS????? arch/arm/kernel/head-nommu.o
> arch/arm/kernel/head-nommu.S: Assembler messages:
> arch/arm/kernel/head-nommu.S:180: Error: selected processor does not support `isb' in ARM mode
> scripts/Makefile.build:417: recipe for target 'arch/arm/kernel/head-nommu.o' failed
> make[2]: *** [arch/arm/kernel/head-nommu.o] Error 1
> Makefile:1034: recipe for target 'arch/arm/kernel' failed
> make[1]: *** [arch/arm/kernel] Error 2
>
> You may recall that patch series from some time back:
> https://www.spinics.net/lists/arm-kernel/msg547602.html
>
> That patch series is pretty much unchanged, and I am running it
> on top of linux-4.18-rc1, using a gcc-5.4.0 based toolchain.
> (I really need to make an effort again to push this further...)
>
> Is the "isb" instruction valid on ARM926T?
Thanks for report and sorry for causing you problems. I've just sent
a patch to address that which I've quickly tested with
qemu-system-arm -M versatilepb ...
sure your patches were applied.
Cheers
Vladimir
>
> Regards
> Greg
>
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 2/4] ARM: NOMMU: Postpone MPU activation till __after_proc_init
2018-06-18 9:52 ` [PATCH 2/4] ARM: NOMMU: Postpone MPU activation till __after_proc_init Vladimir Murzin
@ 2018-06-18 12:43 ` Greg Ungerer
0 siblings, 0 replies; 3+ messages in thread
From: Greg Ungerer @ 2018-06-18 12:43 UTC (permalink / raw
To: linux-arm-kernel
Hi Vladimir,
On 18/06/18 19:52, Vladimir Murzin wrote:
>> On 12/02/2018 11:19:31, Vladimir Murzin wrote:
>>> This patch postpone MPU activation till __after_proc_init (which is
>>> placed in .text section) rather than doing it in __setup_mpu. It
>>> allows us ignore used-only-once .head.text section while programming
>>> PMSAv8 MPU (for PMSAv7 it stays covered anyway).
>>>
>>> Tested-by: Szemz? Andr?s <sza@xxxxxx>
>>> Signed-off-by: Vladimir Murzin <vladimir.murzin@xxxxxxx>
>>> ---
>>> ?arch/arm/kernel/head-nommu.S | 45 ++++++++++++++++++++++----------------------
>>> ?1 file changed, 22 insertions(+), 23 deletions(-)
>>>
>>> diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
>>> index aaa25a6..482936a 100644
>>> --- a/arch/arm/kernel/head-nommu.S
>>> +++ b/arch/arm/kernel/head-nommu.S
>>> @@ -125,11 +125,24 @@ __secondary_data:
>>> ? */
>>> ???? .text
>>> ?__after_proc_init:
>>> +#ifdef CONFIG_ARM_MPU
>>> +M_CLASS(movw??? r12, #:lower16:BASEADDR_V7M_SCB)
>>> +M_CLASS(movt??? r12, #:upper16:BASEADDR_V7M_SCB)
>>> +M_CLASS(ldr??? r3, [r12, 0x50])
>>> +AR_CLASS(mrc??? p15, 0, r3, c0, c1, 4)????????? @ Read ID_MMFR0
>>> +??? and??? r3, r3, #(MMFR0_PMSA)?????????? @ PMSA field
>>> +??? teq??? r3, #(MMFR0_PMSAv7)???????????? @ PMSA v7
>>> +#endif
>>> ?#ifdef CONFIG_CPU_CP15
>>> ???? /*
>>> ????? * CP15 system control register value returned in r0 from
>>> ????? * the CPU init function.
>>> ????? */
>>> +
>>> +#ifdef CONFIG_ARM_MPU
>>> +??? biceq??? r0, r0, #CR_BR??????????? @ Disable the 'default mem-map'
>>> +??? orreq??? r0, r0, #CR_M??????????? @ Set SCTRL.M (MPU on)
>>> +#endif
>>> ?#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
>>> ???? orr??? r0, r0, #CR_A
>>> ?#else
>>> @@ -145,7 +158,15 @@ __after_proc_init:
>>> ???? bic??? r0, r0, #CR_I
>>> ?#endif
>>> ???? mcr??? p15, 0, r0, c1, c0, 0??????? @ write control reg
>>> +??? isb
>>
>> This is causing breakage for me when building with my patches to
>> support the old Versatile platform in no-MMU mode:
>>
>> ? AS????? arch/arm/kernel/head-nommu.o
>> arch/arm/kernel/head-nommu.S: Assembler messages:
>> arch/arm/kernel/head-nommu.S:180: Error: selected processor does not support `isb' in ARM mode
>> scripts/Makefile.build:417: recipe for target 'arch/arm/kernel/head-nommu.o' failed
>> make[2]: *** [arch/arm/kernel/head-nommu.o] Error 1
>> Makefile:1034: recipe for target 'arch/arm/kernel' failed
>> make[1]: *** [arch/arm/kernel] Error 2
>>
>> You may recall that patch series from some time back:
>> https://www.spinics.net/lists/arm-kernel/msg547602.html
>>
>> That patch series is pretty much unchanged, and I am running it
>> on top of linux-4.18-rc1, using a gcc-5.4.0 based toolchain.
>> (I really need to make an effort again to push this further...)
>>
>> Is the "isb" instruction valid on ARM926T?
>
> Thanks for report and sorry for causing you problems. I've just sent
> a patch to address that which I've quickly tested with
>
> qemu-system-arm -M versatilepb ...
>
> sure your patches were applied.
No problem. Thanks for the quick turn around. I tested the patch
and it fixes the problem for me. Runs perfectly under qemu in
my testing again now.
Thanks
Greg
^ permalink raw reply [flat|nested] 3+ messages in thread
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[not found] <a266d2d9-44dc-16aa-6b35-7bbda080c4ef@kernel.org>
2018-06-18 9:52 ` [PATCH 2/4] ARM: NOMMU: Postpone MPU activation till __after_proc_init Vladimir Murzin
2018-06-18 12:43 ` Greg Ungerer
2018-02-12 11:19 [PATCH 0/4] Introduce PMSAv8 memory protection unit Vladimir Murzin
2018-02-12 11:19 ` [PATCH 2/4] ARM: NOMMU: Postpone MPU activation till __after_proc_init Vladimir Murzin
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