From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751990AbdJ3C31 (ORCPT ); Sun, 29 Oct 2017 22:29:27 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:47568 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751388AbdJ3C3Z (ORCPT ); Sun, 29 Oct 2017 22:29:25 -0400 From: Marc Zyngier To: Stafford Horne Cc: LKML , Stefan Kristiansson , Thomas Gleixner , Jason Cooper , Rob Herring , Mark Rutland , Jonas Bonn , "David S. Miller" , Greg Kroah-Hartman , Mauro Carvalho Chehab , Randy Dunlap , devicetree@vger.kernel.org, openrisc@lists.librecores.org Subject: Re: [PATCH v4 05/13] irqchip: add initial support for ompic In-Reply-To: <20171029231123.27281-6-shorne@gmail.com> (Stafford Horne's message of "Mon, 30 Oct 2017 08:11:15 +0900") Organization: ARM Ltd References: <20171029231123.27281-1-shorne@gmail.com> <20171029231123.27281-6-shorne@gmail.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.1 (gnu/linux) Date: Mon, 30 Oct 2017 02:29:18 +0000 Message-ID: <86mv4974ht.fsf@arm.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 30 2017 at 8:11:15 am GMT, Stafford Horne wrote: > From: Stefan Kristiansson > > IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as > described in the Multi-core support section of the OpenRISC 1.2 > architecture specification: > > https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf > > Each OpenRISC core contains a full interrupt controller which is used in > the SMP architecture for interrupt balancing. This IPI device, the > ompic, is the only external device required for enabling SMP on > OpenRISC. > > Pending ops are stored in a memory bit mask which can allow multiple > pending operations to be set and serviced at a time. This is mostly > borrowed from the alpha IPI implementation. > > Cc: Marc Zyngier > Acked-by: Rob Herring > Signed-off-by: Stefan Kristiansson > [shorne@gmail.com: converted ops to bitmask, wrote commit message] > Signed-off-by: Stafford Horne Reviewed-by: Marc Zyngier Side question: what is your merge strategy for this? I can take it through the irqchip tree as it is standalone, but I'm open to other suggestions. Thanks, M. -- Jazz is not dead. It just smells funny. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Subject: Re: [PATCH v4 05/13] irqchip: add initial support for ompic Date: Mon, 30 Oct 2017 02:29:18 +0000 Message-ID: <86mv4974ht.fsf@arm.com> References: <20171029231123.27281-1-shorne@gmail.com> <20171029231123.27281-6-shorne@gmail.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <20171029231123.27281-6-shorne-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> (Stafford Horne's message of "Mon, 30 Oct 2017 08:11:15 +0900") Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Stafford Horne Cc: LKML , Stefan Kristiansson , Thomas Gleixner , Jason Cooper , Rob Herring , Mark Rutland , Jonas Bonn , "David S. Miller" , Greg Kroah-Hartman , Mauro Carvalho Chehab , Randy Dunlap , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, openrisc-cunTk1MwBs9a3B2Vnqf2dGD2FQJk+8+b@public.gmane.org List-Id: devicetree@vger.kernel.org On Mon, Oct 30 2017 at 8:11:15 am GMT, Stafford Horne wrote: > From: Stefan Kristiansson > > IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as > described in the Multi-core support section of the OpenRISC 1.2 > architecture specification: > > https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf > > Each OpenRISC core contains a full interrupt controller which is used in > the SMP architecture for interrupt balancing. This IPI device, the > ompic, is the only external device required for enabling SMP on > OpenRISC. > > Pending ops are stored in a memory bit mask which can allow multiple > pending operations to be set and serviced at a time. This is mostly > borrowed from the alpha IPI implementation. > > Cc: Marc Zyngier > Acked-by: Rob Herring > Signed-off-by: Stefan Kristiansson > [shorne-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org: converted ops to bitmask, wrote commit message] > Signed-off-by: Stafford Horne Reviewed-by: Marc Zyngier Side question: what is your merge strategy for this? I can take it through the irqchip tree as it is standalone, but I'm open to other suggestions. Thanks, M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Date: Mon, 30 Oct 2017 02:29:18 +0000 Subject: [OpenRISC] [PATCH v4 05/13] irqchip: add initial support for ompic In-Reply-To: <20171029231123.27281-6-shorne@gmail.com> (Stafford Horne's message of "Mon, 30 Oct 2017 08:11:15 +0900") References: <20171029231123.27281-1-shorne@gmail.com> <20171029231123.27281-6-shorne@gmail.com> Message-ID: <86mv4974ht.fsf@arm.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: openrisc@lists.librecores.org On Mon, Oct 30 2017 at 8:11:15 am GMT, Stafford Horne wrote: > From: Stefan Kristiansson > > IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as > described in the Multi-core support section of the OpenRISC 1.2 > architecture specification: > > https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf > > Each OpenRISC core contains a full interrupt controller which is used in > the SMP architecture for interrupt balancing. This IPI device, the > ompic, is the only external device required for enabling SMP on > OpenRISC. > > Pending ops are stored in a memory bit mask which can allow multiple > pending operations to be set and serviced at a time. This is mostly > borrowed from the alpha IPI implementation. > > Cc: Marc Zyngier > Acked-by: Rob Herring > Signed-off-by: Stefan Kristiansson > [shorne at gmail.com: converted ops to bitmask, wrote commit message] > Signed-off-by: Stafford Horne Reviewed-by: Marc Zyngier Side question: what is your merge strategy for this? I can take it through the irqchip tree as it is standalone, but I'm open to other suggestions. Thanks, M. -- Jazz is not dead. It just smells funny.