From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
To: Ryan.Wanner@microchip.com, lee@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, sre@kernel.org,
nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com,
p.zabel@pengutronix.de
Cc: linux@armlinux.org.uk, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-rtc@vger.kernel.org,
Li Bin <bin.li@microchip.com>,
Durai Manickam KR <durai.manickamkr@microchip.com>,
Andrei Simion <andrei.simion@microchip.com>
Subject: Re: [PATCH v2 09/15] ARM: at91: pm: fix at91_suspend_finish for ZQ calibration
Date: Wed, 12 Feb 2025 10:17:32 +0200 [thread overview]
Message-ID: <8ad7636f-af6d-417f-8801-66530ff67c1f@tuxon.dev> (raw)
In-Reply-To: <4e685b1f1828b006cb60aa6b66239f2c0966501a.1739221064.git.Ryan.Wanner@microchip.com>
Hi, Ryan,
On 10.02.2025 23:13, Ryan.Wanner@microchip.com wrote:
> From: Li Bin <bin.li@microchip.com>
>
> For sama7g5 and sama7d65 backup mode, we encountered a "ZQ calibrate error"
> during recalibrating the impedance in BootStrap.
> We found that the impedance value saved in at91_suspend_finish() before
> the DDR entered self-refresh mode did not match the resistor values. The
> ZDATA field in the DDR3PHY_ZQ0CR0 register uses a modified gray code to
> select the different impedance setting.
> But these gray code are incorrect, a workaournd from design team fixed the
> bug in the calibration logic. The ZDATA contains four independent impedance
> elements, but the algorithm combined the four elements into one. The elements
> were fixed using properly shifted offsets.
>
> Signed-off-by: Li Bin <bin.li@microchip.com>
> [nicolas.ferre@microchip.com: fix indentation and combine 2 patches]
> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> Tested-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> Tested-by: Durai Manickam KR <durai.manickamkr@microchip.com>
> Tested-by: Andrei Simion <andrei.simion@microchip.com>
Missing your SoB tag.
> ---
> arch/arm/mach-at91/pm.c | 21 +++++++++++----------
> 1 file changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index 05a1547642b60..6c3e6aa22606f 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -545,11 +545,12 @@ extern u32 at91_pm_suspend_in_sram_sz;
>
> static int at91_suspend_finish(unsigned long val)
> {
> - unsigned char modified_gray_code[] = {
> - 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d,
> - 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b,
> - 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13,
> - 0x10, 0x11,
> + /* SYNOPSYS workaround to fix a bug in the calibration logic */
> + unsigned char modified_fix_code[] = {
> + 0x00, 0x01, 0x01, 0x06, 0x07, 0x0c, 0x06, 0x07, 0x0b, 0x18,
> + 0x0a, 0x0b, 0x0c, 0x0d, 0x0d, 0x0a, 0x13, 0x13, 0x12, 0x13,
> + 0x14, 0x15, 0x15, 0x12, 0x18, 0x19, 0x19, 0x1e, 0x1f, 0x14,
> + 0x1e, 0x1f,
> };
> unsigned int tmp, index;
> int i;
> @@ -560,25 +561,25 @@ static int at91_suspend_finish(unsigned long val)
> * restore the ZQ0SR0 with the value saved here. But the
> * calibration is buggy and restoring some values from ZQ0SR0
> * is forbidden and risky thus we need to provide processed
> - * values for these (modified gray code values).
> + * values for these.
> */
> tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0);
>
> /* Store pull-down output impedance select. */
> index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f;
> - soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index];
> + soc_pm.bu->ddr_phy_calibration[0] = modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDO_OFF;
>
> /* Store pull-up output impedance select. */
> index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f;
> - soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
> + soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PUO_OFF;
>
> /* Store pull-down on-die termination impedance select. */
> index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f;
> - soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
> + soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDODT_OFF;
>
> /* Store pull-up on-die termination impedance select. */
> index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f;
> - soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
> + soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SRO_PUODT_OFF;
>
> /*
> * The 1st 8 words of memory might get corrupted in the process
next prev parent reply other threads:[~2025-02-12 8:17 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-10 21:13 [PATCH v2 00/15] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
2025-02-10 21:13 ` [PATCH v2 01/15] dt-bindings: mfd: syscon: add microchip,sama7d65-ddr3phy Ryan.Wanner
2025-02-11 8:12 ` Krzysztof Kozlowski
2025-02-11 8:12 ` Krzysztof Kozlowski
2025-02-10 21:13 ` [PATCH v2 02/15] dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu Ryan.Wanner
2025-02-11 8:14 ` Krzysztof Kozlowski
2025-02-11 8:14 ` Krzysztof Kozlowski
2025-02-13 20:30 ` Conor Dooley
2025-02-13 20:30 ` Conor Dooley
2025-02-14 7:20 ` Krzysztof Kozlowski
2025-02-14 7:20 ` Krzysztof Kozlowski
2025-02-10 21:13 ` [PATCH v2 03/15] dt-bindings: sram: Add microchip,sama7d65-sram Ryan.Wanner
2025-02-10 21:13 ` [PATCH v2 04/15] dt-bindings: power: reset: atmel,sama5d2-shdwc: Add microchip,sama7d65-shdwc Ryan.Wanner
2025-02-10 21:13 ` [PATCH v2 05/15] dt-bindings: reset: atmel,at91sam9260-reset: add microchip,sama7d65-rstc Ryan.Wanner
2025-02-14 8:27 ` Krzysztof Kozlowski
2025-02-14 8:27 ` Krzysztof Kozlowski
2025-02-10 21:13 ` [PATCH v2 06/15] dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc Ryan.Wanner
2025-02-12 8:18 ` Claudiu Beznea
2025-02-14 8:27 ` Krzysztof Kozlowski
2025-02-14 8:27 ` Krzysztof Kozlowski
2025-02-10 21:13 ` [PATCH v2 07/15] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt Ryan.Wanner
2025-02-12 8:18 ` Claudiu Beznea
2025-02-14 8:28 ` Krzysztof Kozlowski
2025-02-14 8:28 ` Krzysztof Kozlowski
2025-02-10 21:13 ` [PATCH v2 08/15] ARM: at91: Add PM support to sama7d65 Ryan.Wanner
2025-02-10 21:13 ` [PATCH v2 09/15] ARM: at91: pm: fix at91_suspend_finish for ZQ calibration Ryan.Wanner
2025-02-12 8:17 ` Claudiu Beznea [this message]
2025-02-10 21:13 ` [PATCH v2 10/15] ARM: at91: pm: add DT compatible support for sama7d65 Ryan.Wanner
2025-02-12 8:20 ` Claudiu Beznea
2025-02-10 21:13 ` [PATCH v2 11/15] ARM: at91: PM: Add Backup mode for SAMA7D65 Ryan.Wanner
2025-02-12 8:15 ` Claudiu Beznea
2025-02-10 21:13 ` [PATCH v2 12/15] ARM: at91: pm: Enable ULP0 " Ryan.Wanner
2025-02-13 8:20 ` Claudiu Beznea
2025-02-14 18:09 ` Ryan.Wanner
2025-02-17 7:18 ` Claudiu Beznea
2025-02-19 15:24 ` Ryan.Wanner
2025-02-24 8:55 ` Claudiu Beznea
2025-02-10 21:13 ` [PATCH v2 13/15] power: reset: at91-sama5d2_shdwc: Add sama7d65 PMC Ryan.Wanner
2025-02-12 8:20 ` Claudiu Beznea
2025-02-10 21:13 ` [PATCH v2 14/15] ARM: dts: microchip: sama7d65: Add Reset and Shutdown and PM support Ryan.Wanner
2025-02-13 8:28 ` Claudiu Beznea
2025-02-10 21:13 ` [PATCH v2 15/15] ARM: dts: microchip: add shutdown controller and rtt timer Ryan.Wanner
2025-02-13 8:30 ` Claudiu Beznea
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