* [PATCH] drm/amdgpu: add pmu counters
@ 2019-06-18 21:34 Kim, Jonathan
[not found] ` <20190618213348.4572-1-jonathan.kim-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: Kim, Jonathan @ 2019-06-18 21:34 UTC (permalink / raw
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; +Cc: Kim, Jonathan
v2: fixed missing break in switch statement
add pmu counters
Change-Id: I1aca271fd12cabce0ccfc076f771cde2d4cadd54
Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 302 +++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h | 37 +++
5 files changed, 349 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 57ce44cc3226..4c9fd2645f64 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -54,7 +54,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
amdgpu_gmc.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
- amdgpu_vm_sdma.o
+ amdgpu_vm_sdma.o amdgpu_pmu.o
# add asic specific block
amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4946d9ecc3e3..8ef2ac59ff04 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -962,6 +962,9 @@ struct amdgpu_device {
long compute_timeout;
uint64_t unique_id;
+
+ /* spin lock for pmu via perf events */
+ raw_spinlock_t pmu_lock;
};
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9d1b8d646661..7663c5d4d0e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -61,6 +61,7 @@
#include "amdgpu_xgmi.h"
#include "amdgpu_ras.h"
+#include "amdgpu_pmu.h"
MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
@@ -2746,6 +2747,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
return r;
}
+ r = amdgpu_pmu_init(adev);
+ if (r)
+ dev_err(adev->dev, "amdgpu_pmu_init failed\n");
+
return 0;
failed:
@@ -2814,6 +2819,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, &dev_attr_pcie_replay_count);
amdgpu_ucode_sysfs_fini(adev);
+ amdgpu_pmu_fini(adev);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
new file mode 100644
index 000000000000..cd45095bd815
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
@@ -0,0 +1,302 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jonathan Kim <jonathan.kim@amd.com>
+ *
+ */
+
+#include <linux/perf_event.h>
+#include <linux/init.h>
+#include "amdgpu.h"
+#include "amdgpu_pmu.h"
+#include "df_v3_6.h"
+
+#define PMU_NAME_SIZE 32
+
+/* record to keep track of pmu entry per pmu type per device */
+struct amdgpu_pmu_entry {
+ struct list_head entry;
+ struct amdgpu_device *adev;
+ struct pmu pmu;
+ unsigned int pmu_perf_type;
+};
+
+static LIST_HEAD(amdgpu_pmu_list);
+
+
+/* initialize perf counter */
+static int amdgpu_perf_event_init(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ /* test the event attr type check for PMU enumeration */
+ if (event->attr.type != event->pmu->type)
+ return -ENOENT;
+
+ /* update the hw_perf_event struct with config data */
+ hwc->conf = event->attr.config;
+
+ return 0;
+}
+
+/* start perf counter */
+static void amdgpu_perf_start(struct perf_event *event, int flags)
+{
+ unsigned long lflags;
+ struct hw_perf_event *hwc = &event->hw;
+ struct amdgpu_pmu_entry *pe = container_of(event->pmu,
+ struct amdgpu_pmu_entry,
+ pmu);
+
+ if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
+ return;
+
+ WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
+ hwc->state = 0;
+
+ raw_spin_lock_irqsave(&pe->adev->pmu_lock, lflags);
+
+ if (!(flags & PERF_EF_RELOAD))
+ pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 1);
+
+ pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 0);
+
+ raw_spin_unlock_irqrestore(&pe->adev->pmu_lock, lflags);
+
+ perf_event_update_userpage(event);
+
+}
+
+/* read perf counter */
+static void amdgpu_perf_read(struct perf_event *event)
+{
+ unsigned long lflags;
+ struct hw_perf_event *hwc = &event->hw;
+ struct amdgpu_pmu_entry *pe = container_of(event->pmu,
+ struct amdgpu_pmu_entry,
+ pmu);
+
+ u64 count, prev;
+
+ raw_spin_lock_irqsave(&pe->adev->pmu_lock, lflags);
+
+ switch (pe->pmu_perf_type) {
+ case PERF_TYPE_AMDGPU_DF:
+ pe->adev->df_funcs->pmc_get_count(pe->adev, hwc->conf, &count);
+ break;
+ default:
+ count = 0;
+ break;
+ };
+
+ pr_info("event %x has count %d\n", hwc->conf, count);
+
+ raw_spin_unlock_irqrestore(&pe->adev->pmu_lock, lflags);
+
+ prev = local64_read(&hwc->prev_count);
+ if (local64_cmpxchg(&hwc->prev_count, prev, count) != prev)
+ return;
+
+ local64_add(count - prev, &event->count);
+}
+
+/* stop perf counter */
+static void amdgpu_perf_stop(struct perf_event *event, int flags)
+{
+ unsigned long lflags;
+ struct hw_perf_event *hwc = &event->hw;
+ struct amdgpu_pmu_entry *pe = container_of(event->pmu,
+ struct amdgpu_pmu_entry,
+ pmu);
+
+ if (hwc->state & PERF_HES_UPTODATE)
+ return;
+
+ raw_spin_lock_irqsave(&pe->adev->pmu_lock, lflags);
+
+ switch (pe->pmu_perf_type) {
+ case PERF_TYPE_AMDGPU_DF:
+ pe->adev->df_funcs->pmc_stop(pe->adev, hwc->conf, 0);
+ break;
+ default:
+ break;
+ };
+
+ raw_spin_unlock_irqrestore(&pe->adev->pmu_lock, lflags);
+
+ WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
+ hwc->state |= PERF_HES_STOPPED;
+
+ if (hwc->state & PERF_HES_UPTODATE)
+ return;
+
+ amdgpu_perf_read(event);
+ hwc->state |= PERF_HES_UPTODATE;
+}
+
+/* add perf counter */
+static int amdgpu_perf_add(struct perf_event *event, int flags)
+{
+ unsigned long lflags;
+ struct hw_perf_event *hwc = &event->hw;
+ int retval;
+
+ struct amdgpu_pmu_entry *pe = container_of(event->pmu,
+ struct amdgpu_pmu_entry,
+ pmu);
+
+ event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+
+ raw_spin_lock_irqsave(&pe->adev->pmu_lock, lflags);
+
+ switch (pe->pmu_perf_type) {
+ case PERF_TYPE_AMDGPU_DF:
+ retval = pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 1);
+ break;
+ default:
+ return 0;
+ };
+
+ raw_spin_unlock_irqrestore(&pe->adev->pmu_lock, lflags);
+
+ if (retval)
+ return retval;
+
+ if (flags & PERF_EF_START)
+ amdgpu_perf_start(event, PERF_EF_RELOAD);
+
+ return retval;
+
+}
+
+/* delete perf counter */
+static void amdgpu_perf_del(struct perf_event *event, int flags)
+{
+ unsigned long lflags;
+ struct hw_perf_event *hwc = &event->hw;
+ struct amdgpu_pmu_entry *pe = container_of(event->pmu,
+ struct amdgpu_pmu_entry,
+ pmu);
+
+ amdgpu_perf_stop(event, PERF_EF_UPDATE);
+
+ raw_spin_lock_irqsave(&pe->adev->pmu_lock, lflags);
+
+ switch (pe->pmu_perf_type) {
+ case PERF_TYPE_AMDGPU_DF:
+ pe->adev->df_funcs->pmc_stop(pe->adev, hwc->conf, 1);
+ break;
+ default:
+ break;
+ };
+
+ raw_spin_unlock_irqrestore(&pe->adev->pmu_lock, lflags);
+
+ perf_event_update_userpage(event);
+}
+
+/* vega20 pmus */
+
+/* init pmu tracking per pmu type */
+int init_pmu_by_type(struct amdgpu_device *adev,
+ const struct attribute_group *attr_groups[],
+ char *pmu_type_name, char *pmu_file_prefix,
+ unsigned int pmu_perf_type)
+{
+ char pmu_name[PMU_NAME_SIZE];
+ struct amdgpu_pmu_entry *pmu_entry;
+ int ret = 0;
+
+ pmu_entry = kzalloc(sizeof(struct amdgpu_pmu_entry), GFP_KERNEL);
+
+ if (!pmu_entry)
+ return -ENOMEM;
+
+ pmu_entry->adev = adev;
+ pmu_entry->pmu = (struct pmu){
+ .event_init = amdgpu_perf_event_init,
+ .add = amdgpu_perf_add,
+ .del = amdgpu_perf_del,
+ .start = amdgpu_perf_start,
+ .stop = amdgpu_perf_stop,
+ .read = amdgpu_perf_read,
+ .task_ctx_nr = perf_invalid_context,
+ };
+
+ pmu_entry->pmu.attr_groups = attr_groups;
+ pmu_entry->pmu_perf_type = pmu_perf_type;
+ snprintf(pmu_name, PMU_NAME_SIZE, "%s_%d",
+ pmu_file_prefix, adev->ddev->primary->index);
+
+ ret = perf_pmu_register(&pmu_entry->pmu, pmu_name, -1);
+
+ if (ret) {
+ kfree(pmu_entry);
+ pr_warn("Error initializing AMDGPU %s PMUs.\n", pmu_type_name);
+ return ret;
+ }
+
+ raw_spin_lock_init(&pmu_entry->adev->pmu_lock);
+
+ pr_info("Detected AMDGPU %s Counters. # of Counters = %d.\n",
+ pmu_type_name, DF_V3_6_MAX_COUNTERS);
+
+ list_add_tail(&pmu_entry->entry, &amdgpu_pmu_list);
+
+ return 0;
+}
+
+/* init amdgpu_pmu */
+int amdgpu_pmu_init(struct amdgpu_device *adev)
+{
+
+ int ret = 0;
+
+ switch (adev->asic_type) {
+ case CHIP_VEGA20:
+ /* init df */
+ ret = init_pmu_by_type(adev, df_v3_6_attr_groups,
+ "DF", "amdgpu_df", PERF_TYPE_AMDGPU_DF);
+
+ /* other pmu types go here*/
+ break;
+ default:
+ return 0;
+ }
+
+ return 0;
+
+}
+
+
+/* destroy all pmu data associated with target device */
+void amdgpu_pmu_fini(struct amdgpu_device *adev)
+{
+ struct amdgpu_pmu_entry *pe, *temp;
+
+ list_for_each_entry_safe(pe, temp, &amdgpu_pmu_list, entry) {
+ if (pe->adev == adev) {
+ list_del(&pe->entry);
+ perf_pmu_unregister(&temp->pmu);
+ kfree(temp);
+ }
+ }
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
new file mode 100644
index 000000000000..7dddb7160a11
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jonathan Kim <jonathan.kim@amd.com>
+ *
+ */
+
+#ifndef _AMDGPU_PMU_H_
+#define _AMDGPU_PMU_H_
+
+enum amdgpu_pmu_perf_type {
+ PERF_TYPE_AMDGPU_DF = 0,
+ PERF_TYPE_AMDGPU_MAX
+};
+
+int amdgpu_pmu_init(struct amdgpu_device *adev);
+void amdgpu_pmu_fini(struct amdgpu_device *adev);
+
+#endif /* _AMDGPU_PMU_H_ */
--
2.17.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH] drm/amdgpu: add pmu counters
@ 2019-06-03 21:51 Kim, Jonathan
0 siblings, 0 replies; 7+ messages in thread
From: Kim, Jonathan @ 2019-06-03 21:51 UTC (permalink / raw
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; +Cc: Kim, Jonathan
add performance monitoring unit (pmu) counters.
Change-Id: I4d0480b8aaa8086a28b6a79a60322b060e1aa73e
Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 353 +++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h | 51 +++
4 files changed, 411 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 57ce44cc3226..4c9fd2645f64 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -54,7 +54,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
amdgpu_gmc.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
- amdgpu_vm_sdma.o
+ amdgpu_vm_sdma.o amdgpu_pmu.o
# add asic specific block
amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 003350a2d299..bcfabd025f5d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -61,6 +61,7 @@
#include "amdgpu_xgmi.h"
#include "amdgpu_ras.h"
+#include "amdgpu_pmu.h"
MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
@@ -2757,6 +2758,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
return r;
}
+ r = amdgpu_pmu_init(adev);
+ if (r)
+ dev_err(adev->dev, "amdgpu_pmu_init failed\n");
+
return 0;
failed:
@@ -2822,6 +2827,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, &dev_attr_pcie_replay_count);
amdgpu_ucode_sysfs_fini(adev);
+ amdgpu_pmu_fini(adev);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
new file mode 100644
index 000000000000..fe318914b07a
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
@@ -0,0 +1,353 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jonathan Kim <jonathan.kim@amd.com>
+ *
+ */
+
+#include <linux/perf_event.h>
+#include <linux/init.h>
+#include "amdgpu.h"
+#include "amdgpu_pmu.h"
+#include "df_v3_6.h"
+
+#define PMU_NAME_SIZE 32
+
+/* record to keep track of pmu entry per pmu type per device */
+struct amdgpu_pmu_entry {
+ struct list_head entry;
+ struct amdgpu_device *adev;
+ struct pmu pmu;
+ unsigned int pmu_perf_type;
+};
+
+static LIST_HEAD(amdgpu_pmu_list);
+
+/* vega20 attribute groups */
+
+/* data fabric (df) */
+
+/* init vega20 df format attrs */
+PMU_FORMAT_ATTR(event, "config:0-7");
+PMU_FORMAT_ATTR(instance, "config:8-15");
+PMU_FORMAT_ATTR(umask, "config:16-23");
+
+/* vega20 df format attributes */
+static struct attribute *amdgpu_vega20_df_format_attrs[] = {
+ &format_attr_event.attr,
+ &format_attr_instance.attr,
+ &format_attr_umask.attr,
+ NULL
+};
+
+/* vega20 df format attribute group */
+static struct attribute_group amdgpu_vega20_df_format_attr_group = {
+ .name = "format",
+ .attrs = amdgpu_vega20_df_format_attrs,
+};
+
+/* init vega20 df event attrs */
+AMDGPU_PMU_EVENT_ATTR(cake0_pcsout_txdata,
+ "event=0x7,instance=0x46,umask=0x2");
+AMDGPU_PMU_EVENT_ATTR(cake1_pcsout_txdata,
+ "event=0x7,instance=0x47,umask=0x2");
+AMDGPU_PMU_EVENT_ATTR(cake0_pcsout_txmeta,
+ "event=0x7,instance=0x46,umask=0x4");
+AMDGPU_PMU_EVENT_ATTR(cake1_pcsout_txmeta,
+ "event=0x7,instance=0x47,umask=0x4");
+AMDGPU_PMU_EVENT_ATTR(cake0_ftiinstat_reqalloc,
+ "event=0xb,instance=0x46,umask=0x4");
+AMDGPU_PMU_EVENT_ATTR(cake1_ftiinstat_reqalloc,
+ "event=0xb,instance=0x47,umask=0x4");
+AMDGPU_PMU_EVENT_ATTR(cake0_ftiinstat_rspalloc,
+ "event=0xb,instance=0x46,umask=0x8");
+AMDGPU_PMU_EVENT_ATTR(cake1_ftiinstat_rspalloc,
+ "event=0xb,instance=0x47,umask=0x8");
+
+/* vega20 df event attributes */
+static struct attribute *amdgpu_vega20_df_event_attrs[] = {
+ &event_attr_cake0_pcsout_txdata.attr,
+ &event_attr_cake1_pcsout_txdata.attr,
+ &event_attr_cake0_pcsout_txmeta.attr,
+ &event_attr_cake1_pcsout_txmeta.attr,
+ &event_attr_cake0_ftiinstat_reqalloc.attr,
+ &event_attr_cake1_ftiinstat_reqalloc.attr,
+ &event_attr_cake0_ftiinstat_rspalloc.attr,
+ &event_attr_cake1_ftiinstat_rspalloc.attr,
+ NULL
+};
+
+/* vega20 df event attribute group */
+static struct attribute_group amdgpu_vega20_df_event_attr_group = {
+ .name = "events",
+ .attrs = amdgpu_vega20_df_event_attrs
+};
+
+/* vega20 df event attr group */
+static const struct attribute_group *amdgpu_vega20_df_attr_groups[] = {
+ &amdgpu_vega20_df_format_attr_group,
+ &amdgpu_vega20_df_event_attr_group,
+ NULL
+};
+
+
+/* initialize perf counter */
+static int amdgpu_perf_event_init(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ /* test the event attr type check for PMU enumeration */
+ if (event->attr.type != event->pmu->type)
+ return -ENOENT;
+
+ /* update the hw_perf_event struct with config data */
+ hwc->conf = event->attr.config;
+
+ return 0;
+}
+
+/* start perf counter */
+static void amdgpu_perf_start(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct amdgpu_pmu_entry *pe = container_of(event->pmu,
+ struct amdgpu_pmu_entry,
+ pmu);
+
+ if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
+ return;
+
+ WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
+ hwc->state = 0;
+
+ if (!(flags & PERF_EF_RELOAD))
+ pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 1);
+
+ pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 0);
+
+ perf_event_update_userpage(event);
+
+}
+
+/* read perf counter */
+static void amdgpu_perf_read(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct amdgpu_pmu_entry *pe = container_of(event->pmu,
+ struct amdgpu_pmu_entry,
+ pmu);
+
+ u64 count, prev;
+
+ switch (pe->pmu_perf_type) {
+ case PERF_TYPE_AMDGPU_DF:
+ pe->adev->df_funcs->pmc_get_count(pe->adev, hwc->conf, &count);
+ default:
+ count = 0;
+ break;
+ };
+
+ prev = local64_read(&hwc->prev_count);
+ if (local64_cmpxchg(&hwc->prev_count, prev, count) != prev)
+ return;
+
+ local64_add(count - prev, &event->count);
+}
+
+/* stop perf counter */
+static void amdgpu_perf_stop(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct amdgpu_pmu_entry *pe = container_of(event->pmu,
+ struct amdgpu_pmu_entry,
+ pmu);
+
+ if (hwc->state & PERF_HES_UPTODATE)
+ return;
+
+ switch (pe->pmu_perf_type) {
+ case PERF_TYPE_AMDGPU_DF:
+ pe->adev->df_funcs->pmc_stop(pe->adev, hwc->conf, 0);
+ break;
+ default:
+ break;
+ };
+
+ WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
+ hwc->state |= PERF_HES_STOPPED;
+
+ if (hwc->state & PERF_HES_UPTODATE)
+ return;
+
+ amdgpu_perf_read(event);
+ hwc->state |= PERF_HES_UPTODATE;
+}
+
+/* add perf counter */
+static int amdgpu_perf_add(struct perf_event *event, int flags)
+{
+
+ struct hw_perf_event *hwc = &event->hw;
+ int retval;
+
+ struct amdgpu_pmu_entry *pe = container_of(event->pmu,
+ struct amdgpu_pmu_entry,
+ pmu);
+
+ event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+
+ switch (pe->pmu_perf_type) {
+ case PERF_TYPE_AMDGPU_DF:
+ retval = pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 1);
+ break;
+ default:
+ return 0;
+ };
+
+ if (retval)
+ return retval;
+
+ if (flags & PERF_EF_START)
+ amdgpu_perf_start(event, PERF_EF_RELOAD);
+
+ return retval;
+
+}
+
+/* delete perf counter */
+static void amdgpu_perf_del(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ struct amdgpu_pmu_entry *pe = container_of(event->pmu,
+ struct amdgpu_pmu_entry,
+ pmu);
+
+ amdgpu_perf_stop(event, PERF_EF_UPDATE);
+
+ switch (pe->pmu_perf_type) {
+ case PERF_TYPE_AMDGPU_DF:
+ pe->adev->df_funcs->pmc_stop(pe->adev, hwc->conf, 1);
+ break;
+ default:
+ break;
+ };
+
+ perf_event_update_userpage(event);
+}
+
+/* vega20 pmus */
+
+/* df pmu */
+static const struct pmu amdgpu_vega20_df_pmu __initconst = {
+ .event_init = amdgpu_perf_event_init,
+ .add = amdgpu_perf_add,
+ .del = amdgpu_perf_del,
+ .start = amdgpu_perf_start,
+ .stop = amdgpu_perf_stop,
+ .read = amdgpu_perf_read,
+ .task_ctx_nr = perf_invalid_context,
+ .attr_groups = amdgpu_vega20_df_attr_groups,
+};
+
+/* init pmu tracking per pmu type */
+int init_pmu_by_type(struct amdgpu_device *adev,
+ const struct attribute_group **attr_groups,
+ char *pmu_type_name, char *pmu_file_prefix,
+ unsigned int pmu_perf_type)
+{
+ char pmu_name[PMU_NAME_SIZE];
+ struct amdgpu_pmu_entry *pmu_entry;
+ int ret = 0;
+
+ pmu_entry = kzalloc(sizeof(struct amdgpu_pmu_entry), GFP_KERNEL);
+
+ if (!pmu_entry)
+ return -ENOMEM;
+
+ pmu_entry->adev = adev;
+ pmu_entry->pmu = (struct pmu){
+ .event_init = amdgpu_perf_event_init,
+ .add = amdgpu_perf_add,
+ .del = amdgpu_perf_del,
+ .start = amdgpu_perf_start,
+ .stop = amdgpu_perf_stop,
+ .read = amdgpu_perf_read,
+ .task_ctx_nr = perf_invalid_context,
+ };
+
+ pmu_entry->pmu.attr_groups = attr_groups;
+ pmu_entry->pmu_perf_type = pmu_perf_type;
+ snprintf(pmu_name, PMU_NAME_SIZE, "%s_%d",
+ pmu_file_prefix, adev->ddev->primary->index);
+
+ ret = perf_pmu_register(&pmu_entry->pmu, pmu_name, -1);
+
+ if (ret) {
+ kfree(pmu_entry);
+ pr_warn("Error initializing AMDGPU %s PMUs.\n", pmu_type_name);
+ return ret;
+ }
+
+ pr_info("Detected AMDGPU %s Counters. # of Counters = %d.\n",
+ pmu_type_name, AMDGPU_DF_MAX_COUNTERS);
+
+ list_add_tail(&pmu_entry->entry, &amdgpu_pmu_list);
+
+ return 0;
+}
+
+/* init amdgpu_pmu */
+int amdgpu_pmu_init(struct amdgpu_device *adev)
+{
+
+ int ret = 0;
+
+ switch (adev->asic_type) {
+ case CHIP_VEGA20:
+ /* init df */
+ ret = init_pmu_by_type(adev, amdgpu_vega20_df_attr_groups,
+ "DF", "amdgpu_df", PERF_TYPE_AMDGPU_DF);
+
+ /* other pmu types go here*/
+ break;
+ default:
+ return 0;
+ }
+
+ return 0;
+
+}
+
+
+/* destroy all pmu data associated with target device */
+void amdgpu_pmu_fini(struct amdgpu_device *adev)
+{
+ struct amdgpu_pmu_entry *pe, *temp;
+
+ list_for_each_entry_safe(pe, temp, &amdgpu_pmu_list, entry) {
+ if (pe->adev == adev) {
+ list_del(&pe->entry);
+ perf_pmu_unregister(&temp->pmu);
+ kfree(temp);
+ }
+ }
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
new file mode 100644
index 000000000000..46883a8c7c86
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jonathan Kim <jonathan.kim@amd.com>
+ *
+ */
+
+#ifndef _AMDGPU_PMU_H_
+#define _AMDGPU_PMU_H_
+
+enum amdgpu_pmu_perf_type {
+ PERF_TYPE_AMDGPU_DF = 0,
+ PERF_TYPE_AMDGPU_MAX
+};
+
+#define AMDGPU_PMU_EVENT_ATTR(_name, _event) \
+ \
+static ssize_t \
+_name##_show(struct kobject *kobj, \
+ struct kobj_attribute *attr, char *buf) \
+{ \
+ BUILD_BUG_ON(sizeof(_event) >= PAGE_SIZE); \
+ return sprintf(buf, "%s\n", _event); \
+} \
+ \
+static struct kobj_attribute event_attr_##_name = \
+ __ATTR(_name, 0444, _name##_show, NULL)
+
+
+int amdgpu_pmu_init(struct amdgpu_device *adev);
+void amdgpu_pmu_fini(struct amdgpu_device *adev);
+
+#endif /* _AMDGPU_PMU_H_ */
--
2.17.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH] drm/amdgpu: add pmu counters
@ 2019-05-29 15:02 Kim, Jonathan
[not found] ` <20190529150154.17375-1-jonathan.kim-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: Kim, Jonathan @ 2019-05-29 15:02 UTC (permalink / raw
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; +Cc: Kim, Jonathan
add pmu counters to monitor amdgpu device performance.
each pmu registered recorded per pmu type per asic type.
Change-Id: I8449f4ea824c411ee24a5b783ac066189b9de08e
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 394 +++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h | 37 ++
4 files changed, 437 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 11a651ff7f0d..90d4c5d299dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -54,7 +54,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
amdgpu_gmc.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
- amdgpu_vm_sdma.o
+ amdgpu_vm_sdma.o amdgpu_pmu.o
# add asic specific block
amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 582f5635fcb2..51f479b357a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -61,6 +61,7 @@
#include "amdgpu_xgmi.h"
#include "amdgpu_ras.h"
+#include "amdgpu_pmu.h"
MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
@@ -2748,6 +2749,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
goto failed;
}
+ r = amdgpu_pmu_init(adev);
+ if (r)
+ dev_err(adev->dev, "amdgpu_pmu_init failed\n");
+
/* must succeed. */
amdgpu_ras_resume(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
new file mode 100644
index 000000000000..39cff772dd9e
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
@@ -0,0 +1,394 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jonathan Kim <jonathan.kim@amd.com>
+ *
+ */
+
+#define pr_fmt(fmt) "perf/amdgpu_pmu: " fmt
+
+#include <linux/perf_event.h>
+#include <linux/init.h>
+#include <linux/cpumask.h>
+#include <linux/slab.h>
+#include "amdgpu.h"
+#include "amdgpu_pmu.h"
+#include "df_v3_6.h"
+
+#define PMU_NAME_SIZE 32
+
+/* record to keep track of pmu entry per pmu type per device */
+struct amdgpu_pmu_entry {
+ struct amdgpu_device *adev;
+ struct pmu pmu;
+ unsigned int pmu_perf_type;
+};
+
+PMU_FORMAT_ATTR(df_event, "config:0-7");
+PMU_FORMAT_ATTR(df_instance, "config:8-15");
+PMU_FORMAT_ATTR(df_unitmask, "config:16-23");
+
+/* df format attributes */
+static struct attribute *amdgpu_df_format_attrs[] = {
+ &format_attr_df_event.attr,
+ &format_attr_df_instance.attr,
+ &format_attr_df_unitmask.attr,
+ NULL
+};
+
+/* df format attribute group */
+static struct attribute_group amdgpu_df_format_attr_group = {
+ .name = "format",
+ .attrs = amdgpu_df_format_attrs,
+};
+
+/* df event attribute group */
+static struct attribute_group amdgpu_df_events_attr_group = {
+ .name = "events",
+};
+
+struct AMDGPU_PMU_EVENT_DESC {
+ struct kobj_attribute attr;
+ const char *event;
+};
+
+static ssize_t _pmu_event_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ struct AMDGPU_PMU_EVENT_DESC *event =
+ container_of(attr, struct AMDGPU_PMU_EVENT_DESC, attr);
+ return sprintf(buf, "%s\n", event->event);
+};
+
+#define AMDGPU_PMU_EVENT_DESC(_name, _event) \
+{ \
+ .attr = __ATTR(_name, 0444, _pmu_event_show, NULL), \
+ .event = _event, \
+}
+
+/* vega20 df events */
+static struct AMDGPU_PMU_EVENT_DESC amdgpu_vega20_df_event_descs[] = {
+ AMDGPU_PMU_EVENT_DESC(cake0_pcsout_txdata,
+ "df_event=0x7,df_instance=0x46,df_unitmask=0x2"),
+ AMDGPU_PMU_EVENT_DESC(cake1_pcsout_txdata,
+ "df_event=0x7,df_instance=0x47,df_unitmask=0x2"),
+ AMDGPU_PMU_EVENT_DESC(cake0_pcsout_txmeta,
+ "df_event=0x7,df_instance=0x46,df_unitmask=0x4"),
+ AMDGPU_PMU_EVENT_DESC(cake1_pcsout_txmeta,
+ "df_event=0x7,df_instance=0x47,df_unitmask=0x4"),
+ AMDGPU_PMU_EVENT_DESC(cake0_ftiinstat_reqalloc,
+ "df_event=0xb,df_instance=0x46,df_unitmask=0x4"),
+ AMDGPU_PMU_EVENT_DESC(cake1_ftiinstat_reqalloc,
+ "df_event=0xb,df_instance=0x47,df_unitmask=0x4"),
+ AMDGPU_PMU_EVENT_DESC(cake0_ftiinstat_rspalloc,
+ "df_event=0xb,df_instance=0x46,df_unitmask=0x8"),
+ AMDGPU_PMU_EVENT_DESC(cake1_ftiinstat_rspalloc,
+ "df_event=0xb,df_instance=0x47,df_unitmask=0x8"),
+ { /* end with zeros */ },
+};
+
+/* df attr group */
+const struct attribute_group *amdgpu_df_attr_groups[] = {
+ &amdgpu_df_format_attr_group,
+ &amdgpu_df_events_attr_group,
+ NULL
+};
+
+
+/* initialize perf counter */
+static int amdgpu_perf_event_init(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ /* test the event attr type check for PMU enumeration */
+ if (event->attr.type != event->pmu->type)
+ return -ENOENT;
+
+ /* update the hw_perf_event struct with config data */
+ hwc->conf = event->attr.config;
+
+ return 0;
+}
+
+/* start perf counter */
+static void amdgpu_perf_start(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct amdgpu_pmu_entry *pe = container_of(event->pmu,
+ struct amdgpu_pmu_entry,
+ pmu);
+
+ if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
+ return;
+
+ WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
+ hwc->state = 0;
+
+ if (!(flags & PERF_EF_RELOAD))
+ pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 1);
+
+ pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 0);
+
+ perf_event_update_userpage(event);
+
+}
+
+/* read perf counter */
+static void amdgpu_perf_read(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct amdgpu_pmu_entry *pe = container_of(event->pmu,
+ struct amdgpu_pmu_entry,
+ pmu);
+
+ u64 count, prev;
+
+ switch (pe->pmu_perf_type) {
+ case PERF_TYPE_AMDGPU_DF:
+ pe->adev->df_funcs->pmc_get_count(pe->adev, hwc->conf, &count);
+ default:
+ count = 0;
+ break;
+ };
+
+ prev = local64_read(&hwc->prev_count);
+ if (local64_cmpxchg(&hwc->prev_count, prev, count) != prev)
+ return;
+
+ local64_add(count - prev, &event->count);
+}
+
+/* stop perf counter */
+static void amdgpu_perf_stop(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct amdgpu_pmu_entry *pe = container_of(event->pmu,
+ struct amdgpu_pmu_entry,
+ pmu);
+
+ if (hwc->state & PERF_HES_UPTODATE)
+ return;
+
+ switch (pe->pmu_perf_type) {
+ case PERF_TYPE_AMDGPU_DF:
+ pe->adev->df_funcs->pmc_stop(pe->adev, hwc->conf, 0);
+ break;
+ default:
+ break;
+ };
+
+ WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
+ hwc->state |= PERF_HES_STOPPED;
+
+ if (hwc->state & PERF_HES_UPTODATE)
+ return;
+
+ amdgpu_perf_read(event);
+ hwc->state |= PERF_HES_UPTODATE;
+}
+
+/* add perf counter */
+static int amdgpu_perf_add(struct perf_event *event, int flags)
+{
+
+ struct hw_perf_event *hwc = &event->hw;
+ int retval;
+
+ struct amdgpu_pmu_entry *pe = container_of(event->pmu,
+ struct amdgpu_pmu_entry,
+ pmu);
+
+ event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+
+ switch (pe->pmu_perf_type) {
+ case PERF_TYPE_AMDGPU_DF:
+ retval = pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 1);
+ break;
+ default:
+ return 0;
+ };
+
+ if (retval)
+ return retval;
+
+ if (flags & PERF_EF_START)
+ amdgpu_perf_start(event, PERF_EF_RELOAD);
+
+ return retval;
+
+}
+
+/* delete perf counter */
+static void amdgpu_perf_del(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ struct amdgpu_pmu_entry *pe = container_of(event->pmu,
+ struct amdgpu_pmu_entry,
+ pmu);
+
+ amdgpu_perf_stop(event, PERF_EF_UPDATE);
+
+ switch (pe->pmu_perf_type) {
+ case PERF_TYPE_AMDGPU_DF:
+ pe->adev->df_funcs->pmc_stop(pe->adev, hwc->conf, 1);
+ break;
+ default:
+ break;
+ };
+
+ perf_event_update_userpage(event);
+}
+
+/* PMUs - pmus to register per pmu type per asic
+ *
+ * df_pmu - data fabric
+ *
+ */
+static const struct pmu df_pmu __initconst = {
+ .event_init = amdgpu_perf_event_init,
+ .add = amdgpu_perf_add,
+ .del = amdgpu_perf_del,
+ .start = amdgpu_perf_start,
+ .stop = amdgpu_perf_stop,
+ .read = amdgpu_perf_read,
+ .task_ctx_nr = perf_invalid_context,
+ .attr_groups = amdgpu_df_attr_groups,
+};
+
+/* initialize event attrs per pmu type per asic */
+static int amdgpu_pmu_set_attributes(struct amdgpu_device *adev,
+ unsigned int perf_type)
+{
+ struct attribute **attrs;
+ struct AMDGPU_PMU_EVENT_DESC *pmu_event_descs;
+ int i, j;
+
+ switch (perf_type) {
+ case PERF_TYPE_AMDGPU_DF:
+
+ switch (adev->asic_type) {
+ case CHIP_VEGA20:
+ pmu_event_descs = amdgpu_vega20_df_event_descs;
+ break;
+ default:
+ return -EINVAL;
+ };
+
+ i = 0;
+ while (pmu_event_descs[i].attr.attr.name)
+ i++;
+
+ attrs = kcalloc(i + 1, sizeof(struct attribute **), GFP_KERNEL);
+
+ if (!attrs)
+ return -ENOMEM;
+
+ for (j = 0; j < i; j++)
+ attrs[j] = &pmu_event_descs[j].attr.attr;
+
+ amdgpu_df_events_attr_group.attrs = attrs;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/* init pmu by type and keep record of pmu entry per asic */
+static int init_pmu_by_type(struct amdgpu_device *adev,
+ unsigned int pmu_type,
+ char *pmu_type_name,
+ char *pmu_file_name)
+{
+ char pmu_name[PMU_NAME_SIZE];
+ struct amdgpu_pmu_entry *pmu_entry;
+ int ret;
+
+ pmu_entry = kzalloc(sizeof(struct amdgpu_pmu_entry), GFP_KERNEL);
+
+ if (!pmu_entry)
+ return -ENOMEM;
+
+ ret = amdgpu_pmu_set_attributes(adev, pmu_type);
+ if (ret)
+ return ret;
+
+ switch (pmu_type) {
+ case PERF_TYPE_AMDGPU_DF:
+ pmu_entry->pmu = df_pmu;
+ break;
+ default:
+ kfree(pmu_entry);
+ return -EINVAL;
+ };
+
+ pmu_entry->adev = adev;
+ pmu_entry->pmu_perf_type = pmu_type;
+
+ snprintf(pmu_name, PMU_NAME_SIZE, "%s_%d",
+ pmu_file_name, adev->ddev->primary->index);
+
+ ret = perf_pmu_register(&pmu_entry->pmu, pmu_name, -1);
+
+ if (!ret) {
+ pr_info("Detected AMDGPU %s Counters. # of Counters = %d.\n",
+ pmu_type_name, AMDGPU_DF_MAX_COUNTERS);
+ } else {
+ kfree(pmu_entry);
+ pr_warn("Error initializing AMDGPU %s PMUs.\n", pmu_type_name);
+ }
+
+ return ret;
+}
+
+/* initialize pmu per asic per pmu type */
+static int init_pmu(struct amdgpu_device *adev)
+{
+ int retval = 0;
+
+ switch (adev->asic_type) {
+ case CHIP_VEGA20:
+ retval = init_pmu_by_type(adev, PERF_TYPE_AMDGPU_DF,
+ "DF", "amdgpu_df");
+ break;
+ default: /* ignore all other chips */
+ break;
+ }
+
+ return retval;
+}
+
+
+/* initialize amdgpu pmu */
+int amdgpu_pmu_init(struct amdgpu_device *adev)
+{
+ int ret;
+
+ ret = init_pmu(adev);
+
+ if (ret)
+ return -ENODEV;
+
+ return ret;
+}
+
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
new file mode 100644
index 000000000000..d070d9e252ff
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jonathan Kim <jonathan.kim@amd.com>
+ *
+ */
+
+#ifndef _AMDGPU_PMU_H_
+#define _AMDGPU_PMU_H_
+
+enum amdgpu_pmu_perf_type {
+ PERF_TYPE_AMDGPU_DF = 0,
+ PERF_TYPE_AMDGPU_MAX
+};
+
+
+int amdgpu_pmu_init(struct amdgpu_device *adev);
+
+#endif /* _AMDGPU_PMU_H_ */
--
2.17.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH] drm/amdgpu: add pmu counters
@ 2019-05-24 19:12 Kim, Jonathan
[not found] ` <20190524191229.84833-1-jonathan.kim-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: Kim, Jonathan @ 2019-05-24 19:12 UTC (permalink / raw
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; +Cc: Kim, Jonathan
add pmu counters to monitor amdgpu device performance
Change-Id: I8449f4ea824c411ee24a5b783ac066189b9de08e
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 370 +++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h | 37 +++
4 files changed, 413 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 11a651ff7f0d..90d4c5d299dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -54,7 +54,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
amdgpu_gmc.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
- amdgpu_vm_sdma.o
+ amdgpu_vm_sdma.o amdgpu_pmu.o
# add asic specific block
amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 582f5635fcb2..51f479b357a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -61,6 +61,7 @@
#include "amdgpu_xgmi.h"
#include "amdgpu_ras.h"
+#include "amdgpu_pmu.h"
MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
@@ -2748,6 +2749,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
goto failed;
}
+ r = amdgpu_pmu_init(adev);
+ if (r)
+ dev_err(adev->dev, "amdgpu_pmu_init failed\n");
+
/* must succeed. */
amdgpu_ras_resume(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
new file mode 100644
index 000000000000..b991e988d6fa
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
@@ -0,0 +1,370 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jonathan Kim <jonathan.kim@amd.com>
+ *
+ */
+
+#define pr_fmt(fmt) "perf/amdgpu_pmu: " fmt
+
+#include <linux/perf_event.h>
+#include <linux/init.h>
+#include <linux/cpumask.h>
+#include <linux/slab.h>
+#include "amdgpu.h"
+#include "amdgpu_pmu.h"
+#include "df_v3_6.h"
+
+#define PMU_NAME_SIZE 32
+
+struct amdgpu_perf_status {
+ struct list_head list;
+ struct pmu pmu;
+ struct amdgpu_device *gpu;
+ int node_idx;
+ char name[PMU_NAME_SIZE];
+ u8 max_counters;
+ uint64_t cntr_assign_mask;
+ raw_spinlock_t lock;
+};
+
+static LIST_HEAD(amdgpu_perf_status_list);
+
+
+/*---------------------------------------------
+ * sysfs format attributes
+ *---------------------------------------------*/
+
+PMU_FORMAT_ATTR(df_event, "config:0-7");
+PMU_FORMAT_ATTR(df_instance, "config:8-15");
+PMU_FORMAT_ATTR(df_unitmask, "config:16-23");
+
+static struct attribute *amdgpu_pmu_format_attrs[] = {
+ &format_attr_df_event.attr,
+ &format_attr_df_instance.attr,
+ &format_attr_df_unitmask.attr,
+ NULL,
+};
+
+
+static struct attribute_group amdgpu_pmu_format_group = {
+ .name = "format",
+ .attrs = amdgpu_pmu_format_attrs,
+};
+
+
+/*---------------------------------------------
+ * sysfs events attributes
+ *---------------------------------------------*/
+
+
+static struct attribute_group amdgpu_pmu_events_group = {
+ .name = "events",
+};
+
+struct AMDGPU_PMU_EVENT_DESC {
+ struct kobj_attribute attr;
+ const char *event;
+};
+
+static ssize_t _pmu_event_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ struct AMDGPU_PMU_EVENT_DESC *event =
+ container_of(attr, struct AMDGPU_PMU_EVENT_DESC, attr);
+ return sprintf(buf, "%s\n", event->event);
+}
+
+#define AMDGPU_PMU_EVENT_DESC(_name, _event) \
+{ \
+ .attr = __ATTR(_name, 0444, _pmu_event_show, NULL), \
+ .event = _event, \
+}
+
+
+/* DF event descriptors */
+static struct AMDGPU_PMU_EVENT_DESC amdgpu_vega20_df_event_descs[] = {
+ AMDGPU_PMU_EVENT_DESC(cake0_pcsout_txdata,
+ "df_event=0x7,df_instance=0x46,df_unitmask=0x2"),
+ AMDGPU_PMU_EVENT_DESC(cake1_pcsout_txdata,
+ "df_event=0x7,df_instance=0x47,df_unitmask=0x2"),
+ AMDGPU_PMU_EVENT_DESC(cake0_pcsout_txmeta,
+ "df_event=0x7,df_instance=0x46,df_unitmask=0x4"),
+ AMDGPU_PMU_EVENT_DESC(cake1_pcsout_txmeta,
+ "df_event=0x7,df_instance=0x47,df_unitmask=0x4"),
+ AMDGPU_PMU_EVENT_DESC(cake0_ftiinstat_reqalloc,
+ "df_event=0xb,df_instance=0x46,df_unitmask=0x4"),
+ AMDGPU_PMU_EVENT_DESC(cake1_ftiinstat_reqalloc,
+ "df_event=0xb,df_instance=0x47,df_unitmask=0x4"),
+ AMDGPU_PMU_EVENT_DESC(cake0_ftiinstat_rspalloc,
+ "df_event=0xb,df_instance=0x46,df_unitmask=0x8"),
+ AMDGPU_PMU_EVENT_DESC(cake1_ftiinstat_rspalloc,
+ "df_event=0xb,df_instance=0x47,df_unitmask=0x8"),
+ { /* end: all zeroes */ },
+};
+
+
+/* Initialize PMU */
+static int amdgpu_perf_event_init(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ /* test the event attr type check for PMU enumeration */
+ if (event->attr.type != event->pmu->type)
+ return -ENOENT;
+
+ /* update the hw_perf_event struct with config data */
+ hwc->conf = event->attr.config;
+
+ return 0;
+}
+
+/* Start PMU */
+static void amdgpu_perf_start(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct amdgpu_device *adev = container_of(event->pmu,
+ struct amdgpu_perf_status, pmu)->gpu;
+
+ if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
+ return;
+
+ WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
+ hwc->state = 0;
+
+ if (!(flags & PERF_EF_RELOAD))
+ adev->df_funcs->pmc_start(adev, hwc->conf, 1);
+
+ adev->df_funcs->pmc_start(adev, hwc->conf, 0);
+
+ perf_event_update_userpage(event);
+
+}
+
+/* Read PMU */
+static void amdgpu_perf_read(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct amdgpu_device *adev = container_of(event->pmu,
+ struct amdgpu_perf_status,
+ pmu)->gpu;
+
+ u64 count, prev;
+
+ adev->df_funcs->pmc_get_count(adev, hwc->conf, &count);
+
+ prev = local64_read(&hwc->prev_count);
+ if (local64_cmpxchg(&hwc->prev_count, prev, count) != prev)
+ return;
+
+ local64_add(count - prev, &event->count);
+}
+
+/* Stop PMU */
+static void amdgpu_perf_stop(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct amdgpu_device *adev = container_of(event->pmu,
+ struct amdgpu_perf_status,
+ pmu)->gpu;
+
+ if (hwc->state & PERF_HES_UPTODATE)
+ return;
+
+ adev->df_funcs->pmc_stop(adev, hwc->conf, 0);
+
+ WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
+ hwc->state |= PERF_HES_STOPPED;
+
+ if (hwc->state & PERF_HES_UPTODATE)
+ return;
+
+ amdgpu_perf_read(event);
+ hwc->state |= PERF_HES_UPTODATE;
+}
+
+/* Add PMU */
+static int amdgpu_perf_add(struct perf_event *event, int flags)
+{
+
+ struct hw_perf_event *hwc = &event->hw;
+ int retval;
+
+ struct amdgpu_device *adev = container_of(event->pmu,
+ struct amdgpu_perf_status,
+ pmu)->gpu;
+
+ event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+
+ adev->df_funcs->pmc_start(adev, hwc->conf, 1);
+
+ if (retval)
+ return retval;
+
+ if (flags & PERF_EF_START)
+ amdgpu_perf_start(event, PERF_EF_RELOAD);
+
+ return retval;
+
+}
+
+/* Delete PMU */
+static void amdgpu_perf_del(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ struct amdgpu_device *adev = container_of(event->pmu,
+ struct amdgpu_perf_status,
+ pmu)->gpu;
+
+ amdgpu_perf_stop(event, PERF_EF_UPDATE);
+
+
+ adev->df_funcs->pmc_stop(adev, hwc->conf, 1);
+
+ perf_event_update_userpage(event);
+}
+
+/* Initialize SYSFS attributes for AMDGPU PMU */
+static int init_events_attrs(struct amdgpu_device *adev)
+{
+ struct attribute **attrs;
+ int i = 0, j;
+
+ switch (adev->asic_type) {
+ case CHIP_VEGA20:
+ while (amdgpu_vega20_df_event_descs[i].attr.attr.name)
+ i++;
+ break;
+ default:
+ break;
+ }
+
+ attrs = kcalloc(i + 1, sizeof(struct attribute **), GFP_KERNEL);
+ if (!attrs)
+ return -ENOMEM;
+
+ switch (adev->asic_type) {
+ case CHIP_VEGA20:
+ for (j = 0; j < i; j++)
+ attrs[j] = &amdgpu_vega20_df_event_descs[j].attr.attr;
+ break;
+ default:
+ break;
+ }
+
+ amdgpu_pmu_events_group.attrs = attrs;
+ return 0;
+}
+
+const struct attribute_group *amdgpu_pmu_attr_groups[] = {
+ &amdgpu_pmu_format_group,
+ &amdgpu_pmu_events_group,
+ NULL,
+};
+
+
+static const struct pmu amdgpu_pmu __initconst = {
+ .event_init = amdgpu_perf_event_init,
+ .add = amdgpu_perf_add,
+ .del = amdgpu_perf_del,
+ .start = amdgpu_perf_start,
+ .stop = amdgpu_perf_stop,
+ .read = amdgpu_perf_read,
+ .task_ctx_nr = perf_invalid_context,
+ .attr_groups = amdgpu_pmu_attr_groups,
+};
+
+/* Initialize Data Fabric PMU */
+static int init_df_pmu(struct amdgpu_device *adev)
+{
+ struct amdgpu_perf_status *perf_status;
+ struct cntr_assign *c_assign;
+ int ret;
+
+ perf_status = kzalloc(sizeof(struct amdgpu_perf_status), GFP_KERNEL);
+ if (!perf_status)
+ return -ENOMEM;
+
+ raw_spin_lock_init(&perf_status->lock);
+
+ /* initialize pmu and counters assignments */
+ perf_status->pmu = amdgpu_pmu;
+ perf_status->gpu = adev;
+ perf_status->max_counters = AMDGPU_DF_MAX_COUNTERS;
+ perf_status->node_idx = adev->ddev->primary->index;
+
+ snprintf(perf_status->name, PMU_NAME_SIZE, "amdgpu_df_%d",
+ adev->ddev->primary->index);
+
+ ret = perf_pmu_register(&perf_status->pmu, perf_status->name,
+ -1);
+
+ if (!ret) {
+ pr_info("Detected AMDGPU DF Counters. # of Counters = %d.\n",
+ perf_status->max_counters);
+ list_add_tail(&perf_status->list, &amdgpu_perf_status_list);
+ } else {
+ pr_warn("Error initializing AMDGPU DF PMUs.\n");
+ kfree(perf_status);
+ }
+
+ return ret;
+}
+
+/* Initialize all PMU Blocks - Only DF for now */
+static int init_pmu(struct amdgpu_device *adev)
+{
+ int retval = 0;
+
+ switch (adev->asic_type) {
+ case CHIP_VEGA20:
+ retval = init_df_pmu(adev);
+ break;
+ default: /* ignore all other chips */
+ break;
+ }
+
+ return retval;
+}
+
+
+/* initialize AMDGPU PMU */
+int amdgpu_pmu_init(struct amdgpu_device *adev)
+{
+
+ int ret;
+
+ ret = init_events_attrs(adev);
+
+ if (ret)
+ return ret;
+
+ ret = init_pmu(adev);
+
+ if (ret) {
+ kfree(amdgpu_pmu_events_group.attrs);
+ return -ENODEV;
+ }
+
+ return ret;
+}
+
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
new file mode 100644
index 000000000000..d070d9e252ff
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jonathan Kim <jonathan.kim@amd.com>
+ *
+ */
+
+#ifndef _AMDGPU_PMU_H_
+#define _AMDGPU_PMU_H_
+
+enum amdgpu_pmu_perf_type {
+ PERF_TYPE_AMDGPU_DF = 0,
+ PERF_TYPE_AMDGPU_MAX
+};
+
+
+int amdgpu_pmu_init(struct amdgpu_device *adev);
+
+#endif /* _AMDGPU_PMU_H_ */
--
2.17.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-06-19 0:40 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-06-18 21:34 [PATCH] drm/amdgpu: add pmu counters Kim, Jonathan
[not found] ` <20190618213348.4572-1-jonathan.kim-5C7GfCeVMHo@public.gmane.org>
2019-06-19 0:40 ` Kuehling, Felix
-- strict thread matches above, loose matches on Subject: below --
2019-06-03 21:51 Kim, Jonathan
2019-05-29 15:02 Kim, Jonathan
[not found] ` <20190529150154.17375-1-jonathan.kim-5C7GfCeVMHo@public.gmane.org>
2019-05-30 13:30 ` Alex Deucher
2019-05-24 19:12 Kim, Jonathan
[not found] ` <20190524191229.84833-1-jonathan.kim-5C7GfCeVMHo@public.gmane.org>
2019-05-24 19:40 ` Kuehling, Felix
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all data and code used by this external index.