* [PATCH v3 0/3] Add interconnect driver for IPQ9574 SoC
@ 2024-03-26 12:13 Varadarajan Narayanan
2024-03-26 12:13 ` [PATCH v3 1/3] dt-bindings: interconnect: Add Qualcomm IPQ9574 support Varadarajan Narayanan
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Varadarajan Narayanan @ 2024-03-26 12:13 UTC (permalink / raw
To: andersson, konrad.dybcio, mturquette, sboyd, robh,
krzysztof.kozlowski+dt, conor+dt, djakov, quic_anusha,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-pm
Cc: Varadarajan Narayanan
MSM platforms manage NoC related clocks and scaling from RPM.
However, in IPQ SoCs, RPM is not involved in managing NoC
related clocks and there is no NoC scaling.
However, there is a requirement to enable some NoC interface
clocks for the accessing the peripherals present in the
system. Hence add a minimalistic interconnect driver that
establishes a path from the processor/memory to those peripherals
and vice versa.
---
v3:
qcom,ipq9574.h
Move 'first id' define to clock driver
gcc-ipq9574.c:
Use indexed identifiers here to avoid confusion
Fix error messages and move code to common.c as it can be
shared with future SoCs
v2:
qcom,ipq9574.h
Fix license identifier
Rename macros
qcom,ipq9574-gcc.yaml
Include interconnect-cells
gcc-ipq9574.c
Update commit log
Remove IS_ENABLED(CONFIG_INTERCONNECT) and auto select it from Kconfig
ipq9574.dtsi
Moved to separate patch
Include interconnect-cells to clock controller node
drivers/clk/qcom/Kconfig:
Auto select CONFIG_INTERCONNECT & CONFIG_INTERCONNECT_CLK
Varadarajan Narayanan (3):
dt-bindings: interconnect: Add Qualcomm IPQ9574 support
clk: qcom: add IPQ9574 interconnect clocks support
arm64: dts: qcom: ipq9574: Add icc provider ability to gcc
.../bindings/clock/qcom,ipq9574-gcc.yaml | 3 +
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 +
drivers/clk/qcom/Kconfig | 2 +
drivers/clk/qcom/common.c | 30 +++++++++
drivers/clk/qcom/common.h | 2 +
drivers/clk/qcom/gcc-ipq9574.c | 64 ++++++++++++++++++-
.../dt-bindings/interconnect/qcom,ipq9574.h | 59 +++++++++++++++++
7 files changed, 161 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 1/3] dt-bindings: interconnect: Add Qualcomm IPQ9574 support
2024-03-26 12:13 [PATCH v3 0/3] Add interconnect driver for IPQ9574 SoC Varadarajan Narayanan
@ 2024-03-26 12:13 ` Varadarajan Narayanan
2024-03-26 12:14 ` Krzysztof Kozlowski
2024-03-26 12:13 ` [PATCH v3 2/3] clk: qcom: add IPQ9574 interconnect clocks support Varadarajan Narayanan
2024-03-26 12:13 ` [PATCH v3 3/3] arm64: dts: qcom: ipq9574: Add icc provider ability to gcc Varadarajan Narayanan
2 siblings, 1 reply; 7+ messages in thread
From: Varadarajan Narayanan @ 2024-03-26 12:13 UTC (permalink / raw
To: andersson, konrad.dybcio, mturquette, sboyd, robh,
krzysztof.kozlowski+dt, conor+dt, djakov, quic_anusha,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-pm
Cc: Varadarajan Narayanan
Add interconnect-cells to clock provider so that it can be
used as icc provider.
Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip
interfaces. This will be used by the gcc-ipq9574 driver
that will for providing interconnect services using the
icc-clk framework.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v3:
Squash Documentation/ and include/ changes into same patch
qcom,ipq9574.h
Move 'first id' to clock driver
---
.../bindings/clock/qcom,ipq9574-gcc.yaml | 3 +
.../dt-bindings/interconnect/qcom,ipq9574.h | 59 +++++++++++++++++++
2 files changed, 62 insertions(+)
create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
index 944a0ea79cd6..824781cbdf34 100644
--- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
@@ -33,6 +33,9 @@ properties:
- description: PCIE30 PHY3 pipe clock source
- description: USB3 PHY pipe clock source
+ '#interconnect-cells':
+ const: 1
+
required:
- compatible
- clocks
diff --git a/include/dt-bindings/interconnect/qcom,ipq9574.h b/include/dt-bindings/interconnect/qcom,ipq9574.h
new file mode 100644
index 000000000000..9c95fbd5dc46
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,ipq9574.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+#ifndef INTERCONNECT_QCOM_IPQ9574_H
+#define INTERCONNECT_QCOM_IPQ9574_H
+
+#define MASTER_ANOC_PCIE0_1 0
+#define SLAVE_ANOC_PCIE0_1 1
+#define MASTER_SNOC_PCIE0_1 2
+#define SLAVE_SNOC_PCIE0_1 3
+#define MASTER_ANOC_PCIE1_1 4
+#define SLAVE_ANOC_PCIE1_1 5
+#define MASTER_SNOC_PCIE1_1 6
+#define SLAVE_SNOC_PCIE1_1 7
+#define MASTER_ANOC_PCIE2_2 8
+#define SLAVE_ANOC_PCIE2_2 9
+#define MASTER_SNOC_PCIE2_2 10
+#define SLAVE_SNOC_PCIE2_2 11
+#define MASTER_ANOC_PCIE3_2 12
+#define SLAVE_ANOC_PCIE3_2 13
+#define MASTER_SNOC_PCIE3_2 14
+#define SLAVE_SNOC_PCIE3_2 15
+#define MASTER_USB 16
+#define SLAVE_USB 17
+#define MASTER_USB_AXI 18
+#define SLAVE_USB_AXI 19
+#define MASTER_NSSNOC_NSSCC 20
+#define SLAVE_NSSNOC_NSSCC 21
+#define MASTER_NSSNOC_SNOC 22
+#define SLAVE_NSSNOC_SNOC 23
+#define MASTER_NSSNOC_SNOC_1 24
+#define SLAVE_NSSNOC_SNOC_1 25
+#define MASTER_NSSNOC_PCNOC_1 26
+#define SLAVE_NSSNOC_PCNOC_1 27
+#define MASTER_NSSNOC_QOSGEN_REF 28
+#define SLAVE_NSSNOC_QOSGEN_REF 29
+#define MASTER_NSSNOC_TIMEOUT_REF 30
+#define SLAVE_NSSNOC_TIMEOUT_REF 31
+#define MASTER_NSSNOC_XO_DCD 32
+#define SLAVE_NSSNOC_XO_DCD 33
+#define MASTER_NSSNOC_ATB 34
+#define SLAVE_NSSNOC_ATB 35
+#define MASTER_MEM_NOC_NSSNOC 36
+#define SLAVE_MEM_NOC_NSSNOC 37
+#define MASTER_NSSNOC_MEMNOC 38
+#define SLAVE_NSSNOC_MEMNOC 39
+#define MASTER_NSSNOC_MEM_NOC_1 40
+#define SLAVE_NSSNOC_MEM_NOC_1 41
+
+#define MASTER_NSS_CC_NSSNOC_PPE 0
+#define SLAVE_NSS_CC_NSSNOC_PPE 1
+#define MASTER_NSS_CC_NSSNOC_PPE_CFG 2
+#define SLAVE_NSS_CC_NSSNOC_PPE_CFG 3
+#define MASTER_NSS_CC_NSSNOC_NSS_CSR 4
+#define SLAVE_NSS_CC_NSSNOC_NSS_CSR 5
+#define MASTER_NSS_CC_NSSNOC_IMEM_QSB 6
+#define SLAVE_NSS_CC_NSSNOC_IMEM_QSB 7
+#define MASTER_NSS_CC_NSSNOC_IMEM_AHB 8
+#define SLAVE_NSS_CC_NSSNOC_IMEM_AHB 9
+
+#endif /* INTERCONNECT_QCOM_IPQ9574_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 2/3] clk: qcom: add IPQ9574 interconnect clocks support
2024-03-26 12:13 [PATCH v3 0/3] Add interconnect driver for IPQ9574 SoC Varadarajan Narayanan
2024-03-26 12:13 ` [PATCH v3 1/3] dt-bindings: interconnect: Add Qualcomm IPQ9574 support Varadarajan Narayanan
@ 2024-03-26 12:13 ` Varadarajan Narayanan
2024-03-26 12:37 ` Dmitry Baryshkov
2024-03-26 12:13 ` [PATCH v3 3/3] arm64: dts: qcom: ipq9574: Add icc provider ability to gcc Varadarajan Narayanan
2 siblings, 1 reply; 7+ messages in thread
From: Varadarajan Narayanan @ 2024-03-26 12:13 UTC (permalink / raw
To: andersson, konrad.dybcio, mturquette, sboyd, robh,
krzysztof.kozlowski+dt, conor+dt, djakov, quic_anusha,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-pm
Cc: Varadarajan Narayanan
Unlike MSM platforms that manage NoC related clocks and scaling
from RPM, IPQ SoCs dont involve RPM in managing NoC related
clocks and there is no NoC scaling.
However, there is a requirement to enable some NoC interface
clocks for accessing the peripheral controllers present on
these NoCs. Though exposing these as normal clocks would work,
having a minimalistic interconnect driver to handle these clocks
would make it consistent with other Qualcomm platforms resulting
in common code paths. This is similar to msm8996-cbf's usage of
icc-clk framework.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v3: Use indexed identifiers here to avoid confusion
Fix error messages and move to common.c
v2: Move DTS to separate patch
Update commit log
Auto select CONFIG_INTERCONNECT & CONFIG_INTERCONNECT_CLK to fix build error
---
drivers/clk/qcom/Kconfig | 2 ++
drivers/clk/qcom/common.c | 30 ++++++++++++++++
drivers/clk/qcom/common.h | 2 ++
drivers/clk/qcom/gcc-ipq9574.c | 64 +++++++++++++++++++++++++++++++++-
4 files changed, 97 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 8ab08e7b5b6c..af73a0b396eb 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -243,6 +243,8 @@ config IPQ_GCC_8074
config IPQ_GCC_9574
tristate "IPQ9574 Global Clock Controller"
+ select INTERCONNECT
+ select INTERCONNECT_CLK
help
Support for global clock controller on ipq9574 devices.
Say Y if you want to use peripheral devices such as UART, SPI,
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index 75f09e6e057e..b18d38509de5 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -8,6 +8,8 @@
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/clk-provider.h>
+#include <linux/interconnect-clk.h>
+#include <linux/interconnect-provider.h>
#include <linux/reset-controller.h>
#include <linux/of.h>
@@ -337,4 +339,32 @@ int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
}
EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
+int qcom_cc_icc_register(struct device *dev, struct clk_regmap *clks[],
+ int *noc_clks, int count, unsigned int first_id)
+{
+ struct icc_provider *provider;
+ struct icc_clk_data *icd;
+ int i;
+
+ icd = devm_kcalloc(dev, count, sizeof(*icd), GFP_KERNEL);
+ if (IS_ERR_OR_NULL(icd))
+ return dev_err_probe(dev, PTR_ERR(icd),
+ "malloc for clock data failed\n");
+
+ for (i = 0; i < count; i++) {
+ icd[i].clk = clks[noc_clks[i]]->hw.clk;
+ if (IS_ERR_OR_NULL(icd[i].clk))
+ return dev_err_probe(dev, -ENOENT,
+ "%d clock not found\n", noc_clks[i]);
+ icd[i].name = clk_hw_get_name(&clks[noc_clks[i]]->hw);
+ }
+
+ provider = icc_clk_register(dev, first_id, count, icd);
+ if (IS_ERR_OR_NULL(provider))
+ return dev_err_probe(dev, PTR_ERR(provider),
+ "icc_clk_register failed\n");
+
+ return 0;
+}
+
MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index 9c8f7b798d9f..4fce5e229fc1 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -65,5 +65,7 @@ extern int qcom_cc_probe(struct platform_device *pdev,
const struct qcom_cc_desc *desc);
extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
const struct qcom_cc_desc *desc);
+int qcom_cc_icc_register(struct device *dev, struct clk_regmap *clks[],
+ int *noc_clks, int count, unsigned int first_id);
#endif
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 0a3f846695b8..c63c44b6740f 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -12,6 +12,7 @@
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+#include <dt-bindings/interconnect/qcom,ipq9574.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
@@ -4301,6 +4302,56 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = {
[GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
};
+#define IPQ_APPS_ID 9574 /* some unique value */
+
+enum {
+ ICC_ANOC_PCIE0,
+ ICC_SNOC_PCIE0,
+ ICC_ANOC_PCIE1,
+ ICC_SNOC_PCIE1,
+ ICC_ANOC_PCIE2,
+ ICC_SNOC_PCIE2,
+ ICC_ANOC_PCIE3,
+ ICC_SNOC_PCIE3,
+ ICC_SNOC_USB,
+ ICC_ANOC_USB_AXI,
+ ICC_NSSNOC_NSSCC,
+ ICC_NSSNOC_SNOC_0,
+ ICC_NSSNOC_SNOC_1,
+ ICC_NSSNOC_PCNOC_1,
+ ICC_NSSNOC_QOSGEN_REF,
+ ICC_NSSNOC_TIMEOUT_REF,
+ ICC_NSSNOC_XO_DCD,
+ ICC_NSSNOC_ATB,
+ ICC_MEM_NOC_NSSNOC,
+ ICC_NSSNOC_MEMNOC,
+ ICC_NSSNOC_MEM_NOC_1,
+};
+
+static int noc_clks[] = {
+ [ICC_ANOC_PCIE0] = GCC_ANOC_PCIE0_1LANE_M_CLK,
+ [ICC_SNOC_PCIE0] = GCC_SNOC_PCIE0_1LANE_S_CLK,
+ [ICC_ANOC_PCIE1] = GCC_ANOC_PCIE1_1LANE_M_CLK,
+ [ICC_SNOC_PCIE1] = GCC_SNOC_PCIE1_1LANE_S_CLK,
+ [ICC_ANOC_PCIE2] = GCC_ANOC_PCIE2_2LANE_M_CLK,
+ [ICC_SNOC_PCIE2] = GCC_SNOC_PCIE2_2LANE_S_CLK,
+ [ICC_ANOC_PCIE3] = GCC_ANOC_PCIE3_2LANE_M_CLK,
+ [ICC_SNOC_PCIE3] = GCC_SNOC_PCIE3_2LANE_S_CLK,
+ [ICC_SNOC_USB] = GCC_SNOC_USB_CLK,
+ [ICC_ANOC_USB_AXI] = GCC_ANOC_USB_AXI_CLK,
+ [ICC_NSSNOC_NSSCC] = GCC_NSSNOC_NSSCC_CLK,
+ [ICC_NSSNOC_SNOC_0] = GCC_NSSNOC_SNOC_CLK,
+ [ICC_NSSNOC_SNOC_1] = GCC_NSSNOC_SNOC_1_CLK,
+ [ICC_NSSNOC_PCNOC_1] = GCC_NSSNOC_PCNOC_1_CLK,
+ [ICC_NSSNOC_QOSGEN_REF] = GCC_NSSNOC_QOSGEN_REF_CLK,
+ [ICC_NSSNOC_TIMEOUT_REF] = GCC_NSSNOC_TIMEOUT_REF_CLK,
+ [ICC_NSSNOC_XO_DCD] = GCC_NSSNOC_XO_DCD_CLK,
+ [ICC_NSSNOC_ATB] = GCC_NSSNOC_ATB_CLK,
+ [ICC_MEM_NOC_NSSNOC] = GCC_MEM_NOC_NSSNOC_CLK,
+ [ICC_NSSNOC_MEMNOC] = GCC_NSSNOC_MEMNOC_CLK,
+ [ICC_NSSNOC_MEM_NOC_1] = GCC_NSSNOC_MEM_NOC_1_CLK,
+};
+
static const struct of_device_id gcc_ipq9574_match_table[] = {
{ .compatible = "qcom,ipq9574-gcc" },
{ }
@@ -4327,7 +4378,18 @@ static const struct qcom_cc_desc gcc_ipq9574_desc = {
static int gcc_ipq9574_probe(struct platform_device *pdev)
{
- return qcom_cc_probe(pdev, &gcc_ipq9574_desc);
+ int ret;
+
+ ret = qcom_cc_probe(pdev, &gcc_ipq9574_desc);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "clock probe failed\n");
+
+ ret = qcom_cc_icc_register(&pdev->dev, gcc_ipq9574_clks, noc_clks,
+ ARRAY_SIZE(noc_clks), IPQ_APPS_ID);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "interconnect register failed\n");
+
+ return 0;
}
static struct platform_driver gcc_ipq9574_driver = {
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 3/3] arm64: dts: qcom: ipq9574: Add icc provider ability to gcc
2024-03-26 12:13 [PATCH v3 0/3] Add interconnect driver for IPQ9574 SoC Varadarajan Narayanan
2024-03-26 12:13 ` [PATCH v3 1/3] dt-bindings: interconnect: Add Qualcomm IPQ9574 support Varadarajan Narayanan
2024-03-26 12:13 ` [PATCH v3 2/3] clk: qcom: add IPQ9574 interconnect clocks support Varadarajan Narayanan
@ 2024-03-26 12:13 ` Varadarajan Narayanan
2 siblings, 0 replies; 7+ messages in thread
From: Varadarajan Narayanan @ 2024-03-26 12:13 UTC (permalink / raw
To: andersson, konrad.dybcio, mturquette, sboyd, robh,
krzysztof.kozlowski+dt, conor+dt, djakov, quic_anusha,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-pm
Cc: Varadarajan Narayanan
IPQ SoCs dont involve RPM in managing NoC related clocks and
there is no NoC scaling. Linux itself handles these clocks.
However, these should not be exposed as just clocks and align
with other Qualcomm SoCs that handle these clocks from a
interconnect provider.
Hence include icc provider capability to the gcc node so that
peripherals can use the interconnect facility to enable these
clocks.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v2: Fix include file order
Move to separate patch
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 7f2e5cbf3bbb..5b3e69379b1f 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+#include <dt-bindings/interconnect/qcom,ipq9574.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
#include <dt-bindings/thermal/thermal.h>
@@ -306,6 +307,7 @@ gcc: clock-controller@1800000 {
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
+ #interconnect-cells = <1>;
};
tcsr_mutex: hwlock@1905000 {
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: interconnect: Add Qualcomm IPQ9574 support
2024-03-26 12:13 ` [PATCH v3 1/3] dt-bindings: interconnect: Add Qualcomm IPQ9574 support Varadarajan Narayanan
@ 2024-03-26 12:14 ` Krzysztof Kozlowski
0 siblings, 0 replies; 7+ messages in thread
From: Krzysztof Kozlowski @ 2024-03-26 12:14 UTC (permalink / raw
To: Varadarajan Narayanan, andersson, konrad.dybcio, mturquette,
sboyd, robh, krzysztof.kozlowski+dt, conor+dt, djakov,
quic_anusha, linux-arm-msm, linux-clk, devicetree, linux-kernel,
linux-pm
On 26/03/2024 13:13, Varadarajan Narayanan wrote:
> Add interconnect-cells to clock provider so that it can be
> used as icc provider.
>
> Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip
> interfaces. This will be used by the gcc-ipq9574 driver
> that will for providing interconnect services using the
> icc-clk framework.
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> v3:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 2/3] clk: qcom: add IPQ9574 interconnect clocks support
2024-03-26 12:13 ` [PATCH v3 2/3] clk: qcom: add IPQ9574 interconnect clocks support Varadarajan Narayanan
@ 2024-03-26 12:37 ` Dmitry Baryshkov
2024-03-27 8:21 ` Varadarajan Narayanan
0 siblings, 1 reply; 7+ messages in thread
From: Dmitry Baryshkov @ 2024-03-26 12:37 UTC (permalink / raw
To: Varadarajan Narayanan
Cc: andersson, konrad.dybcio, mturquette, sboyd, robh,
krzysztof.kozlowski+dt, conor+dt, djakov, quic_anusha,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-pm
On Tue, 26 Mar 2024 at 14:14, Varadarajan Narayanan
<quic_varada@quicinc.com> wrote:
>
> Unlike MSM platforms that manage NoC related clocks and scaling
> from RPM, IPQ SoCs dont involve RPM in managing NoC related
> clocks and there is no NoC scaling.
>
> However, there is a requirement to enable some NoC interface
> clocks for accessing the peripheral controllers present on
> these NoCs. Though exposing these as normal clocks would work,
> having a minimalistic interconnect driver to handle these clocks
> would make it consistent with other Qualcomm platforms resulting
> in common code paths. This is similar to msm8996-cbf's usage of
> icc-clk framework.
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> v3: Use indexed identifiers here to avoid confusion
> Fix error messages and move to common.c
> v2: Move DTS to separate patch
> Update commit log
> Auto select CONFIG_INTERCONNECT & CONFIG_INTERCONNECT_CLK to fix build error
> ---
> drivers/clk/qcom/Kconfig | 2 ++
> drivers/clk/qcom/common.c | 30 ++++++++++++++++
> drivers/clk/qcom/common.h | 2 ++
> drivers/clk/qcom/gcc-ipq9574.c | 64 +++++++++++++++++++++++++++++++++-
> 4 files changed, 97 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 8ab08e7b5b6c..af73a0b396eb 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -243,6 +243,8 @@ config IPQ_GCC_8074
>
> config IPQ_GCC_9574
> tristate "IPQ9574 Global Clock Controller"
> + select INTERCONNECT
> + select INTERCONNECT_CLK
> help
> Support for global clock controller on ipq9574 devices.
> Say Y if you want to use peripheral devices such as UART, SPI,
> diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
> index 75f09e6e057e..b18d38509de5 100644
> --- a/drivers/clk/qcom/common.c
> +++ b/drivers/clk/qcom/common.c
> @@ -8,6 +8,8 @@
> #include <linux/regmap.h>
> #include <linux/platform_device.h>
> #include <linux/clk-provider.h>
> +#include <linux/interconnect-clk.h>
> +#include <linux/interconnect-provider.h>
> #include <linux/reset-controller.h>
> #include <linux/of.h>
>
> @@ -337,4 +339,32 @@ int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
> }
> EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
>
> +int qcom_cc_icc_register(struct device *dev, struct clk_regmap *clks[],
> + int *noc_clks, int count, unsigned int first_id)
> +{
> + struct icc_provider *provider;
> + struct icc_clk_data *icd;
> + int i;
> +
> + icd = devm_kcalloc(dev, count, sizeof(*icd), GFP_KERNEL);
> + if (IS_ERR_OR_NULL(icd))
Can devm_kcalloc return ERR?
> + return dev_err_probe(dev, PTR_ERR(icd),
> + "malloc for clock data failed\n");
So, this becomes dev_err_prove(dev, 0, "..."). returning 0. Not the
expected result for the error case.
> +
> + for (i = 0; i < count; i++) {
> + icd[i].clk = clks[noc_clks[i]]->hw.clk;
> + if (IS_ERR_OR_NULL(icd[i].clk))
> + return dev_err_probe(dev, -ENOENT,
> + "%d clock not found\n", noc_clks[i]);
This is even better. Potential NULL pointer exception, then useless
ERR_OR_NULL and finally API abuse.
Please use clk_hw_get_clk(), it is there for you.
> + icd[i].name = clk_hw_get_name(&clks[noc_clks[i]]->hw);
> + }
> +
> + provider = icc_clk_register(dev, first_id, count, icd);
> + if (IS_ERR_OR_NULL(provider))
> + return dev_err_probe(dev, PTR_ERR(provider),
> + "icc_clk_register failed\n");
> +
> + return 0;
> +}
> +
> MODULE_LICENSE("GPL v2");
> diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
> index 9c8f7b798d9f..4fce5e229fc1 100644
> --- a/drivers/clk/qcom/common.h
> +++ b/drivers/clk/qcom/common.h
> @@ -65,5 +65,7 @@ extern int qcom_cc_probe(struct platform_device *pdev,
> const struct qcom_cc_desc *desc);
> extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
> const struct qcom_cc_desc *desc);
> +int qcom_cc_icc_register(struct device *dev, struct clk_regmap *clks[],
> + int *noc_clks, int count, unsigned int first_id);
Add this function to the qcom_cc_probe() call stream. Change it to
pass an array of clk_hw instead of passing indices.
>
> #endif
> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> index 0a3f846695b8..c63c44b6740f 100644
> --- a/drivers/clk/qcom/gcc-ipq9574.c
> +++ b/drivers/clk/qcom/gcc-ipq9574.c
> @@ -12,6 +12,7 @@
>
> #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
> +#include <dt-bindings/interconnect/qcom,ipq9574.h>
>
> #include "clk-alpha-pll.h"
> #include "clk-branch.h"
> @@ -4301,6 +4302,56 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = {
> [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
> };
>
> +#define IPQ_APPS_ID 9574 /* some unique value */
> +
> +enum {
> + ICC_ANOC_PCIE0,
> + ICC_SNOC_PCIE0,
> + ICC_ANOC_PCIE1,
> + ICC_SNOC_PCIE1,
> + ICC_ANOC_PCIE2,
> + ICC_SNOC_PCIE2,
> + ICC_ANOC_PCIE3,
> + ICC_SNOC_PCIE3,
> + ICC_SNOC_USB,
> + ICC_ANOC_USB_AXI,
> + ICC_NSSNOC_NSSCC,
> + ICC_NSSNOC_SNOC_0,
> + ICC_NSSNOC_SNOC_1,
> + ICC_NSSNOC_PCNOC_1,
> + ICC_NSSNOC_QOSGEN_REF,
> + ICC_NSSNOC_TIMEOUT_REF,
> + ICC_NSSNOC_XO_DCD,
> + ICC_NSSNOC_ATB,
> + ICC_MEM_NOC_NSSNOC,
> + ICC_NSSNOC_MEMNOC,
> + ICC_NSSNOC_MEM_NOC_1,
> +};
> +
> +static int noc_clks[] = {
> + [ICC_ANOC_PCIE0] = GCC_ANOC_PCIE0_1LANE_M_CLK,
> + [ICC_SNOC_PCIE0] = GCC_SNOC_PCIE0_1LANE_S_CLK,
> + [ICC_ANOC_PCIE1] = GCC_ANOC_PCIE1_1LANE_M_CLK,
> + [ICC_SNOC_PCIE1] = GCC_SNOC_PCIE1_1LANE_S_CLK,
> + [ICC_ANOC_PCIE2] = GCC_ANOC_PCIE2_2LANE_M_CLK,
> + [ICC_SNOC_PCIE2] = GCC_SNOC_PCIE2_2LANE_S_CLK,
> + [ICC_ANOC_PCIE3] = GCC_ANOC_PCIE3_2LANE_M_CLK,
> + [ICC_SNOC_PCIE3] = GCC_SNOC_PCIE3_2LANE_S_CLK,
> + [ICC_SNOC_USB] = GCC_SNOC_USB_CLK,
> + [ICC_ANOC_USB_AXI] = GCC_ANOC_USB_AXI_CLK,
> + [ICC_NSSNOC_NSSCC] = GCC_NSSNOC_NSSCC_CLK,
> + [ICC_NSSNOC_SNOC_0] = GCC_NSSNOC_SNOC_CLK,
> + [ICC_NSSNOC_SNOC_1] = GCC_NSSNOC_SNOC_1_CLK,
> + [ICC_NSSNOC_PCNOC_1] = GCC_NSSNOC_PCNOC_1_CLK,
> + [ICC_NSSNOC_QOSGEN_REF] = GCC_NSSNOC_QOSGEN_REF_CLK,
> + [ICC_NSSNOC_TIMEOUT_REF] = GCC_NSSNOC_TIMEOUT_REF_CLK,
> + [ICC_NSSNOC_XO_DCD] = GCC_NSSNOC_XO_DCD_CLK,
> + [ICC_NSSNOC_ATB] = GCC_NSSNOC_ATB_CLK,
> + [ICC_MEM_NOC_NSSNOC] = GCC_MEM_NOC_NSSNOC_CLK,
> + [ICC_NSSNOC_MEMNOC] = GCC_NSSNOC_MEMNOC_CLK,
> + [ICC_NSSNOC_MEM_NOC_1] = GCC_NSSNOC_MEM_NOC_1_CLK,
> +};
> +
> static const struct of_device_id gcc_ipq9574_match_table[] = {
> { .compatible = "qcom,ipq9574-gcc" },
> { }
> @@ -4327,7 +4378,18 @@ static const struct qcom_cc_desc gcc_ipq9574_desc = {
>
> static int gcc_ipq9574_probe(struct platform_device *pdev)
> {
> - return qcom_cc_probe(pdev, &gcc_ipq9574_desc);
> + int ret;
> +
> + ret = qcom_cc_probe(pdev, &gcc_ipq9574_desc);
> + if (ret)
> + return dev_err_probe(&pdev->dev, ret, "clock probe failed\n");
> +
> + ret = qcom_cc_icc_register(&pdev->dev, gcc_ipq9574_clks, noc_clks,
> + ARRAY_SIZE(noc_clks), IPQ_APPS_ID);
> + if (ret)
> + return dev_err_probe(&pdev->dev, ret, "interconnect register failed\n");
So, even if we had a useful message from the called function, it has
become overridden with the useless "failed" message. Please don't do
that.
> +
> + return 0;
> }
>
> static struct platform_driver gcc_ipq9574_driver = {
> --
> 2.34.1
>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 2/3] clk: qcom: add IPQ9574 interconnect clocks support
2024-03-26 12:37 ` Dmitry Baryshkov
@ 2024-03-27 8:21 ` Varadarajan Narayanan
0 siblings, 0 replies; 7+ messages in thread
From: Varadarajan Narayanan @ 2024-03-27 8:21 UTC (permalink / raw
To: Dmitry Baryshkov
Cc: andersson, konrad.dybcio, mturquette, sboyd, robh,
krzysztof.kozlowski+dt, conor+dt, djakov, quic_anusha,
linux-arm-msm, linux-clk, devicetree, linux-kernel, linux-pm
Dmitry,
On Tue, Mar 26, 2024 at 02:37:20PM +0200, Dmitry Baryshkov wrote:
> On Tue, 26 Mar 2024 at 14:14, Varadarajan Narayanan
> <quic_varada@quicinc.com> wrote:
> >
> > Unlike MSM platforms that manage NoC related clocks and scaling
> > from RPM, IPQ SoCs dont involve RPM in managing NoC related
> > clocks and there is no NoC scaling.
> >
> > However, there is a requirement to enable some NoC interface
> > clocks for accessing the peripheral controllers present on
> > these NoCs. Though exposing these as normal clocks would work,
> > having a minimalistic interconnect driver to handle these clocks
> > would make it consistent with other Qualcomm platforms resulting
> > in common code paths. This is similar to msm8996-cbf's usage of
> > icc-clk framework.
> >
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Have posted the next version addressing your comments.
Please review.
Thanks
Varada
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2024-03-27 8:22 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-03-26 12:13 [PATCH v3 0/3] Add interconnect driver for IPQ9574 SoC Varadarajan Narayanan
2024-03-26 12:13 ` [PATCH v3 1/3] dt-bindings: interconnect: Add Qualcomm IPQ9574 support Varadarajan Narayanan
2024-03-26 12:14 ` Krzysztof Kozlowski
2024-03-26 12:13 ` [PATCH v3 2/3] clk: qcom: add IPQ9574 interconnect clocks support Varadarajan Narayanan
2024-03-26 12:37 ` Dmitry Baryshkov
2024-03-27 8:21 ` Varadarajan Narayanan
2024-03-26 12:13 ` [PATCH v3 3/3] arm64: dts: qcom: ipq9574: Add icc provider ability to gcc Varadarajan Narayanan
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