diff for duplicates of <CAAgF-BcTUTN5B59NO+yo7o=r=AtzvEHHOPwLBUgL15ifyYfFWA@mail.gmail.com> diff --git a/a/1.txt b/N1/1.txt index c587505..d2c5b8b 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -19,26 +19,26 @@ Please kindly ignore this patch. >> >> Please ignore my previous patch due to wrong return value. >> ->> arch/arm/mach-s5p64x0/Makefile | 2 +- ->> arch/arm/mach-s5p64x0/include/mach/regs-gpio.h | 10 ++ ->> arch/arm/mach-s5p64x0/irq-eint.c | 152 +>> ?arch/arm/mach-s5p64x0/Makefile ? ? ? ? ? ? ? ? | ? ?2 +- +>> ?arch/arm/mach-s5p64x0/include/mach/regs-gpio.h | ? 10 ++ +>> ?arch/arm/mach-s5p64x0/irq-eint.c ? ? ? ? ? ? ? | ?152 >> ++++++++++++++++++++++++ ->> 3 files changed, 163 insertions(+), 1 deletions(-) ->> create mode 100644 arch/arm/mach-s5p64x0/irq-eint.c +>> ?3 files changed, 163 insertions(+), 1 deletions(-) +>> ?create mode 100644 arch/arm/mach-s5p64x0/irq-eint.c >> >> diff --git a/arch/arm/mach-s5p64x0/Makefile >> b/arch/arm/mach-s5p64x0/Makefile >> index ae6bf6f..5f6afdf 100644 >> --- a/arch/arm/mach-s5p64x0/Makefile >> +++ b/arch/arm/mach-s5p64x0/Makefile ->> @@ -13,7 +13,7 @@ obj- := ->> # Core support for S5P64X0 system +>> @@ -13,7 +13,7 @@ obj- ? ? ? ? ? ? ? ? ? ? ? ? ?:= +>> ?# Core support for S5P64X0 system >> ->> obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o ->> -obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o ->> +obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o irq-eint.o ->> obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o ->> obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o +>> ?obj-$(CONFIG_ARCH_S5P64X0) ? ?+= cpu.o init.o clock.o dma.o gpiolib.o +>> -obj-$(CONFIG_ARCH_S5P64X0) ? ? += setup-i2c0.o +>> +obj-$(CONFIG_ARCH_S5P64X0) ? ? += setup-i2c0.o irq-eint.o +>> ?obj-$(CONFIG_CPU_S5P6440) ? ? += clock-s5p6440.o +>> ?obj-$(CONFIG_CPU_S5P6450) ? ? += clock-s5p6450.o >> >> diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h >> b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h @@ -46,20 +46,20 @@ Please kindly ignore this patch. >> --- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h >> +++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h >> @@ -34,4 +34,14 @@ ->> #define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180) ->> #define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300) +>> ?#define S5P6450_GPQ_BASE ? ? ? ? ? ? ?(S5P_VA_GPIO + 0x0180) +>> ?#define S5P6450_GPS_BASE ? ? ? ? ? ? ?(S5P_VA_GPIO + 0x0300) >> >> +/* External interrupt control registers for group0 */ >> + ->> +#define EINT0CON0_OFFSET (0x900) ->> +#define EINT0MASK_OFFSET (0x920) ->> +#define EINT0PEND_OFFSET (0x924) +>> +#define EINT0CON0_OFFSET ? ? ? ? ? ? ? (0x900) +>> +#define EINT0MASK_OFFSET ? ? ? ? ? ? ? (0x920) +>> +#define EINT0PEND_OFFSET ? ? ? ? ? ? ? (0x924) >> + ->> +#define S5P64X0_EINT0CON0 (S5P_VA_GPIO + EINT0CON0_OFFSET) ->> +#define S5P64X0_EINT0MASK (S5P_VA_GPIO + EINT0MASK_OFFSET) ->> +#define S5P64X0_EINT0PEND (S5P_VA_GPIO + EINT0PEND_OFFSET) +>> +#define S5P64X0_EINT0CON0 ? ? ? ? ? ? ?(S5P_VA_GPIO + EINT0CON0_OFFSET) +>> +#define S5P64X0_EINT0MASK ? ? ? ? ? ? ?(S5P_VA_GPIO + EINT0MASK_OFFSET) +>> +#define S5P64X0_EINT0PEND ? ? ? ? ? ? ?(S5P_VA_GPIO + EINT0PEND_OFFSET) >> + ->> #endif /* __ASM_ARCH_REGS_GPIO_H */ +>> ?#endif /* __ASM_ARCH_REGS_GPIO_H */ >> diff --git a/arch/arm/mach-s5p64x0/irq-eint.c >> b/arch/arm/mach-s5p64x0/irq-eint.c >> new file mode 100644 @@ -70,7 +70,7 @@ Please kindly ignore this patch. >> +/* arch/arm/mach-s5p64x0/irq-eint.c >> + * >> + * Copyright (c) 2011 Samsung Electronics Co., Ltd ->> + * http://www.samsung.com/ +>> + * ? ? ? ? ? ? http://www.samsung.com/ >> + * >> + * Based on linux/arch/arm/mach-s3c64xx/irq-eint.c >> + * @@ -92,57 +92,57 @@ Please kindly ignore this patch. >> +#include<mach/regs-gpio.h> >> +#include<mach/regs-clock.h> >> + ->> +#define eint_offset(irq) ((irq) - IRQ_EINT(0)) +>> +#define eint_offset(irq) ? ? ? ((irq) - IRQ_EINT(0)) >> + >> +static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int >> type) >> +{ ->> + int offs = eint_offset(data->irq); ->> + int shift; ->> + u32 ctrl, mask; ->> + u32 newvalue = 0; ->> + ->> + if (offs> 15) ->> + return -EINVAL; ->> + ->> + switch (type) { ->> + case IRQ_TYPE_NONE: ->> + printk(KERN_WARNING "No edge setting!\n"); ->> + break; ->> + case IRQ_TYPE_EDGE_RISING: ->> + newvalue = S3C2410_EXTINT_RISEEDGE; ->> + break; ->> + case IRQ_TYPE_EDGE_FALLING: ->> + newvalue = S3C2410_EXTINT_FALLEDGE; ->> + break; ->> + case IRQ_TYPE_EDGE_BOTH: ->> + newvalue = S3C2410_EXTINT_BOTHEDGE; ->> + break; ->> + case IRQ_TYPE_LEVEL_LOW: ->> + newvalue = S3C2410_EXTINT_LOWLEV; ->> + break; ->> + case IRQ_TYPE_LEVEL_HIGH: ->> + newvalue = S3C2410_EXTINT_HILEV; ->> + break; ->> + default: ->> + printk(KERN_ERR "No such irq type %d", type); ->> + return -EINVAL; ->> + } ->> + ->> + shift = (offs / 2) * 4; ->> + mask = 0x7<< shift; ->> + ->> + ctrl = __raw_readl(S5P64X0_EINT0CON0)& ~mask; ->> + ctrl |= newvalue<< shift; ->> + __raw_writel(ctrl, S5P64X0_EINT0CON0); ->> + ->> + /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */ ->> + if (0x50000 == (__raw_readl(S5P64X0_SYS_ID)& 0xFF000)) ->> + s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2)); ->> + else ->> + s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2)); ->> + ->> + return 0; +>> + ? ? ? int offs = eint_offset(data->irq); +>> + ? ? ? int shift; +>> + ? ? ? u32 ctrl, mask; +>> + ? ? ? u32 newvalue = 0; +>> + +>> + ? ? ? if (offs> ?15) +>> + ? ? ? ? ? ? ? return -EINVAL; +>> + +>> + ? ? ? switch (type) { +>> + ? ? ? case IRQ_TYPE_NONE: +>> + ? ? ? ? ? ? ? printk(KERN_WARNING "No edge setting!\n"); +>> + ? ? ? ? ? ? ? break; +>> + ? ? ? case IRQ_TYPE_EDGE_RISING: +>> + ? ? ? ? ? ? ? newvalue = S3C2410_EXTINT_RISEEDGE; +>> + ? ? ? ? ? ? ? break; +>> + ? ? ? case IRQ_TYPE_EDGE_FALLING: +>> + ? ? ? ? ? ? ? newvalue = S3C2410_EXTINT_FALLEDGE; +>> + ? ? ? ? ? ? ? break; +>> + ? ? ? case IRQ_TYPE_EDGE_BOTH: +>> + ? ? ? ? ? ? ? newvalue = S3C2410_EXTINT_BOTHEDGE; +>> + ? ? ? ? ? ? ? break; +>> + ? ? ? case IRQ_TYPE_LEVEL_LOW: +>> + ? ? ? ? ? ? ? newvalue = S3C2410_EXTINT_LOWLEV; +>> + ? ? ? ? ? ? ? break; +>> + ? ? ? case IRQ_TYPE_LEVEL_HIGH: +>> + ? ? ? ? ? ? ? newvalue = S3C2410_EXTINT_HILEV; +>> + ? ? ? ? ? ? ? break; +>> + ? ? ? default: +>> + ? ? ? ? ? ? ? printk(KERN_ERR "No such irq type %d", type); +>> + ? ? ? ? ? ? ? return -EINVAL; +>> + ? ? ? } +>> + +>> + ? ? ? shift = (offs / 2) * 4; +>> + ? ? ? mask = 0x7<< ?shift; +>> + +>> + ? ? ? ctrl = __raw_readl(S5P64X0_EINT0CON0)& ?~mask; +>> + ? ? ? ctrl |= newvalue<< ?shift; +>> + ? ? ? __raw_writel(ctrl, S5P64X0_EINT0CON0); +>> + +>> + ? ? ? /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */ +>> + ? ? ? if (0x50000 == (__raw_readl(S5P64X0_SYS_ID)& ?0xFF000)) +>> + ? ? ? ? ? ? ? s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2)); +>> + ? ? ? else +>> + ? ? ? ? ? ? ? s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2)); +>> + +>> + ? ? ? return 0; >> +} >> + >> +/* @@ -155,69 +155,69 @@ Please kindly ignore this patch. >> +static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned >> int end) >> +{ ->> + u32 status = __raw_readl(S5P64X0_EINT0PEND); ->> + u32 mask = __raw_readl(S5P64X0_EINT0MASK); ->> + unsigned int irq; ->> + ->> + status&= ~mask; ->> + status>>= start; ->> + status&= (1<< (end - start + 1)) - 1; ->> + ->> + for (irq = IRQ_EINT(start); irq<= IRQ_EINT(end); irq++) { ->> + if (status& 1) ->> + generic_handle_irq(irq); ->> + status>>= 1; ->> + } +>> + ? ? ? u32 status = __raw_readl(S5P64X0_EINT0PEND); +>> + ? ? ? u32 mask = __raw_readl(S5P64X0_EINT0MASK); +>> + ? ? ? unsigned int irq; +>> + +>> + ? ? ? status&= ~mask; +>> + ? ? ? status>>= start; +>> + ? ? ? status&= (1<< ?(end - start + 1)) - 1; +>> + +>> + ? ? ? for (irq = IRQ_EINT(start); irq<= IRQ_EINT(end); irq++) { +>> + ? ? ? ? ? ? ? if (status& ?1) +>> + ? ? ? ? ? ? ? ? ? ? ? generic_handle_irq(irq); +>> + ? ? ? ? ? ? ? status>>= 1; +>> + ? ? ? } >> +} >> + >> +static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc >> *desc) >> +{ ->> + s5p64x0_irq_demux_eint(0, 3); +>> + ? ? ? s5p64x0_irq_demux_eint(0, 3); >> +} >> + >> +static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc >> *desc) >> +{ ->> + s5p64x0_irq_demux_eint(4, 11); +>> + ? ? ? s5p64x0_irq_demux_eint(4, 11); >> +} >> + >> +static void s5p64x0_irq_demux_eint12_15(unsigned int irq, ->> + struct irq_desc *desc) +>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct irq_desc *desc) >> +{ ->> + s5p64x0_irq_demux_eint(12, 15); +>> + ? ? ? s5p64x0_irq_demux_eint(12, 15); >> +} >> + >> +static int s5p64x0_alloc_gc(void) >> +{ ->> + struct irq_chip_generic *gc; ->> + struct irq_chip_type *ct; +>> + ? ? ? struct irq_chip_generic *gc; +>> + ? ? ? struct irq_chip_type *ct; >> + ->> + gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE, ->> + S5P_VA_GPIO, handle_level_irq); +>> + ? ? ? gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE, +>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? S5P_VA_GPIO, handle_level_irq); > -> ^^^^ +> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ^^^^ Added spaces purposefully to make the parameters aligned properly in the next line > nitpick: Should be TABS >> ->> + if (!gc) { ->> + printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0" ->> + "external interrupts failed\n", __func__); ->> + return -EINVAL; ->> + } ->> + ->> + ct = gc->chip_types; ->> + ct->chip.irq_ack = irq_gc_ack; ->> + ct->chip.irq_mask = irq_gc_mask_set_bit; ->> + ct->chip.irq_unmask = irq_gc_mask_clr_bit; ->> + ct->chip.irq_set_type = s5p64x0_irq_eint_set_type; ->> + ct->regs.ack = EINT0PEND_OFFSET; ->> + ct->regs.mask = EINT0MASK_OFFSET; ->> + irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE, ->> + IRQ_NOREQUEST | IRQ_NOPROBE, 0); +>> + ? ? ? if (!gc) { +>> + ? ? ? ? ? ? ? printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0" +>> + ? ? ? ? ? ? ? ? ? ? ? "external interrupts failed\n", __func__); +>> + ? ? ? ? ? ? ? return -EINVAL; +>> + ? ? ? } +>> + +>> + ? ? ? ct = gc->chip_types; +>> + ? ? ? ct->chip.irq_ack = irq_gc_ack; +>> + ? ? ? ct->chip.irq_mask = irq_gc_mask_set_bit; +>> + ? ? ? ct->chip.irq_unmask = irq_gc_mask_clr_bit; +>> + ? ? ? ct->chip.irq_set_type = s5p64x0_irq_eint_set_type; +>> + ? ? ? ct->regs.ack = EINT0PEND_OFFSET; +>> + ? ? ? ct->regs.mask = EINT0MASK_OFFSET; +>> + ? ? ? irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE, +>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?IRQ_NOREQUEST | IRQ_NOPROBE, 0); > -> ^^^^^^ +> ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^ > TABS Added spaces purposefully to make the parameters aligned properly in the next line. @@ -225,18 +225,18 @@ the next line. Thanks&Regards Padma >> ->> + return 0; +>> + ? ? ? return 0; >> +} >> + >> +static int __init s5p64x0_init_irq_eint(void) >> +{ ->> + int ret = s5p64x0_alloc_gc(); ->> + irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3); ->> + irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11); ->> + irq_set_chained_handler(IRQ_EINT12_15, +>> + ? ? ? int ret = s5p64x0_alloc_gc(); +>> + ? ? ? irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3); +>> + ? ? ? irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11); +>> + ? ? ? irq_set_chained_handler(IRQ_EINT12_15, >> s5p64x0_irq_demux_eint12_15); >> + ->> + return ret; +>> + ? ? ? return ret; >> +} >> +arch_initcall(s5p64x0_init_irq_eint); > @@ -246,6 +246,6 @@ Padma > -- > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" > in -> the body of a message to majordomo@vger.kernel.org -> More majordomo info at http://vger.kernel.org/majordomo-info.html +> the body of a message to majordomo at vger.kernel.org +> More majordomo info at ?http://vger.kernel.org/majordomo-info.html > diff --git a/a/content_digest b/N1/content_digest index a5cd0bb..bcdd804 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -5,23 +5,16 @@ "ref\0004E27B914.3050809\@linaro.org\0" ] [ - "From\0padma venkat <padma.kvr\@gmail.com>\0" + "From\0padma.kvr\@gmail.com (padma venkat)\0" ] [ - "Subject\0Re:\0" + "Subject\0\0" ] [ "Date\0Thu, 21 Jul 2011 11:13:11 +0530\0" ] [ - "To\0Tushar Behera <tushar.behera\@linaro.org>\0" -] -[ - "Cc\0linux-samsung-soc\@vger.kernel.org", - " kgene.kim\@samsung.com", - " linux\@arm.linux.org.uk", - " linux-arm-kernel\@lists.infradead.org", - " Padmavathi Venna <padma.v\@samsung.com>\0" + "To\0linux-arm-kernel\@lists.infradead.org\0" ] [ "\0000:1\0" @@ -51,26 +44,26 @@ ">>\n", ">> Please ignore my previous patch due to wrong return value.\n", ">>\n", - ">> \302\240arch/arm/mach-s5p64x0/Makefile \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 | \302\240 \302\2402 +-\n", - ">> \302\240arch/arm/mach-s5p64x0/include/mach/regs-gpio.h | \302\240 10 ++\n", - ">> \302\240arch/arm/mach-s5p64x0/irq-eint.c \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 | \302\240152\n", + ">> ?arch/arm/mach-s5p64x0/Makefile ? ? ? ? ? ? ? ? | ? ?2 +-\n", + ">> ?arch/arm/mach-s5p64x0/include/mach/regs-gpio.h | ? 10 ++\n", + ">> ?arch/arm/mach-s5p64x0/irq-eint.c ? ? ? ? ? ? ? | ?152\n", ">> ++++++++++++++++++++++++\n", - ">> \302\2403 files changed, 163 insertions(+), 1 deletions(-)\n", - ">> \302\240create mode 100644 arch/arm/mach-s5p64x0/irq-eint.c\n", + ">> ?3 files changed, 163 insertions(+), 1 deletions(-)\n", + ">> ?create mode 100644 arch/arm/mach-s5p64x0/irq-eint.c\n", ">>\n", ">> diff --git a/arch/arm/mach-s5p64x0/Makefile\n", ">> b/arch/arm/mach-s5p64x0/Makefile\n", ">> index ae6bf6f..5f6afdf 100644\n", ">> --- a/arch/arm/mach-s5p64x0/Makefile\n", ">> +++ b/arch/arm/mach-s5p64x0/Makefile\n", - ">> \@\@ -13,7 +13,7 \@\@ obj- \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240:=\n", - ">> \302\240# Core support for S5P64X0 system\n", + ">> \@\@ -13,7 +13,7 \@\@ obj- ? ? ? ? ? ? ? ? ? ? ? ? ?:=\n", + ">> ?# Core support for S5P64X0 system\n", ">>\n", - ">> \302\240obj-\$(CONFIG_ARCH_S5P64X0) \302\240 \302\240+= cpu.o init.o clock.o dma.o gpiolib.o\n", - ">> -obj-\$(CONFIG_ARCH_S5P64X0) \302\240 \302\240 += setup-i2c0.o\n", - ">> +obj-\$(CONFIG_ARCH_S5P64X0) \302\240 \302\240 += setup-i2c0.o irq-eint.o\n", - ">> \302\240obj-\$(CONFIG_CPU_S5P6440) \302\240 \302\240 += clock-s5p6440.o\n", - ">> \302\240obj-\$(CONFIG_CPU_S5P6450) \302\240 \302\240 += clock-s5p6450.o\n", + ">> ?obj-\$(CONFIG_ARCH_S5P64X0) ? ?+= cpu.o init.o clock.o dma.o gpiolib.o\n", + ">> -obj-\$(CONFIG_ARCH_S5P64X0) ? ? += setup-i2c0.o\n", + ">> +obj-\$(CONFIG_ARCH_S5P64X0) ? ? += setup-i2c0.o irq-eint.o\n", + ">> ?obj-\$(CONFIG_CPU_S5P6440) ? ? += clock-s5p6440.o\n", + ">> ?obj-\$(CONFIG_CPU_S5P6450) ? ? += clock-s5p6450.o\n", ">>\n", ">> diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h\n", ">> b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h\n", @@ -78,20 +71,20 @@ ">> --- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h\n", ">> +++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h\n", ">> \@\@ -34,4 +34,14 \@\@\n", - ">> \302\240#define S5P6450_GPQ_BASE \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240(S5P_VA_GPIO + 0x0180)\n", - ">> \302\240#define S5P6450_GPS_BASE \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240(S5P_VA_GPIO + 0x0300)\n", + ">> ?#define S5P6450_GPQ_BASE ? ? ? ? ? ? ?(S5P_VA_GPIO + 0x0180)\n", + ">> ?#define S5P6450_GPS_BASE ? ? ? ? ? ? ?(S5P_VA_GPIO + 0x0300)\n", ">>\n", ">> +/* External interrupt control registers for group0 */\n", ">> +\n", - ">> +#define EINT0CON0_OFFSET \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 (0x900)\n", - ">> +#define EINT0MASK_OFFSET \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 (0x920)\n", - ">> +#define EINT0PEND_OFFSET \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 (0x924)\n", + ">> +#define EINT0CON0_OFFSET ? ? ? ? ? ? ? (0x900)\n", + ">> +#define EINT0MASK_OFFSET ? ? ? ? ? ? ? (0x920)\n", + ">> +#define EINT0PEND_OFFSET ? ? ? ? ? ? ? (0x924)\n", ">> +\n", - ">> +#define S5P64X0_EINT0CON0 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240(S5P_VA_GPIO + EINT0CON0_OFFSET)\n", - ">> +#define S5P64X0_EINT0MASK \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240(S5P_VA_GPIO + EINT0MASK_OFFSET)\n", - ">> +#define S5P64X0_EINT0PEND \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240(S5P_VA_GPIO + EINT0PEND_OFFSET)\n", + ">> +#define S5P64X0_EINT0CON0 ? ? ? ? ? ? ?(S5P_VA_GPIO + EINT0CON0_OFFSET)\n", + ">> +#define S5P64X0_EINT0MASK ? ? ? ? ? ? ?(S5P_VA_GPIO + EINT0MASK_OFFSET)\n", + ">> +#define S5P64X0_EINT0PEND ? ? ? ? ? ? ?(S5P_VA_GPIO + EINT0PEND_OFFSET)\n", ">> +\n", - ">> \302\240#endif /* __ASM_ARCH_REGS_GPIO_H */\n", + ">> ?#endif /* __ASM_ARCH_REGS_GPIO_H */\n", ">> diff --git a/arch/arm/mach-s5p64x0/irq-eint.c\n", ">> b/arch/arm/mach-s5p64x0/irq-eint.c\n", ">> new file mode 100644\n", @@ -102,7 +95,7 @@ ">> +/* arch/arm/mach-s5p64x0/irq-eint.c\n", ">> + *\n", ">> + * Copyright (c) 2011 Samsung Electronics Co., Ltd\n", - ">> + * \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 http://www.samsung.com/\n", + ">> + * ? ? ? ? ? ? http://www.samsung.com/\n", ">> + *\n", ">> + * Based on linux/arch/arm/mach-s3c64xx/irq-eint.c\n", ">> + *\n", @@ -124,57 +117,57 @@ ">> +#include<mach/regs-gpio.h>\n", ">> +#include<mach/regs-clock.h>\n", ">> +\n", - ">> +#define eint_offset(irq) \302\240 \302\240 \302\240 ((irq) - IRQ_EINT(0))\n", + ">> +#define eint_offset(irq) ? ? ? ((irq) - IRQ_EINT(0))\n", ">> +\n", ">> +static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int\n", ">> type)\n", ">> +{\n", - ">> + \302\240 \302\240 \302\240 int offs = eint_offset(data->irq);\n", - ">> + \302\240 \302\240 \302\240 int shift;\n", - ">> + \302\240 \302\240 \302\240 u32 ctrl, mask;\n", - ">> + \302\240 \302\240 \302\240 u32 newvalue = 0;\n", + ">> + ? ? ? int offs = eint_offset(data->irq);\n", + ">> + ? ? ? int shift;\n", + ">> + ? ? ? u32 ctrl, mask;\n", + ">> + ? ? ? u32 newvalue = 0;\n", ">> +\n", - ">> + \302\240 \302\240 \302\240 if (offs> \302\24015)\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return -EINVAL;\n", + ">> + ? ? ? if (offs> ?15)\n", + ">> + ? ? ? ? ? ? ? return -EINVAL;\n", ">> +\n", - ">> + \302\240 \302\240 \302\240 switch (type) {\n", - ">> + \302\240 \302\240 \302\240 case IRQ_TYPE_NONE:\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 printk(KERN_WARNING \"No edge setting!\\n\");\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 break;\n", - ">> + \302\240 \302\240 \302\240 case IRQ_TYPE_EDGE_RISING:\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 newvalue = S3C2410_EXTINT_RISEEDGE;\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 break;\n", - ">> + \302\240 \302\240 \302\240 case IRQ_TYPE_EDGE_FALLING:\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 newvalue = S3C2410_EXTINT_FALLEDGE;\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 break;\n", - ">> + \302\240 \302\240 \302\240 case IRQ_TYPE_EDGE_BOTH:\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 newvalue = S3C2410_EXTINT_BOTHEDGE;\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 break;\n", - ">> + \302\240 \302\240 \302\240 case IRQ_TYPE_LEVEL_LOW:\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 newvalue = S3C2410_EXTINT_LOWLEV;\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 break;\n", - ">> + \302\240 \302\240 \302\240 case IRQ_TYPE_LEVEL_HIGH:\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 newvalue = S3C2410_EXTINT_HILEV;\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 break;\n", - ">> + \302\240 \302\240 \302\240 default:\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 printk(KERN_ERR \"No such irq type %d\", type);\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return -EINVAL;\n", - ">> + \302\240 \302\240 \302\240 }\n", + ">> + ? ? ? switch (type) {\n", + ">> + ? ? ? case IRQ_TYPE_NONE:\n", + ">> + ? ? ? ? ? ? ? printk(KERN_WARNING \"No edge setting!\\n\");\n", + ">> + ? ? ? ? ? ? ? break;\n", + ">> + ? ? ? case IRQ_TYPE_EDGE_RISING:\n", + ">> + ? ? ? ? ? ? ? newvalue = S3C2410_EXTINT_RISEEDGE;\n", + ">> + ? ? ? ? ? ? ? break;\n", + ">> + ? ? ? case IRQ_TYPE_EDGE_FALLING:\n", + ">> + ? ? ? ? ? ? ? newvalue = S3C2410_EXTINT_FALLEDGE;\n", + ">> + ? ? ? ? ? ? ? break;\n", + ">> + ? ? ? case IRQ_TYPE_EDGE_BOTH:\n", + ">> + ? ? ? ? ? ? ? newvalue = S3C2410_EXTINT_BOTHEDGE;\n", + ">> + ? ? ? ? ? ? ? break;\n", + ">> + ? ? ? case IRQ_TYPE_LEVEL_LOW:\n", + ">> + ? ? ? ? ? ? ? newvalue = S3C2410_EXTINT_LOWLEV;\n", + ">> + ? ? ? ? ? ? ? break;\n", + ">> + ? ? ? case IRQ_TYPE_LEVEL_HIGH:\n", + ">> + ? ? ? ? ? ? ? newvalue = S3C2410_EXTINT_HILEV;\n", + ">> + ? ? ? ? ? ? ? break;\n", + ">> + ? ? ? default:\n", + ">> + ? ? ? ? ? ? ? printk(KERN_ERR \"No such irq type %d\", type);\n", + ">> + ? ? ? ? ? ? ? return -EINVAL;\n", + ">> + ? ? ? }\n", ">> +\n", - ">> + \302\240 \302\240 \302\240 shift = (offs / 2) * 4;\n", - ">> + \302\240 \302\240 \302\240 mask = 0x7<< \302\240shift;\n", + ">> + ? ? ? shift = (offs / 2) * 4;\n", + ">> + ? ? ? mask = 0x7<< ?shift;\n", ">> +\n", - ">> + \302\240 \302\240 \302\240 ctrl = __raw_readl(S5P64X0_EINT0CON0)& \302\240~mask;\n", - ">> + \302\240 \302\240 \302\240 ctrl |= newvalue<< \302\240shift;\n", - ">> + \302\240 \302\240 \302\240 __raw_writel(ctrl, S5P64X0_EINT0CON0);\n", + ">> + ? ? ? ctrl = __raw_readl(S5P64X0_EINT0CON0)& ?~mask;\n", + ">> + ? ? ? ctrl |= newvalue<< ?shift;\n", + ">> + ? ? ? __raw_writel(ctrl, S5P64X0_EINT0CON0);\n", ">> +\n", - ">> + \302\240 \302\240 \302\240 /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */\n", - ">> + \302\240 \302\240 \302\240 if (0x50000 == (__raw_readl(S5P64X0_SYS_ID)& \302\2400xFF000))\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));\n", - ">> + \302\240 \302\240 \302\240 else\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));\n", + ">> + ? ? ? /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */\n", + ">> + ? ? ? if (0x50000 == (__raw_readl(S5P64X0_SYS_ID)& ?0xFF000))\n", + ">> + ? ? ? ? ? ? ? s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));\n", + ">> + ? ? ? else\n", + ">> + ? ? ? ? ? ? ? s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));\n", ">> +\n", - ">> + \302\240 \302\240 \302\240 return 0;\n", + ">> + ? ? ? return 0;\n", ">> +}\n", ">> +\n", ">> +/*\n", @@ -187,69 +180,69 @@ ">> +static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned\n", ">> int end)\n", ">> +{\n", - ">> + \302\240 \302\240 \302\240 u32 status = __raw_readl(S5P64X0_EINT0PEND);\n", - ">> + \302\240 \302\240 \302\240 u32 mask = __raw_readl(S5P64X0_EINT0MASK);\n", - ">> + \302\240 \302\240 \302\240 unsigned int irq;\n", + ">> + ? ? ? u32 status = __raw_readl(S5P64X0_EINT0PEND);\n", + ">> + ? ? ? u32 mask = __raw_readl(S5P64X0_EINT0MASK);\n", + ">> + ? ? ? unsigned int irq;\n", ">> +\n", - ">> + \302\240 \302\240 \302\240 status&= ~mask;\n", - ">> + \302\240 \302\240 \302\240 status>>= start;\n", - ">> + \302\240 \302\240 \302\240 status&= (1<< \302\240(end - start + 1)) - 1;\n", + ">> + ? ? ? status&= ~mask;\n", + ">> + ? ? ? status>>= start;\n", + ">> + ? ? ? status&= (1<< ?(end - start + 1)) - 1;\n", ">> +\n", - ">> + \302\240 \302\240 \302\240 for (irq = IRQ_EINT(start); irq<= IRQ_EINT(end); irq++) {\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 if (status& \302\2401)\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 generic_handle_irq(irq);\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 status>>= 1;\n", - ">> + \302\240 \302\240 \302\240 }\n", + ">> + ? ? ? for (irq = IRQ_EINT(start); irq<= IRQ_EINT(end); irq++) {\n", + ">> + ? ? ? ? ? ? ? if (status& ?1)\n", + ">> + ? ? ? ? ? ? ? ? ? ? ? generic_handle_irq(irq);\n", + ">> + ? ? ? ? ? ? ? status>>= 1;\n", + ">> + ? ? ? }\n", ">> +}\n", ">> +\n", ">> +static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc\n", ">> *desc)\n", ">> +{\n", - ">> + \302\240 \302\240 \302\240 s5p64x0_irq_demux_eint(0, 3);\n", + ">> + ? ? ? s5p64x0_irq_demux_eint(0, 3);\n", ">> +}\n", ">> +\n", ">> +static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc\n", ">> *desc)\n", ">> +{\n", - ">> + \302\240 \302\240 \302\240 s5p64x0_irq_demux_eint(4, 11);\n", + ">> + ? ? ? s5p64x0_irq_demux_eint(4, 11);\n", ">> +}\n", ">> +\n", ">> +static void s5p64x0_irq_demux_eint12_15(unsigned int irq,\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 struct irq_desc *desc)\n", + ">> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct irq_desc *desc)\n", ">> +{\n", - ">> + \302\240 \302\240 \302\240 s5p64x0_irq_demux_eint(12, 15);\n", + ">> + ? ? ? s5p64x0_irq_demux_eint(12, 15);\n", ">> +}\n", ">> +\n", ">> +static int s5p64x0_alloc_gc(void)\n", ">> +{\n", - ">> + \302\240 \302\240 \302\240 struct irq_chip_generic *gc;\n", - ">> + \302\240 \302\240 \302\240 struct irq_chip_type *ct;\n", + ">> + ? ? ? struct irq_chip_generic *gc;\n", + ">> + ? ? ? struct irq_chip_type *ct;\n", ">> +\n", - ">> + \302\240 \302\240 \302\240 gc = irq_alloc_generic_chip(\"s5p64x0-eint\", 1, S5P_IRQ_EINT_BASE,\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 S5P_VA_GPIO, handle_level_irq);\n", + ">> + ? ? ? gc = irq_alloc_generic_chip(\"s5p64x0-eint\", 1, S5P_IRQ_EINT_BASE,\n", + ">> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? S5P_VA_GPIO, handle_level_irq);\n", ">\n", - "> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 ^^^^\n", + "> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ^^^^\n", "Added spaces purposefully to make the parameters aligned properly in\n", "the next line\n", "> nitpick: Should be TABS\n", ">>\n", - ">> + \302\240 \302\240 \302\240 if (!gc) {\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 printk(KERN_ERR \"%s: irq_alloc_generic_chip for group 0\"\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \"external interrupts failed\\n\", __func__);\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return -EINVAL;\n", - ">> + \302\240 \302\240 \302\240 }\n", + ">> + ? ? ? if (!gc) {\n", + ">> + ? ? ? ? ? ? ? printk(KERN_ERR \"%s: irq_alloc_generic_chip for group 0\"\n", + ">> + ? ? ? ? ? ? ? ? ? ? ? \"external interrupts failed\\n\", __func__);\n", + ">> + ? ? ? ? ? ? ? return -EINVAL;\n", + ">> + ? ? ? }\n", ">> +\n", - ">> + \302\240 \302\240 \302\240 ct = gc->chip_types;\n", - ">> + \302\240 \302\240 \302\240 ct->chip.irq_ack = irq_gc_ack;\n", - ">> + \302\240 \302\240 \302\240 ct->chip.irq_mask = irq_gc_mask_set_bit;\n", - ">> + \302\240 \302\240 \302\240 ct->chip.irq_unmask = irq_gc_mask_clr_bit;\n", - ">> + \302\240 \302\240 \302\240 ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;\n", - ">> + \302\240 \302\240 \302\240 ct->regs.ack = EINT0PEND_OFFSET;\n", - ">> + \302\240 \302\240 \302\240 ct->regs.mask = EINT0MASK_OFFSET;\n", - ">> + \302\240 \302\240 \302\240 irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,\n", - ">> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240IRQ_NOREQUEST | IRQ_NOPROBE, 0);\n", + ">> + ? ? ? ct = gc->chip_types;\n", + ">> + ? ? ? ct->chip.irq_ack = irq_gc_ack;\n", + ">> + ? ? ? ct->chip.irq_mask = irq_gc_mask_set_bit;\n", + ">> + ? ? ? ct->chip.irq_unmask = irq_gc_mask_clr_bit;\n", + ">> + ? ? ? ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;\n", + ">> + ? ? ? ct->regs.ack = EINT0PEND_OFFSET;\n", + ">> + ? ? ? ct->regs.mask = EINT0MASK_OFFSET;\n", + ">> + ? ? ? irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,\n", + ">> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?IRQ_NOREQUEST | IRQ_NOPROBE, 0);\n", ">\n", - "> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240^^^^^^\n", + "> ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^\n", "> TABS\n", "Added spaces purposefully to make the parameters aligned properly in\n", "the next line.\n", @@ -257,18 +250,18 @@ "Thanks&Regards\n", "Padma\n", ">>\n", - ">> + \302\240 \302\240 \302\240 return 0;\n", + ">> + ? ? ? return 0;\n", ">> +}\n", ">> +\n", ">> +static int __init s5p64x0_init_irq_eint(void)\n", ">> +{\n", - ">> + \302\240 \302\240 \302\240 int ret = s5p64x0_alloc_gc();\n", - ">> + \302\240 \302\240 \302\240 irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);\n", - ">> + \302\240 \302\240 \302\240 irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);\n", - ">> + \302\240 \302\240 \302\240 irq_set_chained_handler(IRQ_EINT12_15,\n", + ">> + ? ? ? int ret = s5p64x0_alloc_gc();\n", + ">> + ? ? ? irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);\n", + ">> + ? ? ? irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);\n", + ">> + ? ? ? irq_set_chained_handler(IRQ_EINT12_15,\n", ">> s5p64x0_irq_demux_eint12_15);\n", ">> +\n", - ">> + \302\240 \302\240 \302\240 return ret;\n", + ">> + ? ? ? return ret;\n", ">> +}\n", ">> +arch_initcall(s5p64x0_init_irq_eint);\n", ">\n", @@ -278,9 +271,9 @@ "> --\n", "> To unsubscribe from this list: send the line \"unsubscribe linux-samsung-soc\"\n", "> in\n", - "> the body of a message to majordomo\@vger.kernel.org\n", - "> More majordomo info at \302\240http://vger.kernel.org/majordomo-info.html\n", + "> the body of a message to majordomo at vger.kernel.org\n", + "> More majordomo info at ?http://vger.kernel.org/majordomo-info.html\n", ">" ] -f9bfa48335da1914e0933a3938ac8951e5edbba67ab383d7e3e84d1327e52375 +a6f472bee220f5dcbc4d1ee30b20efe5065ff3e43196671b105c051972eb910b
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