From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51446) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z7a99-0002Rd-Ll for qemu-devel@nongnu.org; Tue, 23 Jun 2015 22:10:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z7a95-0001MN-GB for qemu-devel@nongnu.org; Tue, 23 Jun 2015 22:10:39 -0400 Received: from mail-yk0-f176.google.com ([209.85.160.176]:34137) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z7a95-0001Lt-9u for qemu-devel@nongnu.org; Tue, 23 Jun 2015 22:10:35 -0400 Received: by ykfy125 with SMTP id y125so16466231ykf.1 for ; Tue, 23 Jun 2015 19:10:35 -0700 (PDT) MIME-Version: 1.0 Sender: peter.crosthwaite@petalogix.com In-Reply-To: <1434648295-30584-9-git-send-email-crosthwaite.peter@gmail.com> References: <1434648295-30584-1-git-send-email-crosthwaite.peter@gmail.com> <1434648295-30584-9-git-send-email-crosthwaite.peter@gmail.com> Date: Tue, 23 Jun 2015 19:10:34 -0700 Message-ID: From: Peter Crosthwaite Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v3 8/8] cpu-exec: Purge all uses of ENV_GET_CPU() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite Cc: Eduardo Habkost , Peter Crosthwaite , "qemu-devel@nongnu.org Developers" , =?UTF-8?Q?Andreas_F=C3=A4rber?= , Aurelien Jarno , Richard Henderson On Thu, Jun 18, 2015 at 10:24 AM, Peter Crosthwaite wrote: > Remove un-needed usages of ENV_GET_CPU() by converting the APIs to use > CPUState pointers and retrieving the env_ptr as minimally needed. > > Scripted conversion for target-* change: > > for I in target-*/cpu.h; do > sed -i \ > 's/\(^int cpu_[^_]*_exec(\)[^ ][^ ]* \*s);$/\1CPUState *cpu);/' \ > $I; > done > > Signed-off-by: Peter Crosthwaite Dropping this patch in v4 as no RBs yet. Regards, Peter > --- > Changed since v2 (Aurelien review): > s/CPU_GET_ENV/ENV_GET_CPU/ > Changed since RFC v2 (RTH review): > Apply target-* change pattern to all arches. > Avoid use of cpu_ptr for X86 specifics > Add () to ENV_GET_CPU macros in commit message > Add BSD and Linux user needed changes > Add missing architecture changes > --- > bsd-user/main.c | 3 ++- > cpu-exec.c | 28 +++++++++++++--------------- > cpus.c | 3 +-- > linux-user/main.c | 28 ++++++++++++++-------------- > target-alpha/cpu.h | 2 +- > target-arm/cpu.h | 2 +- > target-cris/cpu.h | 2 +- > target-i386/cpu.h | 2 +- > target-lm32/cpu.h | 2 +- > target-m68k/cpu.h | 2 +- > target-microblaze/cpu.h | 2 +- > target-mips/cpu.h | 2 +- > target-moxie/cpu.h | 2 +- > target-openrisc/cpu.h | 2 +- > target-ppc/cpu.h | 2 +- > target-s390x/cpu.h | 2 +- > target-sh4/cpu.h | 2 +- > target-sparc/cpu.h | 2 +- > target-tricore/cpu.h | 2 +- > target-unicore32/cpu.h | 3 ++- > target-xtensa/cpu.h | 2 +- > 21 files changed, 48 insertions(+), 49 deletions(-) > > diff --git a/bsd-user/main.c b/bsd-user/main.c > index 45a1436..7196285 100644 > --- a/bsd-user/main.c > +++ b/bsd-user/main.c > @@ -166,6 +166,7 @@ static void set_idt(int n, unsigned int dpl) > > void cpu_loop(CPUX86State *env) > { > + CPUState *cs = CPU(x86_env_get_cpu(env)); > int trapnr; > abi_ulong pc; > //target_siginfo_t info; > @@ -512,7 +513,7 @@ void cpu_loop(CPUSPARCState *env) > //target_siginfo_t info; > > while (1) { > - trapnr = cpu_sparc_exec (env); > + trapnr = cpu_sparc_exec(cs); > > switch (trapnr) { > #ifndef TARGET_SPARC64 > diff --git a/cpu-exec.c b/cpu-exec.c > index 2ffeb6e..31541c6 100644 > --- a/cpu-exec.c > +++ b/cpu-exec.c > @@ -226,10 +226,9 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr) > > /* Execute the code without caching the generated code. An interpreter > could be used if available. */ > -static void cpu_exec_nocache(CPUArchState *env, int max_cycles, > +static void cpu_exec_nocache(CPUState *cpu, int max_cycles, > TranslationBlock *orig_tb) > { > - CPUState *cpu = ENV_GET_CPU(env); > TranslationBlock *tb; > target_ulong pc = orig_tb->pc; > target_ulong cs_base = orig_tb->cs_base; > @@ -253,12 +252,12 @@ static void cpu_exec_nocache(CPUArchState *env, int max_cycles, > tb_free(tb); > } > > -static TranslationBlock *tb_find_slow(CPUArchState *env, > +static TranslationBlock *tb_find_slow(CPUState *cpu, > target_ulong pc, > target_ulong cs_base, > uint64_t flags) > { > - CPUState *cpu = ENV_GET_CPU(env); > + CPUArchState *env = (CPUArchState *)cpu->env_ptr; > TranslationBlock *tb, **ptb1; > unsigned int h; > tb_page_addr_t phys_pc, phys_page1; > @@ -310,9 +309,9 @@ static TranslationBlock *tb_find_slow(CPUArchState *env, > return tb; > } > > -static inline TranslationBlock *tb_find_fast(CPUArchState *env) > +static inline TranslationBlock *tb_find_fast(CPUState *cpu) > { > - CPUState *cpu = ENV_GET_CPU(env); > + CPUArchState *env = (CPUArchState *)cpu->env_ptr; > TranslationBlock *tb; > target_ulong cs_base, pc; > int flags; > @@ -324,14 +323,13 @@ static inline TranslationBlock *tb_find_fast(CPUArchState *env) > tb = cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; > if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base || > tb->flags != flags)) { > - tb = tb_find_slow(env, pc, cs_base, flags); > + tb = tb_find_slow(cpu, pc, cs_base, flags); > } > return tb; > } > > -static void cpu_handle_debug_exception(CPUArchState *env) > +static void cpu_handle_debug_exception(CPUState *cpu) > { > - CPUState *cpu = ENV_GET_CPU(env); > CPUClass *cc = CPU_GET_CLASS(cpu); > CPUWatchpoint *wp; > > @@ -348,12 +346,12 @@ static void cpu_handle_debug_exception(CPUArchState *env) > > volatile sig_atomic_t exit_request; > > -int cpu_exec(CPUArchState *env) > +int cpu_exec(CPUState *cpu) > { > - CPUState *cpu = ENV_GET_CPU(env); > CPUClass *cc = CPU_GET_CLASS(cpu); > #ifdef TARGET_I386 > X86CPU *x86_cpu = X86_CPU(cpu); > + CPUArchState *env = &x86_cpu->env; > #endif > int ret, interrupt_request; > TranslationBlock *tb; > @@ -406,7 +404,7 @@ int cpu_exec(CPUArchState *env) > /* exit request from the cpu execution loop */ > ret = cpu->exception_index; > if (ret == EXCP_DEBUG) { > - cpu_handle_debug_exception(env); > + cpu_handle_debug_exception(cpu); > } > cpu->exception_index = -1; > break; > @@ -482,7 +480,7 @@ int cpu_exec(CPUArchState *env) > } > spin_lock(&tcg_ctx.tb_ctx.tb_lock); > have_tb_lock = true; > - tb = tb_find_fast(env); > + tb = tb_find_fast(cpu); > /* Note: we do it here to avoid a gcc bug on Mac OS X when > doing it in tb_find_slow */ > if (tcg_ctx.tb_ctx.tb_invalidated_flag) { > @@ -542,7 +540,7 @@ int cpu_exec(CPUArchState *env) > if (insns_left > 0) { > /* Execute remaining instructions. */ > tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK); > - cpu_exec_nocache(env, insns_left, tb); > + cpu_exec_nocache(cpu, insns_left, tb); > align_clocks(&sc, cpu); > } > cpu->exception_index = EXCP_INTERRUPT; > @@ -566,11 +564,11 @@ int cpu_exec(CPUArchState *env) > /* Reload env after longjmp - the compiler may have smashed all > * local variables as longjmp is marked 'noreturn'. */ > cpu = current_cpu; > - env = cpu->env_ptr; > cc = CPU_GET_CLASS(cpu); > cpu->can_do_io = 1; > #ifdef TARGET_I386 > x86_cpu = X86_CPU(cpu); > + env = &x86_cpu->env; > #endif > if (have_tb_lock) { > spin_unlock(&tcg_ctx.tb_ctx.tb_lock); > diff --git a/cpus.c b/cpus.c > index 131fa3b..9511bf7 100644 > --- a/cpus.c > +++ b/cpus.c > @@ -1345,7 +1345,6 @@ int vm_stop_force_state(RunState state) > > static int tcg_cpu_exec(CPUState *cpu) > { > - CPUArchState *env = cpu->env_ptr; > int ret; > #ifdef CONFIG_PROFILER > int64_t ti; > @@ -1380,7 +1379,7 @@ static int tcg_cpu_exec(CPUState *cpu) > cpu->icount_decr.u16.low = decr; > cpu->icount_extra = count; > } > - ret = cpu_exec(env); > + ret = cpu_exec(cpu); > #ifdef CONFIG_PROFILER > tcg_time += profile_getclock() - ti; > #endif > diff --git a/linux-user/main.c b/linux-user/main.c > index 17cf38d..b57723a 100644 > --- a/linux-user/main.c > +++ b/linux-user/main.c > @@ -280,7 +280,7 @@ void cpu_loop(CPUX86State *env) > > for(;;) { > cpu_exec_start(cs); > - trapnr = cpu_x86_exec(env); > + trapnr = cpu_x86_exec(cs); > cpu_exec_end(cs); > switch(trapnr) { > case 0x80: > @@ -674,7 +674,7 @@ void cpu_loop(CPUARMState *env) > > for(;;) { > cpu_exec_start(cs); > - trapnr = cpu_arm_exec(env); > + trapnr = cpu_arm_exec(cs); > cpu_exec_end(cs); > switch(trapnr) { > case EXCP_UDEF: > @@ -1005,7 +1005,7 @@ void cpu_loop(CPUARMState *env) > > for (;;) { > cpu_exec_start(cs); > - trapnr = cpu_arm_exec(env); > + trapnr = cpu_arm_exec(cs); > cpu_exec_end(cs); > > switch (trapnr) { > @@ -1084,7 +1084,7 @@ void cpu_loop(CPUUniCore32State *env) > > for (;;) { > cpu_exec_start(cs); > - trapnr = uc32_cpu_exec(env); > + trapnr = uc32_cpu_exec(cs); > cpu_exec_end(cs); > switch (trapnr) { > case UC32_EXCP_PRIV: > @@ -1285,7 +1285,7 @@ void cpu_loop (CPUSPARCState *env) > > while (1) { > cpu_exec_start(cs); > - trapnr = cpu_sparc_exec (env); > + trapnr = cpu_sparc_exec(cs); > cpu_exec_end(cs); > > /* Compute PSR before exposing state. */ > @@ -1566,7 +1566,7 @@ void cpu_loop(CPUPPCState *env) > > for(;;) { > cpu_exec_start(cs); > - trapnr = cpu_ppc_exec(env); > + trapnr = cpu_ppc_exec(cs); > cpu_exec_end(cs); > switch(trapnr) { > case POWERPC_EXCP_NONE: > @@ -2418,7 +2418,7 @@ void cpu_loop(CPUMIPSState *env) > > for(;;) { > cpu_exec_start(cs); > - trapnr = cpu_mips_exec(env); > + trapnr = cpu_mips_exec(cs); > cpu_exec_end(cs); > switch(trapnr) { > case EXCP_SYSCALL: > @@ -2655,7 +2655,7 @@ void cpu_loop(CPUOpenRISCState *env) > > for (;;) { > cpu_exec_start(cs); > - trapnr = cpu_exec(env); > + trapnr = cpu_exec(cs); > cpu_exec_end(cs); > gdbsig = 0; > > @@ -2745,7 +2745,7 @@ void cpu_loop(CPUSH4State *env) > > while (1) { > cpu_exec_start(cs); > - trapnr = cpu_sh4_exec (env); > + trapnr = cpu_sh4_exec(cs); > cpu_exec_end(cs); > > switch (trapnr) { > @@ -2807,7 +2807,7 @@ void cpu_loop(CPUCRISState *env) > > while (1) { > cpu_exec_start(cs); > - trapnr = cpu_cris_exec (env); > + trapnr = cpu_cris_exec(cs); > cpu_exec_end(cs); > switch (trapnr) { > case 0xaa: > @@ -2868,7 +2868,7 @@ void cpu_loop(CPUMBState *env) > > while (1) { > cpu_exec_start(cs); > - trapnr = cpu_mb_exec (env); > + trapnr = cpu_mb_exec(cs); > cpu_exec_end(cs); > switch (trapnr) { > case 0xaa: > @@ -2973,7 +2973,7 @@ void cpu_loop(CPUM68KState *env) > > for(;;) { > cpu_exec_start(cs); > - trapnr = cpu_m68k_exec(env); > + trapnr = cpu_m68k_exec(cs); > cpu_exec_end(cs); > switch(trapnr) { > case EXCP_ILLEGAL: > @@ -3112,7 +3112,7 @@ void cpu_loop(CPUAlphaState *env) > > while (1) { > cpu_exec_start(cs); > - trapnr = cpu_alpha_exec (env); > + trapnr = cpu_alpha_exec(cs); > cpu_exec_end(cs); > > /* All of the traps imply a transition through PALcode, which > @@ -3300,7 +3300,7 @@ void cpu_loop(CPUS390XState *env) > > while (1) { > cpu_exec_start(cs); > - trapnr = cpu_s390x_exec(env); > + trapnr = cpu_s390x_exec(cs); > cpu_exec_end(cs); > switch (trapnr) { > case EXCP_INTERRUPT: > diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h > index 2a4d5cb..91c56d6 100644 > --- a/target-alpha/cpu.h > +++ b/target-alpha/cpu.h > @@ -431,7 +431,7 @@ AlphaCPU *cpu_alpha_init(const char *cpu_model); > #define cpu_init(cpu_model) CPU(cpu_alpha_init(cpu_model)) > > void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf); > -int cpu_alpha_exec(CPUAlphaState *s); > +int cpu_alpha_exec(CPUState *cpu); > /* you can call this signal handler from your SIGBUS and SIGSEGV > signal handlers to inform the virtual CPU of exceptions. non zero > is returned if the signal was handled by the virtual CPU. */ > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 21b5b8e..9225f9e 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -490,7 +490,7 @@ typedef struct CPUARMState { > #include "cpu-qom.h" > > ARMCPU *cpu_arm_init(const char *cpu_model); > -int cpu_arm_exec(CPUARMState *s); > +int cpu_arm_exec(CPUState *cpu); > uint32_t do_arm_semihosting(CPUARMState *env); > void aarch64_sync_32_to_64(CPUARMState *env); > void aarch64_sync_64_to_32(CPUARMState *env); > diff --git a/target-cris/cpu.h b/target-cris/cpu.h > index 677b38c..d422e35 100644 > --- a/target-cris/cpu.h > +++ b/target-cris/cpu.h > @@ -176,7 +176,7 @@ typedef struct CPUCRISState { > #include "cpu-qom.h" > > CRISCPU *cpu_cris_init(const char *cpu_model); > -int cpu_cris_exec(CPUCRISState *s); > +int cpu_cris_exec(CPUState *cpu); > /* you can call this signal handler from your SIGBUS and SIGSEGV > signal handlers to inform the virtual CPU of exceptions. non zero > is returned if the signal was handled by the virtual CPU. */ > diff --git a/target-i386/cpu.h b/target-i386/cpu.h > index 603aaf0..6040205 100644 > --- a/target-i386/cpu.h > +++ b/target-i386/cpu.h > @@ -983,7 +983,7 @@ typedef struct CPUX86State { > > X86CPU *cpu_x86_init(const char *cpu_model); > X86CPU *cpu_x86_create(const char *cpu_model, Error **errp); > -int cpu_x86_exec(CPUX86State *s); > +int cpu_x86_exec(CPUState *cpu); > void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf); > void x86_cpudef_setup(void); > int cpu_x86_support_mca_broadcast(CPUX86State *env); > diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h > index 11ae68d..944777d 100644 > --- a/target-lm32/cpu.h > +++ b/target-lm32/cpu.h > @@ -199,7 +199,7 @@ static inline lm32_wp_t lm32_wp_type(uint32_t dc, int idx) > #include "cpu-qom.h" > > LM32CPU *cpu_lm32_init(const char *cpu_model); > -int cpu_lm32_exec(CPULM32State *s); > +int cpu_lm32_exec(CPUState *cpu); > /* you can call this signal handler from your SIGBUS and SIGSEGV > signal handlers to inform the virtual CPU of exceptions. non zero > is returned if the signal was handled by the virtual CPU. */ > diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h > index 5f165da..9a62f6c 100644 > --- a/target-m68k/cpu.h > +++ b/target-m68k/cpu.h > @@ -117,7 +117,7 @@ typedef struct CPUM68KState { > void m68k_tcg_init(void); > void m68k_cpu_init_gdb(M68kCPU *cpu); > M68kCPU *cpu_m68k_init(const char *cpu_model); > -int cpu_m68k_exec(CPUM68KState *s); > +int cpu_m68k_exec(CPUState *cpu); > /* you can call this signal handler from your SIGBUS and SIGSEGV > signal handlers to inform the virtual CPU of exceptions. non zero > is returned if the signal was handled by the virtual CPU. */ > diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h > index d73e1c7..62c2458 100644 > --- a/target-microblaze/cpu.h > +++ b/target-microblaze/cpu.h > @@ -276,7 +276,7 @@ struct CPUMBState { > > void mb_tcg_init(void); > MicroBlazeCPU *cpu_mb_init(const char *cpu_model); > -int cpu_mb_exec(CPUMBState *s); > +int cpu_mb_exec(CPUState *cpu); > /* you can call this signal handler from your SIGBUS and SIGSEGV > signal handlers to inform the virtual CPU of exceptions. non zero > is returned if the signal was handled by the virtual CPU. */ > diff --git a/target-mips/cpu.h b/target-mips/cpu.h > index 474a0e3..075c561 100644 > --- a/target-mips/cpu.h > +++ b/target-mips/cpu.h > @@ -746,7 +746,7 @@ enum { > */ > #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 > > -int cpu_mips_exec(CPUMIPSState *s); > +int cpu_mips_exec(CPUState *cpu); > void mips_tcg_init(void); > MIPSCPU *cpu_mips_init(const char *cpu_model); > int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); > diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h > index c2733a2..29572aa 100644 > --- a/target-moxie/cpu.h > +++ b/target-moxie/cpu.h > @@ -112,7 +112,7 @@ static inline MoxieCPU *moxie_env_get_cpu(CPUMoxieState *env) > #define ENV_OFFSET offsetof(MoxieCPU, env) > > MoxieCPU *cpu_moxie_init(const char *cpu_model); > -int cpu_moxie_exec(CPUMoxieState *s); > +int cpu_moxie_exec(CPUState *cpu); > void moxie_cpu_do_interrupt(CPUState *cs); > void moxie_cpu_dump_state(CPUState *cpu, FILE *f, > fprintf_function cpu_fprintf, int flags); > diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h > index 9e23cd0..36c4f20 100644 > --- a/target-openrisc/cpu.h > +++ b/target-openrisc/cpu.h > @@ -346,7 +346,7 @@ static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env) > OpenRISCCPU *cpu_openrisc_init(const char *cpu_model); > > void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf); > -int cpu_openrisc_exec(CPUOpenRISCState *s); > +int cpu_openrisc_exec(CPUState *cpu); > void openrisc_cpu_do_interrupt(CPUState *cpu); > bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); > void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index c05c503..6f76674 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -1164,7 +1164,7 @@ do { \ > PowerPCCPU *cpu_ppc_init(const char *cpu_model); > void ppc_translate_init(void); > void gen_update_current_nip(void *opaque); > -int cpu_ppc_exec (CPUPPCState *s); > +int cpu_ppc_exec (CPUState *s); > /* you can call this signal handler from your SIGBUS and SIGSEGV > signal handlers to inform the virtual CPU of exceptions. non zero > is returned if the signal was handled by the virtual CPU. */ > diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h > index 584e74b..ae771fb 100644 > --- a/target-s390x/cpu.h > +++ b/target-s390x/cpu.h > @@ -375,7 +375,7 @@ void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen); > > S390CPU *cpu_s390x_init(const char *cpu_model); > void s390x_translate_init(void); > -int cpu_s390x_exec(CPUS390XState *s); > +int cpu_s390x_exec(CPUState *cpu); > > /* you can call this signal handler from your SIGBUS and SIGSEGV > signal handlers to inform the virtual CPU of exceptions. non zero > diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h > index 4a027a6..34bb3d7 100644 > --- a/target-sh4/cpu.h > +++ b/target-sh4/cpu.h > @@ -193,7 +193,7 @@ typedef struct CPUSH4State { > > void sh4_translate_init(void); > SuperHCPU *cpu_sh4_init(const char *cpu_model); > -int cpu_sh4_exec(CPUSH4State * s); > +int cpu_sh4_exec(CPUState *s); > int cpu_sh4_signal_handler(int host_signum, void *pinfo, > void *puc); > int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, > diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h > index f5c9006..0522b65 100644 > --- a/target-sparc/cpu.h > +++ b/target-sparc/cpu.h > @@ -537,7 +537,7 @@ int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, > void gen_intermediate_code_init(CPUSPARCState *env); > > /* cpu-exec.c */ > -int cpu_sparc_exec(CPUSPARCState *s); > +int cpu_sparc_exec(CPUState *cpu); > > /* win_helper.c */ > target_ulong cpu_get_psr(CPUSPARCState *env1); > diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h > index 504f156..916ee27 100644 > --- a/target-tricore/cpu.h > +++ b/target-tricore/cpu.h > @@ -372,7 +372,7 @@ enum { > }; > > void cpu_state_reset(CPUTriCoreState *s); > -int cpu_tricore_exec(CPUTriCoreState *s); > +int cpu_tricore_exec(CPUState *cpu); > void tricore_tcg_init(void); > int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc); > > diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h > index 14dc862..45e31e5 100644 > --- a/target-unicore32/cpu.h > +++ b/target-unicore32/cpu.h > @@ -125,7 +125,6 @@ void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask) > #define cpu_exec uc32_cpu_exec > #define cpu_signal_handler uc32_cpu_signal_handler > > -int uc32_cpu_exec(CPUUniCore32State *s); > int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc); > > /* MMU modes definitions */ > @@ -141,6 +140,8 @@ static inline int cpu_mmu_index(CPUUniCore32State *env) > #include "cpu-qom.h" > #include "exec/exec-all.h" > > +int uc32_cpu_exec(CPUState *s); > + > UniCore32CPU *uc32_cpu_init(const char *cpu_model); > > #define cpu_init(cpu_model) CPU(uc32_cpu_init(cpu_model)) > diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h > index dfd0d1c..ef1a6e6 100644 > --- a/target-xtensa/cpu.h > +++ b/target-xtensa/cpu.h > @@ -383,7 +383,7 @@ XtensaCPU *cpu_xtensa_init(const char *cpu_model); > > void xtensa_translate_init(void); > void xtensa_breakpoint_handler(CPUState *cs); > -int cpu_xtensa_exec(CPUXtensaState *s); > +int cpu_xtensa_exec(CPUState *cpu); > void xtensa_register_core(XtensaConfigList *node); > void check_interrupts(CPUXtensaState *s); > void xtensa_irq_init(CPUXtensaState *env); > -- > 1.9.1 > >