From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19C54C432BE for ; Thu, 29 Jul 2021 15:25:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F3DC760F43 for ; Thu, 29 Jul 2021 15:25:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238016AbhG2PZC (ORCPT ); Thu, 29 Jul 2021 11:25:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238020AbhG2PXV (ORCPT ); Thu, 29 Jul 2021 11:23:21 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 281B4C0613D3; Thu, 29 Jul 2021 08:23:17 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id l4-20020a05600c1d04b02902506f89ad2dso5975353wms.1; Thu, 29 Jul 2021 08:23:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=rBpQQ4PrkRZY0WtM7KbjU/FjfELe0vopn+N+lTuqMUk=; b=Dr+kc8ks6iyXT9LWSb5Du3HdAHPz7RDalBOKm0Og6v/tOp9R0FVfTLQLEb6YjgcFAZ OODEOtCXWQbWffIcrKm4DBgFkXgZzYwHrt+TnvY8sHMYbODXN5+AC287YYQ1Ml2myFyc lrSos/ncgWbQkBjX/3rJpjjDb/w6OxPEEKcNHNnikoGDo+nLRGD2Lw+wleq+XK+7sWBw xn+dBHPBJMl5k0iAstt3pf8RPQLevB6s/P7bjl/Cxbw+u1yMBrE24gQMmZmmeVacKJeS a5VfkAXtDy6sJ6hPFJv0pet+bPSamucYCLdgJS/zhsmD74VZ85w4fHPzJiF4Ge1OKqbA dyDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=rBpQQ4PrkRZY0WtM7KbjU/FjfELe0vopn+N+lTuqMUk=; b=AC/GqKdxpMX74r0opqPEx49hHRW1AKZL3PWeD6PCGT42KhhUyt2hHkFNBf1Hg26AdX /OrOEaZjqbR5Tz42pXdXCzXv/BpfkHYYM2E3rZmH81ivBd8gc+o4bPBpu3t+Jw9Q/Ijt ITYOSUWntHJK6mj9eOBlA+eWiN7Yqt5xzQ1IH79W5Rbuh/NsFNNGuc/ef5AIi755Gy6o jg1JOkNkkHkwZjxBWgFS86DfrMsP43J15lOIu7K0z9NCGpmjgsX+6tFG95VgEx61Y5ZL 9tloEcabfJzHBJywkFqGKFr7mC2+4OhN/yvi1NnJUh6ieH6x6VbnsUSRptMnFc+RXslN Ax5A== X-Gm-Message-State: AOAM530qMHgLVVSzaaAJrERTs4c5hOVgv9rYEQofvZGWEEzL9A24zMcC zbm2/8/V8ACdJj7W8B44BoBegxNSRRyo79hEXs8= X-Google-Smtp-Source: ABdhPJxzPEUgqOVmodbHdeZsVfk006v7VDK8qP5MqAnzI/Dj02PkT1mP2Sz1xjDX1yMh4Lyhth6wY2YnuSQUJxmpC8s= X-Received: by 2002:a05:600c:4401:: with SMTP id u1mr15603401wmn.49.1627572195705; Thu, 29 Jul 2021 08:23:15 -0700 (PDT) MIME-Version: 1.0 References: <20210729200230.v2.1.I110b87677ef16d97397fb7c81c07a16e1f5d211e@changeid> <20210729200230.v2.2.I286ef007fcadd9e6ee3b2c0ad948f990735f9610@changeid> In-Reply-To: <20210729200230.v2.2.I286ef007fcadd9e6ee3b2c0ad948f990735f9610@changeid> From: Rob Clark Date: Thu, 29 Jul 2021 08:27:25 -0700 Message-ID: Subject: Re: [PATCH v2 2/3] drm/msm/a6xx: Use rev to identify SKU To: Akhil P Oommen Cc: freedreno , dri-devel , linux-arm-msm , Jordan Crouse , Matthias Kaehlcke , Jonathan Marek , Douglas Anderson , Daniel Vetter , David Airlie , Sai Prakash Ranjan , Sean Paul , Sharat Masetty , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jul 29, 2021 at 7:33 AM Akhil P Oommen wrote: > > Use rev instead of revn to identify the SKU. This is in > preparation to the introduction of 7c3 gpu which won't have a > revn. > > Signed-off-by: Akhil P Oommen > --- > > (no changes since v1) > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +++++------ > 1 file changed, 5 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 183b9f9..0da1a66 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1675,11 +1675,11 @@ static u32 a618_get_speed_bin(u32 fuse) > return UINT_MAX; > } > > -static u32 fuse_to_supp_hw(struct device *dev, u32 revn, u32 fuse) > +static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) > { > u32 val = UINT_MAX; > > - if (revn == 618) > + if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) Looks like adreno_cmp_rev() ended up in patch 3/3 when it should have been in this patch.. But I guess we could also move this into adreno_is_a618() and use that here BR, -R > val = a618_get_speed_bin(fuse); > > if (val == UINT_MAX) { > @@ -1692,8 +1692,7 @@ static u32 fuse_to_supp_hw(struct device *dev, u32 revn, u32 fuse) > return (1 << val); > } > > -static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu, > - u32 revn) > +static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) > { > u32 supp_hw = UINT_MAX; > u16 speedbin; > @@ -1714,7 +1713,7 @@ static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu, > } > speedbin = le16_to_cpu(speedbin); > > - supp_hw = fuse_to_supp_hw(dev, revn, speedbin); > + supp_hw = fuse_to_supp_hw(dev, rev, speedbin); > > done: > ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); > @@ -1785,7 +1784,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) > > a6xx_llc_slices_init(pdev, a6xx_gpu); > > - ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info->revn); > + ret = a6xx_set_supported_hw(&pdev->dev, config->rev); > if (ret) { > a6xx_destroy(&(a6xx_gpu->base.base)); > return ERR_PTR(ret); > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation. > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.5 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB3CEC4338F for ; Thu, 29 Jul 2021 15:23:19 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7BFFD601FF for ; Thu, 29 Jul 2021 15:23:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7BFFD601FF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 157156EDC6; Thu, 29 Jul 2021 15:23:19 +0000 (UTC) Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by gabe.freedesktop.org (Postfix) with ESMTPS id 33B476EDC2; Thu, 29 Jul 2021 15:23:17 +0000 (UTC) Received: by mail-wm1-x32e.google.com with SMTP id e25-20020a05600c4b99b0290253418ba0fbso4315227wmp.1; Thu, 29 Jul 2021 08:23:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=rBpQQ4PrkRZY0WtM7KbjU/FjfELe0vopn+N+lTuqMUk=; b=Dr+kc8ks6iyXT9LWSb5Du3HdAHPz7RDalBOKm0Og6v/tOp9R0FVfTLQLEb6YjgcFAZ OODEOtCXWQbWffIcrKm4DBgFkXgZzYwHrt+TnvY8sHMYbODXN5+AC287YYQ1Ml2myFyc lrSos/ncgWbQkBjX/3rJpjjDb/w6OxPEEKcNHNnikoGDo+nLRGD2Lw+wleq+XK+7sWBw xn+dBHPBJMl5k0iAstt3pf8RPQLevB6s/P7bjl/Cxbw+u1yMBrE24gQMmZmmeVacKJeS a5VfkAXtDy6sJ6hPFJv0pet+bPSamucYCLdgJS/zhsmD74VZ85w4fHPzJiF4Ge1OKqbA dyDw== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sean Paul , Sai Prakash Ranjan , Jonathan Marek , David Airlie , linux-arm-msm , Sharat Masetty , Douglas Anderson , dri-devel , Jordan Crouse , Matthias Kaehlcke , freedreno , Linux Kernel Mailing List Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, Jul 29, 2021 at 7:33 AM Akhil P Oommen wrote: > > Use rev instead of revn to identify the SKU. This is in > preparation to the introduction of 7c3 gpu which won't have a > revn. > > Signed-off-by: Akhil P Oommen > --- > > (no changes since v1) > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +++++------ > 1 file changed, 5 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 183b9f9..0da1a66 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1675,11 +1675,11 @@ static u32 a618_get_speed_bin(u32 fuse) > return UINT_MAX; > } > > -static u32 fuse_to_supp_hw(struct device *dev, u32 revn, u32 fuse) > +static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) > { > u32 val = UINT_MAX; > > - if (revn == 618) > + if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) Looks like adreno_cmp_rev() ended up in patch 3/3 when it should have been in this patch.. But I guess we could also move this into adreno_is_a618() and use that here BR, -R > val = a618_get_speed_bin(fuse); > > if (val == UINT_MAX) { > @@ -1692,8 +1692,7 @@ static u32 fuse_to_supp_hw(struct device *dev, u32 revn, u32 fuse) > return (1 << val); > } > > -static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu, > - u32 revn) > +static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) > { > u32 supp_hw = UINT_MAX; > u16 speedbin; > @@ -1714,7 +1713,7 @@ static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu, > } > speedbin = le16_to_cpu(speedbin); > > - supp_hw = fuse_to_supp_hw(dev, revn, speedbin); > + supp_hw = fuse_to_supp_hw(dev, rev, speedbin); > > done: > ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); > @@ -1785,7 +1784,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) > > a6xx_llc_slices_init(pdev, a6xx_gpu); > > - ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info->revn); > + ret = a6xx_set_supported_hw(&pdev->dev, config->rev); > if (ret) { > a6xx_destroy(&(a6xx_gpu->base.base)); > return ERR_PTR(ret); > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation. >