* [PATCH 0/5] Add Actions Semi S900 I2C support
@ 2018-06-23 16:11 ` Manivannan Sadhasivam
0 siblings, 0 replies; 18+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-23 16:11 UTC (permalink / raw
To: wsa, robh+dt, afaerber, linus.walleij, linux-i2c, liuwei, mp-cs,
96boards, devicetree, andy.shevchenko, daniel.thompson,
amit.kucheria, linux-arm-kernel, linux-gpio, linux-kernel, hzhang,
bdong, manivannanece23, thomas.liau, jeff.chen
Cc: Manivannan Sadhasivam
This patchset adds I2C controller support for Actions Semi S900 SoC.
This driver has been structured in a way such that there will be only
one controller driver for the whole OWL family series (S500, S700 and
S900 SoCs).
There are 6 I2C controllers with separate memory mapped register space.
The I2C controller can handle atmost two messages concatenated by a
repeated start via its internal address feature. Hence the driver
uses this feature for messages of length greater than 1. In those cases,
the first message of the combined message should be a `write` with maximum
message length 6 and the second message's maximum length should be 240 bytes.
As far as the bus speed is concerned, this driver only supports
Standard (100KHz) and High speed (400KHz) for now.
The pinctrl definitions are only available for I2C0, I2C1 and I2C2.
With the mux option available only for I2C0.
For Bubblegum-96 board utilizing the S900 SoC, only I2C1 and I2C2 which
are exposed on the Low speed expansion connector are enabled.
Thanks,
Mani
Manivannan Sadhasivam (5):
dt-bindings: i2c: Add binding for Actions Semi OWL I2C controller
arm64: dts: actions: Add Actions Semi S900 I2C controller nodes
arm64: dts: actions: Add pinctrl definition for S900 I2C controller
arm64: dts: actions: Enable I2C1 and I2C2 in Bubblegum-96 board
i2c: Add Actions Semi OWL family S900 I2C driver
.../devicetree/bindings/i2c/i2c-owl.txt | 27 ++
.../dts/actions/s900-bubblegum-96-pins.dtsi | 29 ++
.../boot/dts/actions/s900-bubblegum-96.dts | 11 +
arch/arm64/boot/dts/actions/s900.dtsi | 60 +++
drivers/i2c/busses/Kconfig | 7 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-owl.c | 459 ++++++++++++++++++
7 files changed, 594 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.txt
create mode 100644 arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi
create mode 100644 drivers/i2c/busses/i2c-owl.c
--
2.17.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 0/5] Add Actions Semi S900 I2C support
@ 2018-06-23 16:11 ` Manivannan Sadhasivam
0 siblings, 0 replies; 18+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-23 16:11 UTC (permalink / raw
To: linux-arm-kernel
This patchset adds I2C controller support for Actions Semi S900 SoC.
This driver has been structured in a way such that there will be only
one controller driver for the whole OWL family series (S500, S700 and
S900 SoCs).
There are 6 I2C controllers with separate memory mapped register space.
The I2C controller can handle atmost two messages concatenated by a
repeated start via its internal address feature. Hence the driver
uses this feature for messages of length greater than 1. In those cases,
the first message of the combined message should be a `write` with maximum
message length 6 and the second message's maximum length should be 240 bytes.
As far as the bus speed is concerned, this driver only supports
Standard (100KHz) and High speed (400KHz) for now.
The pinctrl definitions are only available for I2C0, I2C1 and I2C2.
With the mux option available only for I2C0.
For Bubblegum-96 board utilizing the S900 SoC, only I2C1 and I2C2 which
are exposed on the Low speed expansion connector are enabled.
Thanks,
Mani
Manivannan Sadhasivam (5):
dt-bindings: i2c: Add binding for Actions Semi OWL I2C controller
arm64: dts: actions: Add Actions Semi S900 I2C controller nodes
arm64: dts: actions: Add pinctrl definition for S900 I2C controller
arm64: dts: actions: Enable I2C1 and I2C2 in Bubblegum-96 board
i2c: Add Actions Semi OWL family S900 I2C driver
.../devicetree/bindings/i2c/i2c-owl.txt | 27 ++
.../dts/actions/s900-bubblegum-96-pins.dtsi | 29 ++
.../boot/dts/actions/s900-bubblegum-96.dts | 11 +
arch/arm64/boot/dts/actions/s900.dtsi | 60 +++
drivers/i2c/busses/Kconfig | 7 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-owl.c | 459 ++++++++++++++++++
7 files changed, 594 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.txt
create mode 100644 arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi
create mode 100644 drivers/i2c/busses/i2c-owl.c
--
2.17.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/5] dt-bindings: i2c: Add binding for Actions Semi OWL I2C controller
2018-06-23 16:11 ` Manivannan Sadhasivam
@ 2018-06-23 16:11 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 18+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-23 16:11 UTC (permalink / raw
To: wsa, robh+dt, afaerber, linus.walleij, linux-i2c, liuwei, mp-cs,
96boards, devicetree, andy.shevchenko, daniel.thompson,
amit.kucheria, linux-arm-kernel, linux-gpio, linux-kernel, hzhang,
bdong, manivannanece23, thomas.liau, jeff.chen
Cc: Manivannan Sadhasivam
Add devicetree binding for Actions Semi OWL I2C controller
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
.../devicetree/bindings/i2c/i2c-owl.txt | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-owl.txt b/Documentation/devicetree/bindings/i2c/i2c-owl.txt
new file mode 100644
index 000000000000..9b691968cffd
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-owl.txt
@@ -0,0 +1,27 @@
+OWL I2C controller
+
+Required properties:
+
+- compatible : Should be "actions,s900-i2c".
+- reg : Offset and length of the register set for the device.
+- #address-cells : Should be 1.
+- #size-cells : Should be 0.
+- interrupts : A single interrupt specifier.
+- clocks : Phandle of the clock feeding the I2C controller.
+
+Optional properties:
+
+- clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and
+ Fast modes are supported, possible values are 100000 and
+ 400000.
+Examples:
+
+ i2c0: i2c@e0170000 {
+ compatible = "actions,s900-i2c";
+ reg = <0 0xe0170000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_I2C0>;
+ clock-frequency = <100000>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 1/5] dt-bindings: i2c: Add binding for Actions Semi OWL I2C controller
@ 2018-06-23 16:11 ` Manivannan Sadhasivam
0 siblings, 0 replies; 18+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-23 16:11 UTC (permalink / raw
To: linux-arm-kernel
Add devicetree binding for Actions Semi OWL I2C controller
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
.../devicetree/bindings/i2c/i2c-owl.txt | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-owl.txt b/Documentation/devicetree/bindings/i2c/i2c-owl.txt
new file mode 100644
index 000000000000..9b691968cffd
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-owl.txt
@@ -0,0 +1,27 @@
+OWL I2C controller
+
+Required properties:
+
+- compatible : Should be "actions,s900-i2c".
+- reg : Offset and length of the register set for the device.
+- #address-cells : Should be 1.
+- #size-cells : Should be 0.
+- interrupts : A single interrupt specifier.
+- clocks : Phandle of the clock feeding the I2C controller.
+
+Optional properties:
+
+- clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and
+ Fast modes are supported, possible values are 100000 and
+ 400000.
+Examples:
+
+ i2c0: i2c at e0170000 {
+ compatible = "actions,s900-i2c";
+ reg = <0 0xe0170000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_I2C0>;
+ clock-frequency = <100000>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/5] arm64: dts: actions: Add Actions Semi S900 I2C controller nodes
2018-06-23 16:11 ` Manivannan Sadhasivam
@ 2018-06-23 16:11 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 18+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-23 16:11 UTC (permalink / raw
To: wsa, robh+dt, afaerber, linus.walleij, linux-i2c, liuwei, mp-cs,
96boards, devicetree, andy.shevchenko, daniel.thompson,
amit.kucheria, linux-arm-kernel, linux-gpio, linux-kernel, hzhang,
bdong, manivannanece23, thomas.liau, jeff.chen
Cc: Manivannan Sadhasivam
Add I2C controller nodes for Actions Semi S900 SoC.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/actions/s900.dtsi | 60 +++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi
index 7ae8b931f000..6f7b89edbe4d 100644
--- a/arch/arm64/boot/dts/actions/s900.dtsi
+++ b/arch/arm64/boot/dts/actions/s900.dtsi
@@ -174,6 +174,66 @@
#clock-cells = <1>;
};
+ i2c0: i2c@e0170000 {
+ compatible = "actions,s900-i2c";
+ reg = <0 0xe0170000 0 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_default>;
+ };
+
+ i2c1: i2c@e0172000 {
+ compatible = "actions,s900-i2c";
+ reg = <0 0xe0172000 0 0x1000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_default>;
+ };
+
+ i2c2: i2c@e0174000 {
+ compatible = "actions,s900-i2c";
+ reg = <0 0xe0174000 0 0x1000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_default>;
+ };
+
+ i2c3: i2c@e0176000 {
+ compatible = "actions,s900-i2c";
+ reg = <0 0xe0176000 0 0x1000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e0178000 {
+ compatible = "actions,s900-i2c";
+ reg = <0 0xe0178000 0 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@e017a000 {
+ compatible = "actions,s900-i2c";
+ reg = <0 0xe017a000 0 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
pinctrl: pinctrl@e01b0000 {
compatible = "actions,s900-pinctrl";
reg = <0x0 0xe01b0000 0x0 0x1000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/5] arm64: dts: actions: Add Actions Semi S900 I2C controller nodes
@ 2018-06-23 16:11 ` Manivannan Sadhasivam
0 siblings, 0 replies; 18+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-23 16:11 UTC (permalink / raw
To: linux-arm-kernel
Add I2C controller nodes for Actions Semi S900 SoC.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/actions/s900.dtsi | 60 +++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi
index 7ae8b931f000..6f7b89edbe4d 100644
--- a/arch/arm64/boot/dts/actions/s900.dtsi
+++ b/arch/arm64/boot/dts/actions/s900.dtsi
@@ -174,6 +174,66 @@
#clock-cells = <1>;
};
+ i2c0: i2c at e0170000 {
+ compatible = "actions,s900-i2c";
+ reg = <0 0xe0170000 0 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_default>;
+ };
+
+ i2c1: i2c at e0172000 {
+ compatible = "actions,s900-i2c";
+ reg = <0 0xe0172000 0 0x1000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_default>;
+ };
+
+ i2c2: i2c at e0174000 {
+ compatible = "actions,s900-i2c";
+ reg = <0 0xe0174000 0 0x1000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_default>;
+ };
+
+ i2c3: i2c at e0176000 {
+ compatible = "actions,s900-i2c";
+ reg = <0 0xe0176000 0 0x1000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c at e0178000 {
+ compatible = "actions,s900-i2c";
+ reg = <0 0xe0178000 0 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c at e017a000 {
+ compatible = "actions,s900-i2c";
+ reg = <0 0xe017a000 0 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
pinctrl: pinctrl at e01b0000 {
compatible = "actions,s900-pinctrl";
reg = <0x0 0xe01b0000 0x0 0x1000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/5] arm64: dts: actions: Add pinctrl definition for S900 I2C controller
2018-06-23 16:11 ` Manivannan Sadhasivam
@ 2018-06-23 16:11 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 18+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-23 16:11 UTC (permalink / raw
To: wsa, robh+dt, afaerber, linus.walleij, linux-i2c, liuwei, mp-cs,
96boards, devicetree, andy.shevchenko, daniel.thompson,
amit.kucheria, linux-arm-kernel, linux-gpio, linux-kernel, hzhang,
bdong, manivannanece23, thomas.liau, jeff.chen
Cc: Manivannan Sadhasivam
Add pinctrl definition for Actions Semi S900 I2C controller. Pinctrl
definitions are only available for I2C0, I2C1, and I2C2.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
.../dts/actions/s900-bubblegum-96-pins.dtsi | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi
diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi b/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi
new file mode 100644
index 000000000000..e46ae187b27e
--- /dev/null
+++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+&pinctrl {
+
+ i2c0_default: i2c0_default {
+ pinmux {
+ groups = "i2c0_mfp";
+ function = "i2c0";
+ };
+ pinconf {
+ pins = "i2c0_sclk", "i2c0_sdata";
+ bias-pull-up;
+ };
+ };
+
+ i2c1_default: i2c1_default {
+ pinconf {
+ pins = "i2c1_sclk", "i2c1_sdata";
+ bias-pull-up;
+ };
+ };
+
+ i2c2_default: i2c2_default {
+ pinconf {
+ pins = "i2c2_sclk", "i2c2_sdata";
+ bias-pull-up;
+ };
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/5] arm64: dts: actions: Add pinctrl definition for S900 I2C controller
@ 2018-06-23 16:11 ` Manivannan Sadhasivam
0 siblings, 0 replies; 18+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-23 16:11 UTC (permalink / raw
To: linux-arm-kernel
Add pinctrl definition for Actions Semi S900 I2C controller. Pinctrl
definitions are only available for I2C0, I2C1, and I2C2.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
.../dts/actions/s900-bubblegum-96-pins.dtsi | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi
diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi b/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi
new file mode 100644
index 000000000000..e46ae187b27e
--- /dev/null
+++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+&pinctrl {
+
+ i2c0_default: i2c0_default {
+ pinmux {
+ groups = "i2c0_mfp";
+ function = "i2c0";
+ };
+ pinconf {
+ pins = "i2c0_sclk", "i2c0_sdata";
+ bias-pull-up;
+ };
+ };
+
+ i2c1_default: i2c1_default {
+ pinconf {
+ pins = "i2c1_sclk", "i2c1_sdata";
+ bias-pull-up;
+ };
+ };
+
+ i2c2_default: i2c2_default {
+ pinconf {
+ pins = "i2c2_sclk", "i2c2_sdata";
+ bias-pull-up;
+ };
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/5] arm64: dts: actions: Enable I2C1 and I2C2 in Bubblegum-96 board
2018-06-23 16:11 ` Manivannan Sadhasivam
@ 2018-06-23 16:11 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 18+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-23 16:11 UTC (permalink / raw
To: wsa, robh+dt, afaerber, linus.walleij, linux-i2c, liuwei, mp-cs,
96boards, devicetree, andy.shevchenko, daniel.thompson,
amit.kucheria, linux-arm-kernel, linux-gpio, linux-kernel, hzhang,
bdong, manivannanece23, thomas.liau, jeff.chen
Cc: Manivannan Sadhasivam
Enable I2C1 and I2C2 exposed on the low speed expansion connector in
Bubblegum-96 board.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/actions/s900-bubblegum-96.dts | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
index d0ba35df9015..57ae374cfb5a 100644
--- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
+++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "s900.dtsi"
+#include "s900-bubblegum-96-pins.dtsi"
/ {
compatible = "ucrobotics,bubblegum-96", "actions,s900";
@@ -35,6 +36,16 @@
clocks = <&cmu CLK_UART5>;
};
+&i2c1 {
+ status = "okay";
+ clocks = <&cmu CLK_I2C1>;
+};
+
+&i2c2 {
+ status = "okay";
+ clocks = <&cmu CLK_I2C2>;
+};
+
/*
* GPIO name legend: proper name = the GPIO line is used as GPIO
* NC = not connected (pin out but not routed from the chip to
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/5] arm64: dts: actions: Enable I2C1 and I2C2 in Bubblegum-96 board
@ 2018-06-23 16:11 ` Manivannan Sadhasivam
0 siblings, 0 replies; 18+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-23 16:11 UTC (permalink / raw
To: linux-arm-kernel
Enable I2C1 and I2C2 exposed on the low speed expansion connector in
Bubblegum-96 board.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/actions/s900-bubblegum-96.dts | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
index d0ba35df9015..57ae374cfb5a 100644
--- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
+++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "s900.dtsi"
+#include "s900-bubblegum-96-pins.dtsi"
/ {
compatible = "ucrobotics,bubblegum-96", "actions,s900";
@@ -35,6 +36,16 @@
clocks = <&cmu CLK_UART5>;
};
+&i2c1 {
+ status = "okay";
+ clocks = <&cmu CLK_I2C1>;
+};
+
+&i2c2 {
+ status = "okay";
+ clocks = <&cmu CLK_I2C2>;
+};
+
/*
* GPIO name legend: proper name = the GPIO line is used as GPIO
* NC = not connected (pin out but not routed from the chip to
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 5/5] i2c: Add Actions Semi OWL family S900 I2C driver
2018-06-23 16:11 ` Manivannan Sadhasivam
@ 2018-06-23 16:11 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 18+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-23 16:11 UTC (permalink / raw
To: wsa, robh+dt, afaerber, linus.walleij, linux-i2c, liuwei, mp-cs,
96boards, devicetree, andy.shevchenko, daniel.thompson,
amit.kucheria, linux-arm-kernel, linux-gpio, linux-kernel, hzhang,
bdong, manivannanece23, thomas.liau, jeff.chen
Cc: Manivannan Sadhasivam
Add Actions Semi OWL family S900 I2C driver.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/i2c/busses/Kconfig | 7 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-owl.c | 459 +++++++++++++++++++++++++++++++++++
3 files changed, 467 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-owl.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 4f8df2ec87b1..2062da17e33b 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -762,6 +762,13 @@ config I2C_OMAP
Like OMAP1510/1610/1710/5912 and OMAP242x.
For details see http://www.ti.com/omap.
+config I2C_OWL
+ tristate "OWL I2C Controller"
+ depends on ARCH_ACTIONS || COMPILE_TEST
+ help
+ Say Y here if you want to use the I2C bus controller on
+ the Actions Semi OWL SoCs.
+
config I2C_PASEMI
tristate "PA Semi SMBus interface"
depends on PPC_PASEMI && PCI
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 5a869144a0c5..b71618f77880 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_MXS) += i2c-mxs.o
obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o
obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o
obj-$(CONFIG_I2C_OMAP) += i2c-omap.o
+obj-$(CONFIG_I2C_OWL) += i2c-owl.o
obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o
obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pca-platform.o
obj-$(CONFIG_I2C_PMCMSP) += i2c-pmcmsp.o
diff --git a/drivers/i2c/busses/i2c-owl.c b/drivers/i2c/busses/i2c-owl.c
new file mode 100644
index 000000000000..53100ddfb3cc
--- /dev/null
+++ b/drivers/i2c/busses/i2c-owl.c
@@ -0,0 +1,459 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * OWL SoC's I2C driver
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Author: David Liu <liuwei@actions-semi.com>
+ *
+ * Copyright (c) 2018 Linaro Ltd.
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/io.h>
+
+/* I2C registers */
+#define OWL_I2C_REG_CTL (0x0000)
+#define OWL_I2C_REG_CLKDIV (0x0004)
+#define OWL_I2C_REG_STAT (0x0008)
+#define OWL_I2C_REG_ADDR (0x000C)
+#define OWL_I2C_REG_TXDAT (0x0010)
+#define OWL_I2C_REG_RXDAT (0x0014)
+#define OWL_I2C_REG_CMD (0x0018)
+#define OWL_I2C_REG_FIFOCTL (0x001C)
+#define OWL_I2C_REG_FIFOSTAT (0x0020)
+#define OWL_I2C_REG_DATCNT (0x0024)
+#define OWL_I2C_REG_RCNT (0x0028)
+
+/* I2Cx_CTL Bit Mask */
+#define OWL_I2C_CTL_RB BIT(1)
+#define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2)
+#define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0)
+#define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1)
+#define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2)
+#define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3)
+#define OWL_I2C_CTL_IRQE BIT(5)
+#define OWL_I2C_CTL_EN BIT(7)
+#define OWL_I2C_CTL_AE BIT(8)
+#define OWL_I2C_CTL_SHSM BIT(10)
+
+#define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff)
+
+/* I2Cx_STAT Bit Mask */
+#define OWL_I2C_STAT_RACK BIT(0)
+#define OWL_I2C_STAT_BEB BIT(1)
+#define OWL_I2C_STAT_IRQP BIT(2)
+#define OWL_I2C_STAT_LAB BIT(3)
+#define OWL_I2C_STAT_STPD BIT(4)
+#define OWL_I2C_STAT_STAD BIT(5)
+#define OWL_I2C_STAT_BBB BIT(6)
+#define OWL_I2C_STAT_TCB BIT(7)
+#define OWL_I2C_STAT_LBST BIT(8)
+#define OWL_I2C_STAT_SAMB BIT(9)
+#define OWL_I2C_STAT_SRGC BIT(10)
+
+/* I2Cx_CMD Bit Mask */
+#define OWL_I2C_CMD_SBE BIT(0)
+#define OWL_I2C_CMD_RBE BIT(4)
+#define OWL_I2C_CMD_DE BIT(8)
+#define OWL_I2C_CMD_NS BIT(9)
+#define OWL_I2C_CMD_SE BIT(10)
+#define OWL_I2C_CMD_MSS BIT(11)
+#define OWL_I2C_CMD_WRS BIT(12)
+#define OWL_I2C_CMD_SECL BIT(15)
+
+#define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1)
+#define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5)
+
+/* I2Cx_FIFOCTL Bit Mask */
+#define OWL_I2C_FIFOCTL_NIB BIT(0)
+#define OWL_I2C_FIFOCTL_RFR BIT(1)
+#define OWL_I2C_FIFOCTL_TFR BIT(2)
+
+/* I2Cc_FIFOSTAT Bit Mask */
+#define OWL_I2C_FIFOSTAT_RNB BIT(1)
+#define OWL_I2C_FIFOSTAT_RFE BIT(2)
+#define OWL_I2C_FIFOSTAT_TFF BIT(5)
+#define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16)
+#define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8)
+
+/* I2C bus timeout */
+#define OWL_I2C_TIMEOUT (msecs_to_jiffies(4 * 1000))
+
+#define OWL_I2C_DEFAULT_SPEED 100000
+#define OWL_I2C_MAX_SPEED 400000
+
+struct owl_i2c_dev {
+ struct i2c_adapter adap;
+ struct i2c_msg *msg;
+ struct completion msg_complete;
+ struct clk *clk;
+ void __iomem *base;
+ unsigned long clk_rate;
+ u32 bus_freq;
+ u32 msg_ptr;
+};
+
+static void owl_i2c_update_reg(void __iomem *base, unsigned int val, bool state)
+{
+ unsigned int regval;
+
+ regval = readl(base);
+
+ if (state)
+ regval |= val;
+ else
+ regval &= ~val;
+
+ writel(regval, base);
+}
+
+static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev)
+{
+ unsigned int val;
+
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
+ OWL_I2C_CTL_EN, false);
+ mdelay(1);
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
+ OWL_I2C_CTL_EN, true);
+
+ /* Reset FIFO */
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
+ OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR,
+ true);
+
+ /* Wait until FIFO reset complete */
+ do {
+ val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL);
+ if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR)))
+ break;
+ } while (1);
+
+ /* Clear status registers */
+ writel(0, i2c_dev->base + OWL_I2C_REG_STAT);
+}
+
+static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev)
+{
+ unsigned int val;
+
+ val = (i2c_dev->clk_rate + i2c_dev->bus_freq * 16 - 1) /
+ (i2c_dev->bus_freq * 16);
+
+ /* Set clock divider factor */
+ writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV);
+}
+
+static void owl_i2c_hw_init(struct owl_i2c_dev *i2c_dev)
+{
+ /* Reset I2C controller */
+ owl_i2c_reset(i2c_dev);
+
+ /* Set bus frequency */
+ owl_i2c_set_freq(i2c_dev);
+}
+
+static irqreturn_t owl_i2c_interrupt(int irq, void *_dev)
+{
+ struct owl_i2c_dev *i2c_dev = _dev;
+ struct i2c_msg *msg = i2c_dev->msg;
+ unsigned int stat, fifostat;
+
+ fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT);
+ if (fifostat & OWL_I2C_FIFOSTAT_RNB) {
+ dev_warn(&i2c_dev->adap.dev, "received NACK from device");
+ owl_i2c_reset(i2c_dev);
+ goto stop;
+ }
+
+ stat = readl(i2c_dev->base + OWL_I2C_REG_STAT);
+ if (stat & OWL_I2C_STAT_BEB) {
+ dev_warn(&i2c_dev->adap.dev, "bus error");
+ owl_i2c_reset(i2c_dev);
+ goto stop;
+ }
+
+ /* Handle FIFO read */
+ if (msg->flags & I2C_M_RD) {
+ while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
+ OWL_I2C_FIFOSTAT_RFE) &&
+ (i2c_dev->msg_ptr < msg->len)) {
+ msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base +
+ OWL_I2C_REG_RXDAT);
+ }
+ } else {
+ /* Handle the remaining bytes which were not sent */
+ while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
+ OWL_I2C_FIFOSTAT_TFF) &&
+ i2c_dev->msg_ptr < msg->len) {
+ writel(msg->buf[i2c_dev->msg_ptr++], i2c_dev->base +
+ OWL_I2C_REG_TXDAT);
+ }
+ }
+
+stop:
+ /* Clear pending interrupts */
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
+ OWL_I2C_STAT_IRQP, true);
+
+ complete_all(&i2c_dev->msg_complete);
+
+ return IRQ_HANDLED;
+}
+
+static u32 owl_i2c_func(struct i2c_adapter *adap)
+{
+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static int owl_i2c_check_bus_busy(struct i2c_adapter *adap)
+{
+ struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+ unsigned long timeout;
+ unsigned int val;
+
+ timeout = jiffies + OWL_I2C_TIMEOUT;
+ while (1) {
+ val = readl(i2c_dev->base + OWL_I2C_REG_STAT);
+
+ /* Check for Arbitration lost */
+ if (val & OWL_I2C_STAT_LAB) {
+ val &= ~OWL_I2C_STAT_LAB;
+ writel(val, i2c_dev->base + OWL_I2C_REG_STAT);
+ return -EAGAIN;
+ }
+
+ /* Check for Bus busy */
+ if (!(val & OWL_I2C_STAT_BBB))
+ break;
+
+ if (time_after(jiffies, timeout)) {
+ dev_err(&adap->dev, "Bus busy timeout");
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
+static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
+ int num)
+{
+ struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+ struct i2c_msg *msg;
+ unsigned long time_left;
+ unsigned int i2c_cmd;
+ unsigned int addr;
+ int ret = 0, idx;
+
+ owl_i2c_hw_init(i2c_dev);
+
+ ret = owl_i2c_check_bus_busy(adap);
+ if (ret)
+ return ret;
+
+ reinit_completion(&i2c_dev->msg_complete);
+
+ /* Enable I2C controller interrupt */
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
+ OWL_I2C_CTL_IRQE, true);
+
+ /*
+ * Select: FIFO enable, Master mode, Stop enable, Data count enable,
+ * Send start bit
+ */
+ i2c_cmd = (OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE
+ | OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE);
+
+ addr = (msgs[0].addr & 0x7f) << 1;
+
+ /* Handle repeated start condition */
+ if (num > 1) {
+ /* Set internal address length and enable repeated start */
+ i2c_cmd |= (OWL_I2C_CMD_AS(msgs[0].len + 1)
+ | OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE);
+
+ /* Write slave address */
+ writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
+
+ /* Write internal register address */
+ for (idx = 0; idx < msgs[0].len; idx++)
+ writel(msgs[0].buf[idx], i2c_dev->base +
+ OWL_I2C_REG_TXDAT);
+
+ msg = &msgs[1];
+ } else {
+ /* Set address length */
+ i2c_cmd |= OWL_I2C_CMD_AS(1);
+ msg = &msgs[0];
+ }
+
+ i2c_dev->msg = msg;
+ i2c_dev->msg_ptr = 0;
+
+ /* Set data count for the message */
+ writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT);
+
+ if (msg->flags & I2C_M_RD) {
+ writel((addr | 1), i2c_dev->base + OWL_I2C_REG_TXDAT);
+ } else {
+ writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
+
+ /* Write data to FIFO */
+ for (idx = 0; idx < msg->len; idx++) {
+ /* Check for FIFO full */
+ if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT)
+ & OWL_I2C_FIFOSTAT_TFF)
+ break;
+
+ writel(msg->buf[idx],
+ i2c_dev->base + OWL_I2C_REG_TXDAT);
+ }
+
+ i2c_dev->msg_ptr = idx;
+ }
+
+ /* Ingore the NACK if needed */
+ if (msg->flags & I2C_M_IGNORE_NAK)
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
+ OWL_I2C_FIFOCTL_NIB, true);
+ else
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
+ OWL_I2C_FIFOCTL_NIB, false);
+
+ /* Start the transfer */
+ writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD);
+
+ time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
+ adap->timeout);
+ if (time_left == 0) {
+ dev_err(&adap->dev, "Transaction timed out");
+ /* Send stop condition and release the bus */
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
+ OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB, true);
+ ret = -ETIMEDOUT;
+ }
+
+ /* Disable I2C controller */
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
+ OWL_I2C_CTL_EN, false);
+
+ return i2c_dev->msg_ptr;
+}
+
+static const struct i2c_algorithm owl_i2c_algorithm = {
+ .master_xfer = owl_i2c_master_xfer,
+ .functionality = owl_i2c_func
+};
+
+static const struct i2c_adapter_quirks owl_i2c_quirks = {
+ .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST,
+ .max_read_len = 240,
+ .max_write_len = 240,
+ .max_comb_1st_msg_len = 6,
+ .max_comb_2nd_msg_len = 240
+};
+
+static int owl_i2c_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct owl_i2c_dev *i2c_dev;
+ struct resource *res;
+ int ret, irq;
+
+ i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL);
+ if (!i2c_dev)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ i2c_dev->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(i2c_dev->base))
+ return PTR_ERR(i2c_dev->base);
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(dev, "failed to get IRQ number\n");
+ return irq;
+ }
+
+ if (of_property_read_u32(dev->of_node, "clock-frequency",
+ &i2c_dev->bus_freq))
+ i2c_dev->bus_freq = OWL_I2C_DEFAULT_SPEED;
+
+ /* We support only frequencies of 100k and 400k for now */
+ if (i2c_dev->bus_freq != OWL_I2C_DEFAULT_SPEED &&
+ i2c_dev->bus_freq > OWL_I2C_MAX_SPEED) {
+ dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq);
+ return -EINVAL;
+ }
+
+ i2c_dev->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(i2c_dev->clk)) {
+ dev_err(dev, "failed to get clock\n");
+ return PTR_ERR(i2c_dev->clk);
+ }
+
+ ret = clk_prepare_enable(i2c_dev->clk);
+ if (ret)
+ return ret;
+
+ i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk);
+ if (!i2c_dev->clk_rate) {
+ dev_err(dev, "input clock rate should not be zero\n");
+ ret = -EINVAL;
+ goto disable_clk;
+ }
+
+ init_completion(&i2c_dev->msg_complete);
+ i2c_dev->adap.owner = THIS_MODULE;
+ i2c_dev->adap.algo = &owl_i2c_algorithm;
+ i2c_dev->adap.timeout = OWL_I2C_TIMEOUT;
+ i2c_dev->adap.quirks = &owl_i2c_quirks;
+ i2c_dev->adap.dev.parent = dev;
+ i2c_dev->adap.dev.of_node = dev->of_node;
+ snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
+ "%s", "OWL I2C adapter");
+ i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
+
+ platform_set_drvdata(pdev, i2c_dev);
+
+ ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name,
+ i2c_dev);
+ if (ret) {
+ dev_err(dev, "failed to request irq %d\n", irq);
+ goto disable_clk;
+ }
+
+ ret = i2c_add_adapter(&i2c_dev->adap);
+disable_clk:
+ if (ret)
+ clk_disable_unprepare(i2c_dev->clk);
+
+ return ret;
+}
+
+static const struct of_device_id owl_i2c_of_match[] = {
+ {.compatible = "actions,s900-i2c"},
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, owl_i2c_of_match);
+
+static struct platform_driver owl_i2c_driver = {
+ .probe = owl_i2c_probe,
+ .driver = {
+ .name = "owl-i2c",
+ .of_match_table = of_match_ptr(owl_i2c_of_match),
+ },
+};
+module_platform_driver(owl_i2c_driver);
+
+MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>");
+MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
+MODULE_DESCRIPTION("Actions Semi OWL SoCs I2C driver");
+MODULE_LICENSE("GPL");
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 5/5] i2c: Add Actions Semi OWL family S900 I2C driver
@ 2018-06-23 16:11 ` Manivannan Sadhasivam
0 siblings, 0 replies; 18+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-23 16:11 UTC (permalink / raw
To: linux-arm-kernel
Add Actions Semi OWL family S900 I2C driver.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/i2c/busses/Kconfig | 7 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-owl.c | 459 +++++++++++++++++++++++++++++++++++
3 files changed, 467 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-owl.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 4f8df2ec87b1..2062da17e33b 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -762,6 +762,13 @@ config I2C_OMAP
Like OMAP1510/1610/1710/5912 and OMAP242x.
For details see http://www.ti.com/omap.
+config I2C_OWL
+ tristate "OWL I2C Controller"
+ depends on ARCH_ACTIONS || COMPILE_TEST
+ help
+ Say Y here if you want to use the I2C bus controller on
+ the Actions Semi OWL SoCs.
+
config I2C_PASEMI
tristate "PA Semi SMBus interface"
depends on PPC_PASEMI && PCI
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 5a869144a0c5..b71618f77880 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_MXS) += i2c-mxs.o
obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o
obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o
obj-$(CONFIG_I2C_OMAP) += i2c-omap.o
+obj-$(CONFIG_I2C_OWL) += i2c-owl.o
obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o
obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pca-platform.o
obj-$(CONFIG_I2C_PMCMSP) += i2c-pmcmsp.o
diff --git a/drivers/i2c/busses/i2c-owl.c b/drivers/i2c/busses/i2c-owl.c
new file mode 100644
index 000000000000..53100ddfb3cc
--- /dev/null
+++ b/drivers/i2c/busses/i2c-owl.c
@@ -0,0 +1,459 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * OWL SoC's I2C driver
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Author: David Liu <liuwei@actions-semi.com>
+ *
+ * Copyright (c) 2018 Linaro Ltd.
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/io.h>
+
+/* I2C registers */
+#define OWL_I2C_REG_CTL (0x0000)
+#define OWL_I2C_REG_CLKDIV (0x0004)
+#define OWL_I2C_REG_STAT (0x0008)
+#define OWL_I2C_REG_ADDR (0x000C)
+#define OWL_I2C_REG_TXDAT (0x0010)
+#define OWL_I2C_REG_RXDAT (0x0014)
+#define OWL_I2C_REG_CMD (0x0018)
+#define OWL_I2C_REG_FIFOCTL (0x001C)
+#define OWL_I2C_REG_FIFOSTAT (0x0020)
+#define OWL_I2C_REG_DATCNT (0x0024)
+#define OWL_I2C_REG_RCNT (0x0028)
+
+/* I2Cx_CTL Bit Mask */
+#define OWL_I2C_CTL_RB BIT(1)
+#define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2)
+#define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0)
+#define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1)
+#define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2)
+#define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3)
+#define OWL_I2C_CTL_IRQE BIT(5)
+#define OWL_I2C_CTL_EN BIT(7)
+#define OWL_I2C_CTL_AE BIT(8)
+#define OWL_I2C_CTL_SHSM BIT(10)
+
+#define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff)
+
+/* I2Cx_STAT Bit Mask */
+#define OWL_I2C_STAT_RACK BIT(0)
+#define OWL_I2C_STAT_BEB BIT(1)
+#define OWL_I2C_STAT_IRQP BIT(2)
+#define OWL_I2C_STAT_LAB BIT(3)
+#define OWL_I2C_STAT_STPD BIT(4)
+#define OWL_I2C_STAT_STAD BIT(5)
+#define OWL_I2C_STAT_BBB BIT(6)
+#define OWL_I2C_STAT_TCB BIT(7)
+#define OWL_I2C_STAT_LBST BIT(8)
+#define OWL_I2C_STAT_SAMB BIT(9)
+#define OWL_I2C_STAT_SRGC BIT(10)
+
+/* I2Cx_CMD Bit Mask */
+#define OWL_I2C_CMD_SBE BIT(0)
+#define OWL_I2C_CMD_RBE BIT(4)
+#define OWL_I2C_CMD_DE BIT(8)
+#define OWL_I2C_CMD_NS BIT(9)
+#define OWL_I2C_CMD_SE BIT(10)
+#define OWL_I2C_CMD_MSS BIT(11)
+#define OWL_I2C_CMD_WRS BIT(12)
+#define OWL_I2C_CMD_SECL BIT(15)
+
+#define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1)
+#define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5)
+
+/* I2Cx_FIFOCTL Bit Mask */
+#define OWL_I2C_FIFOCTL_NIB BIT(0)
+#define OWL_I2C_FIFOCTL_RFR BIT(1)
+#define OWL_I2C_FIFOCTL_TFR BIT(2)
+
+/* I2Cc_FIFOSTAT Bit Mask */
+#define OWL_I2C_FIFOSTAT_RNB BIT(1)
+#define OWL_I2C_FIFOSTAT_RFE BIT(2)
+#define OWL_I2C_FIFOSTAT_TFF BIT(5)
+#define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16)
+#define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8)
+
+/* I2C bus timeout */
+#define OWL_I2C_TIMEOUT (msecs_to_jiffies(4 * 1000))
+
+#define OWL_I2C_DEFAULT_SPEED 100000
+#define OWL_I2C_MAX_SPEED 400000
+
+struct owl_i2c_dev {
+ struct i2c_adapter adap;
+ struct i2c_msg *msg;
+ struct completion msg_complete;
+ struct clk *clk;
+ void __iomem *base;
+ unsigned long clk_rate;
+ u32 bus_freq;
+ u32 msg_ptr;
+};
+
+static void owl_i2c_update_reg(void __iomem *base, unsigned int val, bool state)
+{
+ unsigned int regval;
+
+ regval = readl(base);
+
+ if (state)
+ regval |= val;
+ else
+ regval &= ~val;
+
+ writel(regval, base);
+}
+
+static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev)
+{
+ unsigned int val;
+
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
+ OWL_I2C_CTL_EN, false);
+ mdelay(1);
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
+ OWL_I2C_CTL_EN, true);
+
+ /* Reset FIFO */
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
+ OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR,
+ true);
+
+ /* Wait until FIFO reset complete */
+ do {
+ val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL);
+ if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR)))
+ break;
+ } while (1);
+
+ /* Clear status registers */
+ writel(0, i2c_dev->base + OWL_I2C_REG_STAT);
+}
+
+static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev)
+{
+ unsigned int val;
+
+ val = (i2c_dev->clk_rate + i2c_dev->bus_freq * 16 - 1) /
+ (i2c_dev->bus_freq * 16);
+
+ /* Set clock divider factor */
+ writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV);
+}
+
+static void owl_i2c_hw_init(struct owl_i2c_dev *i2c_dev)
+{
+ /* Reset I2C controller */
+ owl_i2c_reset(i2c_dev);
+
+ /* Set bus frequency */
+ owl_i2c_set_freq(i2c_dev);
+}
+
+static irqreturn_t owl_i2c_interrupt(int irq, void *_dev)
+{
+ struct owl_i2c_dev *i2c_dev = _dev;
+ struct i2c_msg *msg = i2c_dev->msg;
+ unsigned int stat, fifostat;
+
+ fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT);
+ if (fifostat & OWL_I2C_FIFOSTAT_RNB) {
+ dev_warn(&i2c_dev->adap.dev, "received NACK from device");
+ owl_i2c_reset(i2c_dev);
+ goto stop;
+ }
+
+ stat = readl(i2c_dev->base + OWL_I2C_REG_STAT);
+ if (stat & OWL_I2C_STAT_BEB) {
+ dev_warn(&i2c_dev->adap.dev, "bus error");
+ owl_i2c_reset(i2c_dev);
+ goto stop;
+ }
+
+ /* Handle FIFO read */
+ if (msg->flags & I2C_M_RD) {
+ while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
+ OWL_I2C_FIFOSTAT_RFE) &&
+ (i2c_dev->msg_ptr < msg->len)) {
+ msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base +
+ OWL_I2C_REG_RXDAT);
+ }
+ } else {
+ /* Handle the remaining bytes which were not sent */
+ while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
+ OWL_I2C_FIFOSTAT_TFF) &&
+ i2c_dev->msg_ptr < msg->len) {
+ writel(msg->buf[i2c_dev->msg_ptr++], i2c_dev->base +
+ OWL_I2C_REG_TXDAT);
+ }
+ }
+
+stop:
+ /* Clear pending interrupts */
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
+ OWL_I2C_STAT_IRQP, true);
+
+ complete_all(&i2c_dev->msg_complete);
+
+ return IRQ_HANDLED;
+}
+
+static u32 owl_i2c_func(struct i2c_adapter *adap)
+{
+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static int owl_i2c_check_bus_busy(struct i2c_adapter *adap)
+{
+ struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+ unsigned long timeout;
+ unsigned int val;
+
+ timeout = jiffies + OWL_I2C_TIMEOUT;
+ while (1) {
+ val = readl(i2c_dev->base + OWL_I2C_REG_STAT);
+
+ /* Check for Arbitration lost */
+ if (val & OWL_I2C_STAT_LAB) {
+ val &= ~OWL_I2C_STAT_LAB;
+ writel(val, i2c_dev->base + OWL_I2C_REG_STAT);
+ return -EAGAIN;
+ }
+
+ /* Check for Bus busy */
+ if (!(val & OWL_I2C_STAT_BBB))
+ break;
+
+ if (time_after(jiffies, timeout)) {
+ dev_err(&adap->dev, "Bus busy timeout");
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
+static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
+ int num)
+{
+ struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
+ struct i2c_msg *msg;
+ unsigned long time_left;
+ unsigned int i2c_cmd;
+ unsigned int addr;
+ int ret = 0, idx;
+
+ owl_i2c_hw_init(i2c_dev);
+
+ ret = owl_i2c_check_bus_busy(adap);
+ if (ret)
+ return ret;
+
+ reinit_completion(&i2c_dev->msg_complete);
+
+ /* Enable I2C controller interrupt */
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
+ OWL_I2C_CTL_IRQE, true);
+
+ /*
+ * Select: FIFO enable, Master mode, Stop enable, Data count enable,
+ * Send start bit
+ */
+ i2c_cmd = (OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE
+ | OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE);
+
+ addr = (msgs[0].addr & 0x7f) << 1;
+
+ /* Handle repeated start condition */
+ if (num > 1) {
+ /* Set internal address length and enable repeated start */
+ i2c_cmd |= (OWL_I2C_CMD_AS(msgs[0].len + 1)
+ | OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE);
+
+ /* Write slave address */
+ writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
+
+ /* Write internal register address */
+ for (idx = 0; idx < msgs[0].len; idx++)
+ writel(msgs[0].buf[idx], i2c_dev->base +
+ OWL_I2C_REG_TXDAT);
+
+ msg = &msgs[1];
+ } else {
+ /* Set address length */
+ i2c_cmd |= OWL_I2C_CMD_AS(1);
+ msg = &msgs[0];
+ }
+
+ i2c_dev->msg = msg;
+ i2c_dev->msg_ptr = 0;
+
+ /* Set data count for the message */
+ writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT);
+
+ if (msg->flags & I2C_M_RD) {
+ writel((addr | 1), i2c_dev->base + OWL_I2C_REG_TXDAT);
+ } else {
+ writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
+
+ /* Write data to FIFO */
+ for (idx = 0; idx < msg->len; idx++) {
+ /* Check for FIFO full */
+ if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT)
+ & OWL_I2C_FIFOSTAT_TFF)
+ break;
+
+ writel(msg->buf[idx],
+ i2c_dev->base + OWL_I2C_REG_TXDAT);
+ }
+
+ i2c_dev->msg_ptr = idx;
+ }
+
+ /* Ingore the NACK if needed */
+ if (msg->flags & I2C_M_IGNORE_NAK)
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
+ OWL_I2C_FIFOCTL_NIB, true);
+ else
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
+ OWL_I2C_FIFOCTL_NIB, false);
+
+ /* Start the transfer */
+ writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD);
+
+ time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
+ adap->timeout);
+ if (time_left == 0) {
+ dev_err(&adap->dev, "Transaction timed out");
+ /* Send stop condition and release the bus */
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
+ OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB, true);
+ ret = -ETIMEDOUT;
+ }
+
+ /* Disable I2C controller */
+ owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
+ OWL_I2C_CTL_EN, false);
+
+ return i2c_dev->msg_ptr;
+}
+
+static const struct i2c_algorithm owl_i2c_algorithm = {
+ .master_xfer = owl_i2c_master_xfer,
+ .functionality = owl_i2c_func
+};
+
+static const struct i2c_adapter_quirks owl_i2c_quirks = {
+ .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST,
+ .max_read_len = 240,
+ .max_write_len = 240,
+ .max_comb_1st_msg_len = 6,
+ .max_comb_2nd_msg_len = 240
+};
+
+static int owl_i2c_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct owl_i2c_dev *i2c_dev;
+ struct resource *res;
+ int ret, irq;
+
+ i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL);
+ if (!i2c_dev)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ i2c_dev->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(i2c_dev->base))
+ return PTR_ERR(i2c_dev->base);
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(dev, "failed to get IRQ number\n");
+ return irq;
+ }
+
+ if (of_property_read_u32(dev->of_node, "clock-frequency",
+ &i2c_dev->bus_freq))
+ i2c_dev->bus_freq = OWL_I2C_DEFAULT_SPEED;
+
+ /* We support only frequencies of 100k and 400k for now */
+ if (i2c_dev->bus_freq != OWL_I2C_DEFAULT_SPEED &&
+ i2c_dev->bus_freq > OWL_I2C_MAX_SPEED) {
+ dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq);
+ return -EINVAL;
+ }
+
+ i2c_dev->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(i2c_dev->clk)) {
+ dev_err(dev, "failed to get clock\n");
+ return PTR_ERR(i2c_dev->clk);
+ }
+
+ ret = clk_prepare_enable(i2c_dev->clk);
+ if (ret)
+ return ret;
+
+ i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk);
+ if (!i2c_dev->clk_rate) {
+ dev_err(dev, "input clock rate should not be zero\n");
+ ret = -EINVAL;
+ goto disable_clk;
+ }
+
+ init_completion(&i2c_dev->msg_complete);
+ i2c_dev->adap.owner = THIS_MODULE;
+ i2c_dev->adap.algo = &owl_i2c_algorithm;
+ i2c_dev->adap.timeout = OWL_I2C_TIMEOUT;
+ i2c_dev->adap.quirks = &owl_i2c_quirks;
+ i2c_dev->adap.dev.parent = dev;
+ i2c_dev->adap.dev.of_node = dev->of_node;
+ snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
+ "%s", "OWL I2C adapter");
+ i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
+
+ platform_set_drvdata(pdev, i2c_dev);
+
+ ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name,
+ i2c_dev);
+ if (ret) {
+ dev_err(dev, "failed to request irq %d\n", irq);
+ goto disable_clk;
+ }
+
+ ret = i2c_add_adapter(&i2c_dev->adap);
+disable_clk:
+ if (ret)
+ clk_disable_unprepare(i2c_dev->clk);
+
+ return ret;
+}
+
+static const struct of_device_id owl_i2c_of_match[] = {
+ {.compatible = "actions,s900-i2c"},
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, owl_i2c_of_match);
+
+static struct platform_driver owl_i2c_driver = {
+ .probe = owl_i2c_probe,
+ .driver = {
+ .name = "owl-i2c",
+ .of_match_table = of_match_ptr(owl_i2c_of_match),
+ },
+};
+module_platform_driver(owl_i2c_driver);
+
+MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>");
+MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
+MODULE_DESCRIPTION("Actions Semi OWL SoCs I2C driver");
+MODULE_LICENSE("GPL");
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 5/5] i2c: Add Actions Semi OWL family S900 I2C driver
2018-06-23 16:11 ` Manivannan Sadhasivam
@ 2018-06-25 9:38 ` Andy Shevchenko
-1 siblings, 0 replies; 18+ messages in thread
From: Andy Shevchenko @ 2018-06-25 9:38 UTC (permalink / raw
To: Manivannan Sadhasivam
Cc: Wolfram Sang, Rob Herring, Andreas Färber, Linus Walleij,
linux-i2c, 刘炜, mp-cs, 96boards, devicetree,
Daniel Thompson, amit.kucheria, linux-arm Mailing List,
open list:GPIO SUBSYSTEM, Linux Kernel Mailing List, hzhang,
bdong, Mani Sadhasivam, Thomas Liau, jeff.chen
On Sat, Jun 23, 2018 at 7:11 PM, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
> Add Actions Semi OWL family S900 I2C driver.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> drivers/i2c/busses/Kconfig | 7 +
> drivers/i2c/busses/Makefile | 1 +
> drivers/i2c/busses/i2c-owl.c | 459 +++++++++++++++++++++++++++++++++++
> 3 files changed, 467 insertions(+)
> create mode 100644 drivers/i2c/busses/i2c-owl.c
>
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index 4f8df2ec87b1..2062da17e33b 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -762,6 +762,13 @@ config I2C_OMAP
> Like OMAP1510/1610/1710/5912 and OMAP242x.
> For details see http://www.ti.com/omap.
>
> +config I2C_OWL
> + tristate "OWL I2C Controller"
> + depends on ARCH_ACTIONS || COMPILE_TEST
> + help
> + Say Y here if you want to use the I2C bus controller on
> + the Actions Semi OWL SoCs.
> +
> config I2C_PASEMI
> tristate "PA Semi SMBus interface"
> depends on PPC_PASEMI && PCI
> diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> index 5a869144a0c5..b71618f77880 100644
> --- a/drivers/i2c/busses/Makefile
> +++ b/drivers/i2c/busses/Makefile
> @@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_MXS) += i2c-mxs.o
> obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o
> obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o
> obj-$(CONFIG_I2C_OMAP) += i2c-omap.o
> +obj-$(CONFIG_I2C_OWL) += i2c-owl.o
> obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o
> obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pca-platform.o
> obj-$(CONFIG_I2C_PMCMSP) += i2c-pmcmsp.o
> diff --git a/drivers/i2c/busses/i2c-owl.c b/drivers/i2c/busses/i2c-owl.c
> new file mode 100644
> index 000000000000..53100ddfb3cc
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-owl.c
> @@ -0,0 +1,459 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * OWL SoC's I2C driver
> + *
> + * Copyright (c) 2014 Actions Semi Inc.
> + * Author: David Liu <liuwei@actions-semi.com>
> + *
> + * Copyright (c) 2018 Linaro Ltd.
> + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/i2c.h>
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/io.h>
> +
> +/* I2C registers */
> +#define OWL_I2C_REG_CTL (0x0000)
> +#define OWL_I2C_REG_CLKDIV (0x0004)
> +#define OWL_I2C_REG_STAT (0x0008)
> +#define OWL_I2C_REG_ADDR (0x000C)
> +#define OWL_I2C_REG_TXDAT (0x0010)
> +#define OWL_I2C_REG_RXDAT (0x0014)
> +#define OWL_I2C_REG_CMD (0x0018)
> +#define OWL_I2C_REG_FIFOCTL (0x001C)
> +#define OWL_I2C_REG_FIFOSTAT (0x0020)
> +#define OWL_I2C_REG_DATCNT (0x0024)
> +#define OWL_I2C_REG_RCNT (0x0028)
I don't understand why these have parents?
> +
> +/* I2Cx_CTL Bit Mask */
> +#define OWL_I2C_CTL_RB BIT(1)
> +#define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2)
> +#define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0)
> +#define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1)
> +#define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2)
> +#define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3)
> +#define OWL_I2C_CTL_IRQE BIT(5)
> +#define OWL_I2C_CTL_EN BIT(7)
> +#define OWL_I2C_CTL_AE BIT(8)
> +#define OWL_I2C_CTL_SHSM BIT(10)
> +
> +#define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff)
> +
> +/* I2Cx_STAT Bit Mask */
> +#define OWL_I2C_STAT_RACK BIT(0)
> +#define OWL_I2C_STAT_BEB BIT(1)
> +#define OWL_I2C_STAT_IRQP BIT(2)
> +#define OWL_I2C_STAT_LAB BIT(3)
> +#define OWL_I2C_STAT_STPD BIT(4)
> +#define OWL_I2C_STAT_STAD BIT(5)
> +#define OWL_I2C_STAT_BBB BIT(6)
> +#define OWL_I2C_STAT_TCB BIT(7)
> +#define OWL_I2C_STAT_LBST BIT(8)
> +#define OWL_I2C_STAT_SAMB BIT(9)
> +#define OWL_I2C_STAT_SRGC BIT(10)
> +
> +/* I2Cx_CMD Bit Mask */
> +#define OWL_I2C_CMD_SBE BIT(0)
> +#define OWL_I2C_CMD_RBE BIT(4)
> +#define OWL_I2C_CMD_DE BIT(8)
> +#define OWL_I2C_CMD_NS BIT(9)
> +#define OWL_I2C_CMD_SE BIT(10)
> +#define OWL_I2C_CMD_MSS BIT(11)
> +#define OWL_I2C_CMD_WRS BIT(12)
> +#define OWL_I2C_CMD_SECL BIT(15)
> +
> +#define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1)
> +#define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5)
> +
> +/* I2Cx_FIFOCTL Bit Mask */
> +#define OWL_I2C_FIFOCTL_NIB BIT(0)
> +#define OWL_I2C_FIFOCTL_RFR BIT(1)
> +#define OWL_I2C_FIFOCTL_TFR BIT(2)
> +
> +/* I2Cc_FIFOSTAT Bit Mask */
> +#define OWL_I2C_FIFOSTAT_RNB BIT(1)
> +#define OWL_I2C_FIFOSTAT_RFE BIT(2)
> +#define OWL_I2C_FIFOSTAT_TFF BIT(5)
> +#define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16)
> +#define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8)
> +
> +/* I2C bus timeout */
> +#define OWL_I2C_TIMEOUT (msecs_to_jiffies(4 * 1000))
Ditto.
> +
> +#define OWL_I2C_DEFAULT_SPEED 100000
> +#define OWL_I2C_MAX_SPEED 400000
> +
> +struct owl_i2c_dev {
> + struct i2c_adapter adap;
> + struct i2c_msg *msg;
> + struct completion msg_complete;
> + struct clk *clk;
> + void __iomem *base;
> + unsigned long clk_rate;
> + u32 bus_freq;
> + u32 msg_ptr;
> +};
> +
> +static void owl_i2c_update_reg(void __iomem *base, unsigned int val, bool state)
> +{
> + unsigned int regval;
> +
> + regval = readl(base);
> +
> + if (state)
> + regval |= val;
> + else
> + regval &= ~val;
> +
> + writel(regval, base);
> +}
> +
> +static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev)
> +{
> + unsigned int val;
> +
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> + OWL_I2C_CTL_EN, false);
> + mdelay(1);
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> + OWL_I2C_CTL_EN, true);
> +
> + /* Reset FIFO */
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
> + OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR,
> + true);
> +
> + /* Wait until FIFO reset complete */
> + do {
> + val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL);
> + if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR)))
> + break;
> + } while (1);
No way. Get rid of infinite loop.
> +
> + /* Clear status registers */
> + writel(0, i2c_dev->base + OWL_I2C_REG_STAT);
> +}
> +
> +static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev)
> +{
> + unsigned int val;
> +
> + val = (i2c_dev->clk_rate + i2c_dev->bus_freq * 16 - 1) /
> + (i2c_dev->bus_freq * 16);
> +
> + /* Set clock divider factor */
> + writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV);
> +}
> +
> +static void owl_i2c_hw_init(struct owl_i2c_dev *i2c_dev)
> +{
> + /* Reset I2C controller */
> + owl_i2c_reset(i2c_dev);
> +
> + /* Set bus frequency */
> + owl_i2c_set_freq(i2c_dev);
> +}
> +
> +static irqreturn_t owl_i2c_interrupt(int irq, void *_dev)
> +{
> + struct owl_i2c_dev *i2c_dev = _dev;
> + struct i2c_msg *msg = i2c_dev->msg;
> + unsigned int stat, fifostat;
> +
> + fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT);
> + if (fifostat & OWL_I2C_FIFOSTAT_RNB) {
> + dev_warn(&i2c_dev->adap.dev, "received NACK from device");
And if it happens hundreds times in a row?
> + owl_i2c_reset(i2c_dev);
> + goto stop;
> + }
> +
> + stat = readl(i2c_dev->base + OWL_I2C_REG_STAT);
> + if (stat & OWL_I2C_STAT_BEB) {
> + dev_warn(&i2c_dev->adap.dev, "bus error");
Ditto.
> + owl_i2c_reset(i2c_dev);
> + goto stop;
> + }
> +
> + /* Handle FIFO read */
> + if (msg->flags & I2C_M_RD) {
> + while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
> + OWL_I2C_FIFOSTAT_RFE) &&
> + (i2c_dev->msg_ptr < msg->len)) {
> + msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base +
> + OWL_I2C_REG_RXDAT);
> + }
> + } else {
> + /* Handle the remaining bytes which were not sent */
> + while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
> + OWL_I2C_FIFOSTAT_TFF) &&
> + i2c_dev->msg_ptr < msg->len) {
> + writel(msg->buf[i2c_dev->msg_ptr++], i2c_dev->base +
> + OWL_I2C_REG_TXDAT);
> + }
> + }
> +
> +stop:
> + /* Clear pending interrupts */
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
> + OWL_I2C_STAT_IRQP, true);
> +
> + complete_all(&i2c_dev->msg_complete);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static u32 owl_i2c_func(struct i2c_adapter *adap)
> +{
> + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
> +}
> +
> +static int owl_i2c_check_bus_busy(struct i2c_adapter *adap)
> +{
> + struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
> + unsigned long timeout;
> + unsigned int val;
> +
> + timeout = jiffies + OWL_I2C_TIMEOUT;
> + while (1) {
Red flag!
Use
do {
...
} while (time_after(...));
instead.
> + val = readl(i2c_dev->base + OWL_I2C_REG_STAT);
> +
> + /* Check for Arbitration lost */
> + if (val & OWL_I2C_STAT_LAB) {
> + val &= ~OWL_I2C_STAT_LAB;
> + writel(val, i2c_dev->base + OWL_I2C_REG_STAT);
> + return -EAGAIN;
> + }
> +
> + /* Check for Bus busy */
> + if (!(val & OWL_I2C_STAT_BBB))
> + break;
> +
> + if (time_after(jiffies, timeout)) {
> + dev_err(&adap->dev, "Bus busy timeout");
> + return -ETIMEDOUT;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
> + int num)
> +{
> + struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
> + struct i2c_msg *msg;
> + unsigned long time_left;
> + unsigned int i2c_cmd;
> + unsigned int addr;
> + int ret = 0, idx;
> +
> + owl_i2c_hw_init(i2c_dev);
> +
> + ret = owl_i2c_check_bus_busy(adap);
> + if (ret)
> + return ret;
> +
> + reinit_completion(&i2c_dev->msg_complete);
> +
> + /* Enable I2C controller interrupt */
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> + OWL_I2C_CTL_IRQE, true);
> +
> + /*
> + * Select: FIFO enable, Master mode, Stop enable, Data count enable,
> + * Send start bit
> + */
> + i2c_cmd = (OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE
> + | OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE);
> +
> + addr = (msgs[0].addr & 0x7f) << 1;
> +
> + /* Handle repeated start condition */
> + if (num > 1) {
> + /* Set internal address length and enable repeated start */
> + i2c_cmd |= (OWL_I2C_CMD_AS(msgs[0].len + 1)
> + | OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE);
> +
> + /* Write slave address */
> + writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
> +
> + /* Write internal register address */
> + for (idx = 0; idx < msgs[0].len; idx++)
> + writel(msgs[0].buf[idx], i2c_dev->base +
> + OWL_I2C_REG_TXDAT);
> +
> + msg = &msgs[1];
> + } else {
> + /* Set address length */
> + i2c_cmd |= OWL_I2C_CMD_AS(1);
> + msg = &msgs[0];
> + }
> +
> + i2c_dev->msg = msg;
> + i2c_dev->msg_ptr = 0;
> +
> + /* Set data count for the message */
> + writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT);
> +
> + if (msg->flags & I2C_M_RD) {
> + writel((addr | 1), i2c_dev->base + OWL_I2C_REG_TXDAT);
> + } else {
> + writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
Don't we have a helper to construct 8-bit address?
> +
> + /* Write data to FIFO */
> + for (idx = 0; idx < msg->len; idx++) {
> + /* Check for FIFO full */
> + if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT)
> + & OWL_I2C_FIFOSTAT_TFF)
> + break;
> +
> + writel(msg->buf[idx],
> + i2c_dev->base + OWL_I2C_REG_TXDAT);
> + }
> +
> + i2c_dev->msg_ptr = idx;
> + }
> +
> + /* Ingore the NACK if needed */
> + if (msg->flags & I2C_M_IGNORE_NAK)
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
> + OWL_I2C_FIFOCTL_NIB, true);
> + else
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
> + OWL_I2C_FIFOCTL_NIB, false);
> +
> + /* Start the transfer */
> + writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD);
> +
> + time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
> + adap->timeout);
> + if (time_left == 0) {
> + dev_err(&adap->dev, "Transaction timed out");
> + /* Send stop condition and release the bus */
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> + OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB, true);
> + ret = -ETIMEDOUT;
> + }
> +
> + /* Disable I2C controller */
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> + OWL_I2C_CTL_EN, false);
> +
> + return i2c_dev->msg_ptr;
> +}
> +
> +static const struct i2c_algorithm owl_i2c_algorithm = {
> + .master_xfer = owl_i2c_master_xfer,
> + .functionality = owl_i2c_func
> +};
> +
> +static const struct i2c_adapter_quirks owl_i2c_quirks = {
> + .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST,
> + .max_read_len = 240,
> + .max_write_len = 240,
> + .max_comb_1st_msg_len = 6,
> + .max_comb_2nd_msg_len = 240
> +};
> +
> +static int owl_i2c_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct owl_i2c_dev *i2c_dev;
> + struct resource *res;
> + int ret, irq;
> +
> + i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL);
> + if (!i2c_dev)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + i2c_dev->base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(i2c_dev->base))
> + return PTR_ERR(i2c_dev->base);
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0) {
> + dev_err(dev, "failed to get IRQ number\n");
> + return irq;
> + }
> +
> + if (of_property_read_u32(dev->of_node, "clock-frequency",
> + &i2c_dev->bus_freq))
> + i2c_dev->bus_freq = OWL_I2C_DEFAULT_SPEED;
> +
> + /* We support only frequencies of 100k and 400k for now */
> + if (i2c_dev->bus_freq != OWL_I2C_DEFAULT_SPEED &&
> + i2c_dev->bus_freq > OWL_I2C_MAX_SPEED) {
> + dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq);
> + return -EINVAL;
> + }
> +
> + i2c_dev->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(i2c_dev->clk)) {
> + dev_err(dev, "failed to get clock\n");
> + return PTR_ERR(i2c_dev->clk);
> + }
> +
> + ret = clk_prepare_enable(i2c_dev->clk);
> + if (ret)
> + return ret;
> +
> + i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk);
> + if (!i2c_dev->clk_rate) {
> + dev_err(dev, "input clock rate should not be zero\n");
> + ret = -EINVAL;
> + goto disable_clk;
> + }
> +
> + init_completion(&i2c_dev->msg_complete);
> + i2c_dev->adap.owner = THIS_MODULE;
> + i2c_dev->adap.algo = &owl_i2c_algorithm;
> + i2c_dev->adap.timeout = OWL_I2C_TIMEOUT;
> + i2c_dev->adap.quirks = &owl_i2c_quirks;
> + i2c_dev->adap.dev.parent = dev;
> + i2c_dev->adap.dev.of_node = dev->of_node;
> + snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
> + "%s", "OWL I2C adapter");
> + i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
> +
> + platform_set_drvdata(pdev, i2c_dev);
> +
> + ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name,
> + i2c_dev);
> + if (ret) {
> + dev_err(dev, "failed to request irq %d\n", irq);
> + goto disable_clk;
> + }
> +
> + ret = i2c_add_adapter(&i2c_dev->adap);
> +disable_clk:
> + if (ret)
> + clk_disable_unprepare(i2c_dev->clk);
> +
> + return ret;
Can't we go with more usual patter, i.e.
ret = ...;
if (ret)
goto err_handling;
return 0;
err_handling:
...
return ret;
?
> +}
> +
> +static const struct of_device_id owl_i2c_of_match[] = {
> + {.compatible = "actions,s900-i2c"},
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, owl_i2c_of_match);
> +
> +static struct platform_driver owl_i2c_driver = {
> + .probe = owl_i2c_probe,
> + .driver = {
> + .name = "owl-i2c",
> + .of_match_table = of_match_ptr(owl_i2c_of_match),
> + },
> +};
> +module_platform_driver(owl_i2c_driver);
> +
> +MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>");
> +MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
> +MODULE_DESCRIPTION("Actions Semi OWL SoCs I2C driver");
> +MODULE_LICENSE("GPL");
> --
> 2.17.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 5/5] i2c: Add Actions Semi OWL family S900 I2C driver
@ 2018-06-25 9:38 ` Andy Shevchenko
0 siblings, 0 replies; 18+ messages in thread
From: Andy Shevchenko @ 2018-06-25 9:38 UTC (permalink / raw
To: linux-arm-kernel
On Sat, Jun 23, 2018 at 7:11 PM, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
> Add Actions Semi OWL family S900 I2C driver.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> drivers/i2c/busses/Kconfig | 7 +
> drivers/i2c/busses/Makefile | 1 +
> drivers/i2c/busses/i2c-owl.c | 459 +++++++++++++++++++++++++++++++++++
> 3 files changed, 467 insertions(+)
> create mode 100644 drivers/i2c/busses/i2c-owl.c
>
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index 4f8df2ec87b1..2062da17e33b 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -762,6 +762,13 @@ config I2C_OMAP
> Like OMAP1510/1610/1710/5912 and OMAP242x.
> For details see http://www.ti.com/omap.
>
> +config I2C_OWL
> + tristate "OWL I2C Controller"
> + depends on ARCH_ACTIONS || COMPILE_TEST
> + help
> + Say Y here if you want to use the I2C bus controller on
> + the Actions Semi OWL SoCs.
> +
> config I2C_PASEMI
> tristate "PA Semi SMBus interface"
> depends on PPC_PASEMI && PCI
> diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> index 5a869144a0c5..b71618f77880 100644
> --- a/drivers/i2c/busses/Makefile
> +++ b/drivers/i2c/busses/Makefile
> @@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_MXS) += i2c-mxs.o
> obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o
> obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o
> obj-$(CONFIG_I2C_OMAP) += i2c-omap.o
> +obj-$(CONFIG_I2C_OWL) += i2c-owl.o
> obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o
> obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pca-platform.o
> obj-$(CONFIG_I2C_PMCMSP) += i2c-pmcmsp.o
> diff --git a/drivers/i2c/busses/i2c-owl.c b/drivers/i2c/busses/i2c-owl.c
> new file mode 100644
> index 000000000000..53100ddfb3cc
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-owl.c
> @@ -0,0 +1,459 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * OWL SoC's I2C driver
> + *
> + * Copyright (c) 2014 Actions Semi Inc.
> + * Author: David Liu <liuwei@actions-semi.com>
> + *
> + * Copyright (c) 2018 Linaro Ltd.
> + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/i2c.h>
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/io.h>
> +
> +/* I2C registers */
> +#define OWL_I2C_REG_CTL (0x0000)
> +#define OWL_I2C_REG_CLKDIV (0x0004)
> +#define OWL_I2C_REG_STAT (0x0008)
> +#define OWL_I2C_REG_ADDR (0x000C)
> +#define OWL_I2C_REG_TXDAT (0x0010)
> +#define OWL_I2C_REG_RXDAT (0x0014)
> +#define OWL_I2C_REG_CMD (0x0018)
> +#define OWL_I2C_REG_FIFOCTL (0x001C)
> +#define OWL_I2C_REG_FIFOSTAT (0x0020)
> +#define OWL_I2C_REG_DATCNT (0x0024)
> +#define OWL_I2C_REG_RCNT (0x0028)
I don't understand why these have parents?
> +
> +/* I2Cx_CTL Bit Mask */
> +#define OWL_I2C_CTL_RB BIT(1)
> +#define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2)
> +#define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0)
> +#define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1)
> +#define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2)
> +#define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3)
> +#define OWL_I2C_CTL_IRQE BIT(5)
> +#define OWL_I2C_CTL_EN BIT(7)
> +#define OWL_I2C_CTL_AE BIT(8)
> +#define OWL_I2C_CTL_SHSM BIT(10)
> +
> +#define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff)
> +
> +/* I2Cx_STAT Bit Mask */
> +#define OWL_I2C_STAT_RACK BIT(0)
> +#define OWL_I2C_STAT_BEB BIT(1)
> +#define OWL_I2C_STAT_IRQP BIT(2)
> +#define OWL_I2C_STAT_LAB BIT(3)
> +#define OWL_I2C_STAT_STPD BIT(4)
> +#define OWL_I2C_STAT_STAD BIT(5)
> +#define OWL_I2C_STAT_BBB BIT(6)
> +#define OWL_I2C_STAT_TCB BIT(7)
> +#define OWL_I2C_STAT_LBST BIT(8)
> +#define OWL_I2C_STAT_SAMB BIT(9)
> +#define OWL_I2C_STAT_SRGC BIT(10)
> +
> +/* I2Cx_CMD Bit Mask */
> +#define OWL_I2C_CMD_SBE BIT(0)
> +#define OWL_I2C_CMD_RBE BIT(4)
> +#define OWL_I2C_CMD_DE BIT(8)
> +#define OWL_I2C_CMD_NS BIT(9)
> +#define OWL_I2C_CMD_SE BIT(10)
> +#define OWL_I2C_CMD_MSS BIT(11)
> +#define OWL_I2C_CMD_WRS BIT(12)
> +#define OWL_I2C_CMD_SECL BIT(15)
> +
> +#define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1)
> +#define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5)
> +
> +/* I2Cx_FIFOCTL Bit Mask */
> +#define OWL_I2C_FIFOCTL_NIB BIT(0)
> +#define OWL_I2C_FIFOCTL_RFR BIT(1)
> +#define OWL_I2C_FIFOCTL_TFR BIT(2)
> +
> +/* I2Cc_FIFOSTAT Bit Mask */
> +#define OWL_I2C_FIFOSTAT_RNB BIT(1)
> +#define OWL_I2C_FIFOSTAT_RFE BIT(2)
> +#define OWL_I2C_FIFOSTAT_TFF BIT(5)
> +#define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16)
> +#define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8)
> +
> +/* I2C bus timeout */
> +#define OWL_I2C_TIMEOUT (msecs_to_jiffies(4 * 1000))
Ditto.
> +
> +#define OWL_I2C_DEFAULT_SPEED 100000
> +#define OWL_I2C_MAX_SPEED 400000
> +
> +struct owl_i2c_dev {
> + struct i2c_adapter adap;
> + struct i2c_msg *msg;
> + struct completion msg_complete;
> + struct clk *clk;
> + void __iomem *base;
> + unsigned long clk_rate;
> + u32 bus_freq;
> + u32 msg_ptr;
> +};
> +
> +static void owl_i2c_update_reg(void __iomem *base, unsigned int val, bool state)
> +{
> + unsigned int regval;
> +
> + regval = readl(base);
> +
> + if (state)
> + regval |= val;
> + else
> + regval &= ~val;
> +
> + writel(regval, base);
> +}
> +
> +static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev)
> +{
> + unsigned int val;
> +
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> + OWL_I2C_CTL_EN, false);
> + mdelay(1);
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> + OWL_I2C_CTL_EN, true);
> +
> + /* Reset FIFO */
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
> + OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR,
> + true);
> +
> + /* Wait until FIFO reset complete */
> + do {
> + val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL);
> + if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR)))
> + break;
> + } while (1);
No way. Get rid of infinite loop.
> +
> + /* Clear status registers */
> + writel(0, i2c_dev->base + OWL_I2C_REG_STAT);
> +}
> +
> +static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev)
> +{
> + unsigned int val;
> +
> + val = (i2c_dev->clk_rate + i2c_dev->bus_freq * 16 - 1) /
> + (i2c_dev->bus_freq * 16);
> +
> + /* Set clock divider factor */
> + writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV);
> +}
> +
> +static void owl_i2c_hw_init(struct owl_i2c_dev *i2c_dev)
> +{
> + /* Reset I2C controller */
> + owl_i2c_reset(i2c_dev);
> +
> + /* Set bus frequency */
> + owl_i2c_set_freq(i2c_dev);
> +}
> +
> +static irqreturn_t owl_i2c_interrupt(int irq, void *_dev)
> +{
> + struct owl_i2c_dev *i2c_dev = _dev;
> + struct i2c_msg *msg = i2c_dev->msg;
> + unsigned int stat, fifostat;
> +
> + fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT);
> + if (fifostat & OWL_I2C_FIFOSTAT_RNB) {
> + dev_warn(&i2c_dev->adap.dev, "received NACK from device");
And if it happens hundreds times in a row?
> + owl_i2c_reset(i2c_dev);
> + goto stop;
> + }
> +
> + stat = readl(i2c_dev->base + OWL_I2C_REG_STAT);
> + if (stat & OWL_I2C_STAT_BEB) {
> + dev_warn(&i2c_dev->adap.dev, "bus error");
Ditto.
> + owl_i2c_reset(i2c_dev);
> + goto stop;
> + }
> +
> + /* Handle FIFO read */
> + if (msg->flags & I2C_M_RD) {
> + while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
> + OWL_I2C_FIFOSTAT_RFE) &&
> + (i2c_dev->msg_ptr < msg->len)) {
> + msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base +
> + OWL_I2C_REG_RXDAT);
> + }
> + } else {
> + /* Handle the remaining bytes which were not sent */
> + while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
> + OWL_I2C_FIFOSTAT_TFF) &&
> + i2c_dev->msg_ptr < msg->len) {
> + writel(msg->buf[i2c_dev->msg_ptr++], i2c_dev->base +
> + OWL_I2C_REG_TXDAT);
> + }
> + }
> +
> +stop:
> + /* Clear pending interrupts */
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
> + OWL_I2C_STAT_IRQP, true);
> +
> + complete_all(&i2c_dev->msg_complete);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static u32 owl_i2c_func(struct i2c_adapter *adap)
> +{
> + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
> +}
> +
> +static int owl_i2c_check_bus_busy(struct i2c_adapter *adap)
> +{
> + struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
> + unsigned long timeout;
> + unsigned int val;
> +
> + timeout = jiffies + OWL_I2C_TIMEOUT;
> + while (1) {
Red flag!
Use
do {
...
} while (time_after(...));
instead.
> + val = readl(i2c_dev->base + OWL_I2C_REG_STAT);
> +
> + /* Check for Arbitration lost */
> + if (val & OWL_I2C_STAT_LAB) {
> + val &= ~OWL_I2C_STAT_LAB;
> + writel(val, i2c_dev->base + OWL_I2C_REG_STAT);
> + return -EAGAIN;
> + }
> +
> + /* Check for Bus busy */
> + if (!(val & OWL_I2C_STAT_BBB))
> + break;
> +
> + if (time_after(jiffies, timeout)) {
> + dev_err(&adap->dev, "Bus busy timeout");
> + return -ETIMEDOUT;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
> + int num)
> +{
> + struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
> + struct i2c_msg *msg;
> + unsigned long time_left;
> + unsigned int i2c_cmd;
> + unsigned int addr;
> + int ret = 0, idx;
> +
> + owl_i2c_hw_init(i2c_dev);
> +
> + ret = owl_i2c_check_bus_busy(adap);
> + if (ret)
> + return ret;
> +
> + reinit_completion(&i2c_dev->msg_complete);
> +
> + /* Enable I2C controller interrupt */
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> + OWL_I2C_CTL_IRQE, true);
> +
> + /*
> + * Select: FIFO enable, Master mode, Stop enable, Data count enable,
> + * Send start bit
> + */
> + i2c_cmd = (OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE
> + | OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE);
> +
> + addr = (msgs[0].addr & 0x7f) << 1;
> +
> + /* Handle repeated start condition */
> + if (num > 1) {
> + /* Set internal address length and enable repeated start */
> + i2c_cmd |= (OWL_I2C_CMD_AS(msgs[0].len + 1)
> + | OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE);
> +
> + /* Write slave address */
> + writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
> +
> + /* Write internal register address */
> + for (idx = 0; idx < msgs[0].len; idx++)
> + writel(msgs[0].buf[idx], i2c_dev->base +
> + OWL_I2C_REG_TXDAT);
> +
> + msg = &msgs[1];
> + } else {
> + /* Set address length */
> + i2c_cmd |= OWL_I2C_CMD_AS(1);
> + msg = &msgs[0];
> + }
> +
> + i2c_dev->msg = msg;
> + i2c_dev->msg_ptr = 0;
> +
> + /* Set data count for the message */
> + writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT);
> +
> + if (msg->flags & I2C_M_RD) {
> + writel((addr | 1), i2c_dev->base + OWL_I2C_REG_TXDAT);
> + } else {
> + writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
Don't we have a helper to construct 8-bit address?
> +
> + /* Write data to FIFO */
> + for (idx = 0; idx < msg->len; idx++) {
> + /* Check for FIFO full */
> + if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT)
> + & OWL_I2C_FIFOSTAT_TFF)
> + break;
> +
> + writel(msg->buf[idx],
> + i2c_dev->base + OWL_I2C_REG_TXDAT);
> + }
> +
> + i2c_dev->msg_ptr = idx;
> + }
> +
> + /* Ingore the NACK if needed */
> + if (msg->flags & I2C_M_IGNORE_NAK)
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
> + OWL_I2C_FIFOCTL_NIB, true);
> + else
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
> + OWL_I2C_FIFOCTL_NIB, false);
> +
> + /* Start the transfer */
> + writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD);
> +
> + time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
> + adap->timeout);
> + if (time_left == 0) {
> + dev_err(&adap->dev, "Transaction timed out");
> + /* Send stop condition and release the bus */
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> + OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB, true);
> + ret = -ETIMEDOUT;
> + }
> +
> + /* Disable I2C controller */
> + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> + OWL_I2C_CTL_EN, false);
> +
> + return i2c_dev->msg_ptr;
> +}
> +
> +static const struct i2c_algorithm owl_i2c_algorithm = {
> + .master_xfer = owl_i2c_master_xfer,
> + .functionality = owl_i2c_func
> +};
> +
> +static const struct i2c_adapter_quirks owl_i2c_quirks = {
> + .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST,
> + .max_read_len = 240,
> + .max_write_len = 240,
> + .max_comb_1st_msg_len = 6,
> + .max_comb_2nd_msg_len = 240
> +};
> +
> +static int owl_i2c_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct owl_i2c_dev *i2c_dev;
> + struct resource *res;
> + int ret, irq;
> +
> + i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL);
> + if (!i2c_dev)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + i2c_dev->base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(i2c_dev->base))
> + return PTR_ERR(i2c_dev->base);
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0) {
> + dev_err(dev, "failed to get IRQ number\n");
> + return irq;
> + }
> +
> + if (of_property_read_u32(dev->of_node, "clock-frequency",
> + &i2c_dev->bus_freq))
> + i2c_dev->bus_freq = OWL_I2C_DEFAULT_SPEED;
> +
> + /* We support only frequencies of 100k and 400k for now */
> + if (i2c_dev->bus_freq != OWL_I2C_DEFAULT_SPEED &&
> + i2c_dev->bus_freq > OWL_I2C_MAX_SPEED) {
> + dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq);
> + return -EINVAL;
> + }
> +
> + i2c_dev->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(i2c_dev->clk)) {
> + dev_err(dev, "failed to get clock\n");
> + return PTR_ERR(i2c_dev->clk);
> + }
> +
> + ret = clk_prepare_enable(i2c_dev->clk);
> + if (ret)
> + return ret;
> +
> + i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk);
> + if (!i2c_dev->clk_rate) {
> + dev_err(dev, "input clock rate should not be zero\n");
> + ret = -EINVAL;
> + goto disable_clk;
> + }
> +
> + init_completion(&i2c_dev->msg_complete);
> + i2c_dev->adap.owner = THIS_MODULE;
> + i2c_dev->adap.algo = &owl_i2c_algorithm;
> + i2c_dev->adap.timeout = OWL_I2C_TIMEOUT;
> + i2c_dev->adap.quirks = &owl_i2c_quirks;
> + i2c_dev->adap.dev.parent = dev;
> + i2c_dev->adap.dev.of_node = dev->of_node;
> + snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
> + "%s", "OWL I2C adapter");
> + i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
> +
> + platform_set_drvdata(pdev, i2c_dev);
> +
> + ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name,
> + i2c_dev);
> + if (ret) {
> + dev_err(dev, "failed to request irq %d\n", irq);
> + goto disable_clk;
> + }
> +
> + ret = i2c_add_adapter(&i2c_dev->adap);
> +disable_clk:
> + if (ret)
> + clk_disable_unprepare(i2c_dev->clk);
> +
> + return ret;
Can't we go with more usual patter, i.e.
ret = ...;
if (ret)
goto err_handling;
return 0;
err_handling:
...
return ret;
?
> +}
> +
> +static const struct of_device_id owl_i2c_of_match[] = {
> + {.compatible = "actions,s900-i2c"},
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, owl_i2c_of_match);
> +
> +static struct platform_driver owl_i2c_driver = {
> + .probe = owl_i2c_probe,
> + .driver = {
> + .name = "owl-i2c",
> + .of_match_table = of_match_ptr(owl_i2c_of_match),
> + },
> +};
> +module_platform_driver(owl_i2c_driver);
> +
> +MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>");
> +MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
> +MODULE_DESCRIPTION("Actions Semi OWL SoCs I2C driver");
> +MODULE_LICENSE("GPL");
> --
> 2.17.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 5/5] i2c: Add Actions Semi OWL family S900 I2C driver
2018-06-25 9:38 ` Andy Shevchenko
@ 2018-06-26 17:01 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 18+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-26 17:01 UTC (permalink / raw
To: Andy Shevchenko
Cc: Wolfram Sang, Rob Herring, Andreas Färber, Linus Walleij,
linux-i2c, 刘炜, mp-cs, 96boards, devicetree,
Daniel Thompson, amit.kucheria, linux-arm Mailing List,
open list:GPIO SUBSYSTEM, Linux Kernel Mailing List, hzhang,
bdong, Mani Sadhasivam, Thomas Liau, jeff.chen
Hi Andy,
Thanks for the review!
On Mon, Jun 25, 2018 at 12:38:50PM +0300, Andy Shevchenko wrote:
> On Sat, Jun 23, 2018 at 7:11 PM, Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
> > Add Actions Semi OWL family S900 I2C driver.
> >
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> > drivers/i2c/busses/Kconfig | 7 +
> > drivers/i2c/busses/Makefile | 1 +
> > drivers/i2c/busses/i2c-owl.c | 459 +++++++++++++++++++++++++++++++++++
> > 3 files changed, 467 insertions(+)
> > create mode 100644 drivers/i2c/busses/i2c-owl.c
> >
> > diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> > index 4f8df2ec87b1..2062da17e33b 100644
> > --- a/drivers/i2c/busses/Kconfig
> > +++ b/drivers/i2c/busses/Kconfig
> > @@ -762,6 +762,13 @@ config I2C_OMAP
> > Like OMAP1510/1610/1710/5912 and OMAP242x.
> > For details see http://www.ti.com/omap.
> >
> > +config I2C_OWL
> > + tristate "OWL I2C Controller"
> > + depends on ARCH_ACTIONS || COMPILE_TEST
> > + help
> > + Say Y here if you want to use the I2C bus controller on
> > + the Actions Semi OWL SoCs.
> > +
> > config I2C_PASEMI
> > tristate "PA Semi SMBus interface"
> > depends on PPC_PASEMI && PCI
> > diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> > index 5a869144a0c5..b71618f77880 100644
> > --- a/drivers/i2c/busses/Makefile
> > +++ b/drivers/i2c/busses/Makefile
> > @@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_MXS) += i2c-mxs.o
> > obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o
> > obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o
> > obj-$(CONFIG_I2C_OMAP) += i2c-omap.o
> > +obj-$(CONFIG_I2C_OWL) += i2c-owl.o
> > obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o
> > obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pca-platform.o
> > obj-$(CONFIG_I2C_PMCMSP) += i2c-pmcmsp.o
> > diff --git a/drivers/i2c/busses/i2c-owl.c b/drivers/i2c/busses/i2c-owl.c
> > new file mode 100644
> > index 000000000000..53100ddfb3cc
> > --- /dev/null
> > +++ b/drivers/i2c/busses/i2c-owl.c
> > @@ -0,0 +1,459 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * OWL SoC's I2C driver
> > + *
> > + * Copyright (c) 2014 Actions Semi Inc.
> > + * Author: David Liu <liuwei@actions-semi.com>
> > + *
> > + * Copyright (c) 2018 Linaro Ltd.
> > + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/i2c.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/io.h>
> > +
> > +/* I2C registers */
> > +#define OWL_I2C_REG_CTL (0x0000)
> > +#define OWL_I2C_REG_CLKDIV (0x0004)
> > +#define OWL_I2C_REG_STAT (0x0008)
> > +#define OWL_I2C_REG_ADDR (0x000C)
> > +#define OWL_I2C_REG_TXDAT (0x0010)
> > +#define OWL_I2C_REG_RXDAT (0x0014)
> > +#define OWL_I2C_REG_CMD (0x0018)
> > +#define OWL_I2C_REG_FIFOCTL (0x001C)
> > +#define OWL_I2C_REG_FIFOSTAT (0x0020)
> > +#define OWL_I2C_REG_DATCNT (0x0024)
> > +#define OWL_I2C_REG_RCNT (0x0028)
>
> I don't understand why these have parents?
>
I'm not sure what you mean here! Can you please elaborate?
> > +
> > +/* I2Cx_CTL Bit Mask */
> > +#define OWL_I2C_CTL_RB BIT(1)
> > +#define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2)
> > +#define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0)
> > +#define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1)
> > +#define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2)
> > +#define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3)
> > +#define OWL_I2C_CTL_IRQE BIT(5)
> > +#define OWL_I2C_CTL_EN BIT(7)
> > +#define OWL_I2C_CTL_AE BIT(8)
> > +#define OWL_I2C_CTL_SHSM BIT(10)
> > +
> > +#define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff)
> > +
> > +/* I2Cx_STAT Bit Mask */
> > +#define OWL_I2C_STAT_RACK BIT(0)
> > +#define OWL_I2C_STAT_BEB BIT(1)
> > +#define OWL_I2C_STAT_IRQP BIT(2)
> > +#define OWL_I2C_STAT_LAB BIT(3)
> > +#define OWL_I2C_STAT_STPD BIT(4)
> > +#define OWL_I2C_STAT_STAD BIT(5)
> > +#define OWL_I2C_STAT_BBB BIT(6)
> > +#define OWL_I2C_STAT_TCB BIT(7)
> > +#define OWL_I2C_STAT_LBST BIT(8)
> > +#define OWL_I2C_STAT_SAMB BIT(9)
> > +#define OWL_I2C_STAT_SRGC BIT(10)
> > +
> > +/* I2Cx_CMD Bit Mask */
> > +#define OWL_I2C_CMD_SBE BIT(0)
> > +#define OWL_I2C_CMD_RBE BIT(4)
> > +#define OWL_I2C_CMD_DE BIT(8)
> > +#define OWL_I2C_CMD_NS BIT(9)
> > +#define OWL_I2C_CMD_SE BIT(10)
> > +#define OWL_I2C_CMD_MSS BIT(11)
> > +#define OWL_I2C_CMD_WRS BIT(12)
> > +#define OWL_I2C_CMD_SECL BIT(15)
> > +
> > +#define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1)
> > +#define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5)
> > +
> > +/* I2Cx_FIFOCTL Bit Mask */
> > +#define OWL_I2C_FIFOCTL_NIB BIT(0)
> > +#define OWL_I2C_FIFOCTL_RFR BIT(1)
> > +#define OWL_I2C_FIFOCTL_TFR BIT(2)
> > +
> > +/* I2Cc_FIFOSTAT Bit Mask */
> > +#define OWL_I2C_FIFOSTAT_RNB BIT(1)
> > +#define OWL_I2C_FIFOSTAT_RFE BIT(2)
> > +#define OWL_I2C_FIFOSTAT_TFF BIT(5)
> > +#define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16)
> > +#define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8)
> > +
>
> > +/* I2C bus timeout */
> > +#define OWL_I2C_TIMEOUT (msecs_to_jiffies(4 * 1000))
>
> Ditto.
>
Same as above
> > +
> > +#define OWL_I2C_DEFAULT_SPEED 100000
> > +#define OWL_I2C_MAX_SPEED 400000
> > +
> > +struct owl_i2c_dev {
> > + struct i2c_adapter adap;
> > + struct i2c_msg *msg;
> > + struct completion msg_complete;
> > + struct clk *clk;
> > + void __iomem *base;
> > + unsigned long clk_rate;
> > + u32 bus_freq;
> > + u32 msg_ptr;
> > +};
> > +
> > +static void owl_i2c_update_reg(void __iomem *base, unsigned int val, bool state)
> > +{
> > + unsigned int regval;
> > +
> > + regval = readl(base);
> > +
> > + if (state)
> > + regval |= val;
> > + else
> > + regval &= ~val;
> > +
> > + writel(regval, base);
> > +}
> > +
> > +static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev)
> > +{
> > + unsigned int val;
> > +
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> > + OWL_I2C_CTL_EN, false);
> > + mdelay(1);
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> > + OWL_I2C_CTL_EN, true);
> > +
> > + /* Reset FIFO */
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
> > + OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR,
> > + true);
> > +
> > + /* Wait until FIFO reset complete */
> > + do {
> > + val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL);
> > + if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR)))
> > + break;
> > + } while (1);
>
> No way. Get rid of infinite loop.
>
Okay. Can I change it to max of 50 retries with 1ms delay?
> > +
> > + /* Clear status registers */
> > + writel(0, i2c_dev->base + OWL_I2C_REG_STAT);
> > +}
> > +
> > +static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev)
> > +{
> > + unsigned int val;
> > +
> > + val = (i2c_dev->clk_rate + i2c_dev->bus_freq * 16 - 1) /
> > + (i2c_dev->bus_freq * 16);
> > +
> > + /* Set clock divider factor */
> > + writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV);
> > +}
> > +
> > +static void owl_i2c_hw_init(struct owl_i2c_dev *i2c_dev)
> > +{
> > + /* Reset I2C controller */
> > + owl_i2c_reset(i2c_dev);
> > +
> > + /* Set bus frequency */
> > + owl_i2c_set_freq(i2c_dev);
> > +}
> > +
> > +static irqreturn_t owl_i2c_interrupt(int irq, void *_dev)
> > +{
> > + struct owl_i2c_dev *i2c_dev = _dev;
> > + struct i2c_msg *msg = i2c_dev->msg;
> > + unsigned int stat, fifostat;
> > +
> > + fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT);
> > + if (fifostat & OWL_I2C_FIFOSTAT_RNB) {
>
> > + dev_warn(&i2c_dev->adap.dev, "received NACK from device");
>
> And if it happens hundreds times in a row?
>
Should I change it to dev_dbg?
> > + owl_i2c_reset(i2c_dev);
> > + goto stop;
> > + }
> > +
> > + stat = readl(i2c_dev->base + OWL_I2C_REG_STAT);
> > + if (stat & OWL_I2C_STAT_BEB) {
>
> > + dev_warn(&i2c_dev->adap.dev, "bus error");
>
> Ditto.
>
Same as above?
> > + owl_i2c_reset(i2c_dev);
> > + goto stop;
> > + }
> > +
> > + /* Handle FIFO read */
> > + if (msg->flags & I2C_M_RD) {
> > + while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
> > + OWL_I2C_FIFOSTAT_RFE) &&
> > + (i2c_dev->msg_ptr < msg->len)) {
> > + msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base +
> > + OWL_I2C_REG_RXDAT);
> > + }
> > + } else {
> > + /* Handle the remaining bytes which were not sent */
> > + while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
> > + OWL_I2C_FIFOSTAT_TFF) &&
> > + i2c_dev->msg_ptr < msg->len) {
> > + writel(msg->buf[i2c_dev->msg_ptr++], i2c_dev->base +
> > + OWL_I2C_REG_TXDAT);
> > + }
> > + }
> > +
> > +stop:
> > + /* Clear pending interrupts */
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
> > + OWL_I2C_STAT_IRQP, true);
> > +
> > + complete_all(&i2c_dev->msg_complete);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +static u32 owl_i2c_func(struct i2c_adapter *adap)
> > +{
> > + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
> > +}
> > +
> > +static int owl_i2c_check_bus_busy(struct i2c_adapter *adap)
> > +{
> > + struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
> > + unsigned long timeout;
> > + unsigned int val;
> > +
> > + timeout = jiffies + OWL_I2C_TIMEOUT;
>
> > + while (1) {
>
> Red flag!
>
> Use
>
> do {
> ...
> } while (time_after(...));
>
> instead.
>
Okay, will change it.
> > + val = readl(i2c_dev->base + OWL_I2C_REG_STAT);
> > +
> > + /* Check for Arbitration lost */
> > + if (val & OWL_I2C_STAT_LAB) {
> > + val &= ~OWL_I2C_STAT_LAB;
> > + writel(val, i2c_dev->base + OWL_I2C_REG_STAT);
> > + return -EAGAIN;
> > + }
> > +
> > + /* Check for Bus busy */
> > + if (!(val & OWL_I2C_STAT_BBB))
> > + break;
> > +
> > + if (time_after(jiffies, timeout)) {
> > + dev_err(&adap->dev, "Bus busy timeout");
> > + return -ETIMEDOUT;
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
> > + int num)
> > +{
> > + struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
> > + struct i2c_msg *msg;
> > + unsigned long time_left;
> > + unsigned int i2c_cmd;
> > + unsigned int addr;
> > + int ret = 0, idx;
> > +
> > + owl_i2c_hw_init(i2c_dev);
> > +
> > + ret = owl_i2c_check_bus_busy(adap);
> > + if (ret)
> > + return ret;
> > +
> > + reinit_completion(&i2c_dev->msg_complete);
> > +
> > + /* Enable I2C controller interrupt */
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> > + OWL_I2C_CTL_IRQE, true);
> > +
> > + /*
> > + * Select: FIFO enable, Master mode, Stop enable, Data count enable,
> > + * Send start bit
> > + */
> > + i2c_cmd = (OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE
> > + | OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE);
> > +
> > + addr = (msgs[0].addr & 0x7f) << 1;
> > +
> > + /* Handle repeated start condition */
> > + if (num > 1) {
> > + /* Set internal address length and enable repeated start */
> > + i2c_cmd |= (OWL_I2C_CMD_AS(msgs[0].len + 1)
> > + | OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE);
> > +
> > + /* Write slave address */
> > + writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
> > +
> > + /* Write internal register address */
> > + for (idx = 0; idx < msgs[0].len; idx++)
> > + writel(msgs[0].buf[idx], i2c_dev->base +
> > + OWL_I2C_REG_TXDAT);
> > +
> > + msg = &msgs[1];
> > + } else {
> > + /* Set address length */
> > + i2c_cmd |= OWL_I2C_CMD_AS(1);
> > + msg = &msgs[0];
> > + }
> > +
> > + i2c_dev->msg = msg;
> > + i2c_dev->msg_ptr = 0;
> > +
> > + /* Set data count for the message */
> > + writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT);
> > +
>
> > + if (msg->flags & I2C_M_RD) {
> > + writel((addr | 1), i2c_dev->base + OWL_I2C_REG_TXDAT);
> > + } else {
> > + writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
>
> Don't we have a helper to construct 8-bit address?
>
Okay, will use i2c_8bit_addr_from_msg for constructing the address
> > +
> > + /* Write data to FIFO */
> > + for (idx = 0; idx < msg->len; idx++) {
> > + /* Check for FIFO full */
> > + if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT)
> > + & OWL_I2C_FIFOSTAT_TFF)
> > + break;
> > +
> > + writel(msg->buf[idx],
> > + i2c_dev->base + OWL_I2C_REG_TXDAT);
> > + }
> > +
> > + i2c_dev->msg_ptr = idx;
> > + }
> > +
> > + /* Ingore the NACK if needed */
> > + if (msg->flags & I2C_M_IGNORE_NAK)
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
> > + OWL_I2C_FIFOCTL_NIB, true);
> > + else
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
> > + OWL_I2C_FIFOCTL_NIB, false);
> > +
> > + /* Start the transfer */
> > + writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD);
> > +
> > + time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
> > + adap->timeout);
> > + if (time_left == 0) {
> > + dev_err(&adap->dev, "Transaction timed out");
> > + /* Send stop condition and release the bus */
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> > + OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB, true);
> > + ret = -ETIMEDOUT;
> > + }
> > +
> > + /* Disable I2C controller */
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> > + OWL_I2C_CTL_EN, false);
> > +
> > + return i2c_dev->msg_ptr;
> > +}
> > +
> > +static const struct i2c_algorithm owl_i2c_algorithm = {
> > + .master_xfer = owl_i2c_master_xfer,
> > + .functionality = owl_i2c_func
> > +};
> > +
> > +static const struct i2c_adapter_quirks owl_i2c_quirks = {
> > + .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST,
> > + .max_read_len = 240,
> > + .max_write_len = 240,
> > + .max_comb_1st_msg_len = 6,
> > + .max_comb_2nd_msg_len = 240
> > +};
> > +
> > +static int owl_i2c_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct owl_i2c_dev *i2c_dev;
> > + struct resource *res;
> > + int ret, irq;
> > +
> > + i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL);
> > + if (!i2c_dev)
> > + return -ENOMEM;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + i2c_dev->base = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(i2c_dev->base))
> > + return PTR_ERR(i2c_dev->base);
> > +
> > + irq = platform_get_irq(pdev, 0);
> > + if (irq < 0) {
> > + dev_err(dev, "failed to get IRQ number\n");
> > + return irq;
> > + }
> > +
> > + if (of_property_read_u32(dev->of_node, "clock-frequency",
> > + &i2c_dev->bus_freq))
> > + i2c_dev->bus_freq = OWL_I2C_DEFAULT_SPEED;
> > +
> > + /* We support only frequencies of 100k and 400k for now */
> > + if (i2c_dev->bus_freq != OWL_I2C_DEFAULT_SPEED &&
> > + i2c_dev->bus_freq > OWL_I2C_MAX_SPEED) {
> > + dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq);
> > + return -EINVAL;
> > + }
> > +
> > + i2c_dev->clk = devm_clk_get(dev, NULL);
> > + if (IS_ERR(i2c_dev->clk)) {
> > + dev_err(dev, "failed to get clock\n");
> > + return PTR_ERR(i2c_dev->clk);
> > + }
> > +
> > + ret = clk_prepare_enable(i2c_dev->clk);
> > + if (ret)
> > + return ret;
> > +
> > + i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk);
> > + if (!i2c_dev->clk_rate) {
> > + dev_err(dev, "input clock rate should not be zero\n");
> > + ret = -EINVAL;
> > + goto disable_clk;
> > + }
> > +
> > + init_completion(&i2c_dev->msg_complete);
> > + i2c_dev->adap.owner = THIS_MODULE;
> > + i2c_dev->adap.algo = &owl_i2c_algorithm;
> > + i2c_dev->adap.timeout = OWL_I2C_TIMEOUT;
> > + i2c_dev->adap.quirks = &owl_i2c_quirks;
> > + i2c_dev->adap.dev.parent = dev;
> > + i2c_dev->adap.dev.of_node = dev->of_node;
> > + snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
> > + "%s", "OWL I2C adapter");
> > + i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
> > +
> > + platform_set_drvdata(pdev, i2c_dev);
> > +
> > + ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name,
> > + i2c_dev);
> > + if (ret) {
> > + dev_err(dev, "failed to request irq %d\n", irq);
> > + goto disable_clk;
> > + }
> > +
>
> > + ret = i2c_add_adapter(&i2c_dev->adap);
> > +disable_clk:
> > + if (ret)
> > + clk_disable_unprepare(i2c_dev->clk);
> > +
> > + return ret;
>
>
> Can't we go with more usual patter, i.e.
>
> ret = ...;
> if (ret)
> goto err_handling;
>
> return 0;
>
> err_handling:
> ...
> return ret;
>
> ?
>
Ack.
Thanks,
Mani
> > +}
> > +
> > +static const struct of_device_id owl_i2c_of_match[] = {
> > + {.compatible = "actions,s900-i2c"},
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, owl_i2c_of_match);
> > +
> > +static struct platform_driver owl_i2c_driver = {
> > + .probe = owl_i2c_probe,
> > + .driver = {
> > + .name = "owl-i2c",
> > + .of_match_table = of_match_ptr(owl_i2c_of_match),
> > + },
> > +};
> > +module_platform_driver(owl_i2c_driver);
> > +
> > +MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>");
> > +MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
> > +MODULE_DESCRIPTION("Actions Semi OWL SoCs I2C driver");
> > +MODULE_LICENSE("GPL");
> > --
> > 2.17.1
> >
>
>
>
> --
> With Best Regards,
> Andy Shevchenko
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 5/5] i2c: Add Actions Semi OWL family S900 I2C driver
@ 2018-06-26 17:01 ` Manivannan Sadhasivam
0 siblings, 0 replies; 18+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-26 17:01 UTC (permalink / raw
To: linux-arm-kernel
Hi Andy,
Thanks for the review!
On Mon, Jun 25, 2018 at 12:38:50PM +0300, Andy Shevchenko wrote:
> On Sat, Jun 23, 2018 at 7:11 PM, Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
> > Add Actions Semi OWL family S900 I2C driver.
> >
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> > drivers/i2c/busses/Kconfig | 7 +
> > drivers/i2c/busses/Makefile | 1 +
> > drivers/i2c/busses/i2c-owl.c | 459 +++++++++++++++++++++++++++++++++++
> > 3 files changed, 467 insertions(+)
> > create mode 100644 drivers/i2c/busses/i2c-owl.c
> >
> > diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> > index 4f8df2ec87b1..2062da17e33b 100644
> > --- a/drivers/i2c/busses/Kconfig
> > +++ b/drivers/i2c/busses/Kconfig
> > @@ -762,6 +762,13 @@ config I2C_OMAP
> > Like OMAP1510/1610/1710/5912 and OMAP242x.
> > For details see http://www.ti.com/omap.
> >
> > +config I2C_OWL
> > + tristate "OWL I2C Controller"
> > + depends on ARCH_ACTIONS || COMPILE_TEST
> > + help
> > + Say Y here if you want to use the I2C bus controller on
> > + the Actions Semi OWL SoCs.
> > +
> > config I2C_PASEMI
> > tristate "PA Semi SMBus interface"
> > depends on PPC_PASEMI && PCI
> > diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> > index 5a869144a0c5..b71618f77880 100644
> > --- a/drivers/i2c/busses/Makefile
> > +++ b/drivers/i2c/busses/Makefile
> > @@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_MXS) += i2c-mxs.o
> > obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o
> > obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o
> > obj-$(CONFIG_I2C_OMAP) += i2c-omap.o
> > +obj-$(CONFIG_I2C_OWL) += i2c-owl.o
> > obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o
> > obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pca-platform.o
> > obj-$(CONFIG_I2C_PMCMSP) += i2c-pmcmsp.o
> > diff --git a/drivers/i2c/busses/i2c-owl.c b/drivers/i2c/busses/i2c-owl.c
> > new file mode 100644
> > index 000000000000..53100ddfb3cc
> > --- /dev/null
> > +++ b/drivers/i2c/busses/i2c-owl.c
> > @@ -0,0 +1,459 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * OWL SoC's I2C driver
> > + *
> > + * Copyright (c) 2014 Actions Semi Inc.
> > + * Author: David Liu <liuwei@actions-semi.com>
> > + *
> > + * Copyright (c) 2018 Linaro Ltd.
> > + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/i2c.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/io.h>
> > +
> > +/* I2C registers */
> > +#define OWL_I2C_REG_CTL (0x0000)
> > +#define OWL_I2C_REG_CLKDIV (0x0004)
> > +#define OWL_I2C_REG_STAT (0x0008)
> > +#define OWL_I2C_REG_ADDR (0x000C)
> > +#define OWL_I2C_REG_TXDAT (0x0010)
> > +#define OWL_I2C_REG_RXDAT (0x0014)
> > +#define OWL_I2C_REG_CMD (0x0018)
> > +#define OWL_I2C_REG_FIFOCTL (0x001C)
> > +#define OWL_I2C_REG_FIFOSTAT (0x0020)
> > +#define OWL_I2C_REG_DATCNT (0x0024)
> > +#define OWL_I2C_REG_RCNT (0x0028)
>
> I don't understand why these have parents?
>
I'm not sure what you mean here! Can you please elaborate?
> > +
> > +/* I2Cx_CTL Bit Mask */
> > +#define OWL_I2C_CTL_RB BIT(1)
> > +#define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2)
> > +#define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0)
> > +#define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1)
> > +#define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2)
> > +#define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3)
> > +#define OWL_I2C_CTL_IRQE BIT(5)
> > +#define OWL_I2C_CTL_EN BIT(7)
> > +#define OWL_I2C_CTL_AE BIT(8)
> > +#define OWL_I2C_CTL_SHSM BIT(10)
> > +
> > +#define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff)
> > +
> > +/* I2Cx_STAT Bit Mask */
> > +#define OWL_I2C_STAT_RACK BIT(0)
> > +#define OWL_I2C_STAT_BEB BIT(1)
> > +#define OWL_I2C_STAT_IRQP BIT(2)
> > +#define OWL_I2C_STAT_LAB BIT(3)
> > +#define OWL_I2C_STAT_STPD BIT(4)
> > +#define OWL_I2C_STAT_STAD BIT(5)
> > +#define OWL_I2C_STAT_BBB BIT(6)
> > +#define OWL_I2C_STAT_TCB BIT(7)
> > +#define OWL_I2C_STAT_LBST BIT(8)
> > +#define OWL_I2C_STAT_SAMB BIT(9)
> > +#define OWL_I2C_STAT_SRGC BIT(10)
> > +
> > +/* I2Cx_CMD Bit Mask */
> > +#define OWL_I2C_CMD_SBE BIT(0)
> > +#define OWL_I2C_CMD_RBE BIT(4)
> > +#define OWL_I2C_CMD_DE BIT(8)
> > +#define OWL_I2C_CMD_NS BIT(9)
> > +#define OWL_I2C_CMD_SE BIT(10)
> > +#define OWL_I2C_CMD_MSS BIT(11)
> > +#define OWL_I2C_CMD_WRS BIT(12)
> > +#define OWL_I2C_CMD_SECL BIT(15)
> > +
> > +#define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1)
> > +#define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5)
> > +
> > +/* I2Cx_FIFOCTL Bit Mask */
> > +#define OWL_I2C_FIFOCTL_NIB BIT(0)
> > +#define OWL_I2C_FIFOCTL_RFR BIT(1)
> > +#define OWL_I2C_FIFOCTL_TFR BIT(2)
> > +
> > +/* I2Cc_FIFOSTAT Bit Mask */
> > +#define OWL_I2C_FIFOSTAT_RNB BIT(1)
> > +#define OWL_I2C_FIFOSTAT_RFE BIT(2)
> > +#define OWL_I2C_FIFOSTAT_TFF BIT(5)
> > +#define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16)
> > +#define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8)
> > +
>
> > +/* I2C bus timeout */
> > +#define OWL_I2C_TIMEOUT (msecs_to_jiffies(4 * 1000))
>
> Ditto.
>
Same as above
> > +
> > +#define OWL_I2C_DEFAULT_SPEED 100000
> > +#define OWL_I2C_MAX_SPEED 400000
> > +
> > +struct owl_i2c_dev {
> > + struct i2c_adapter adap;
> > + struct i2c_msg *msg;
> > + struct completion msg_complete;
> > + struct clk *clk;
> > + void __iomem *base;
> > + unsigned long clk_rate;
> > + u32 bus_freq;
> > + u32 msg_ptr;
> > +};
> > +
> > +static void owl_i2c_update_reg(void __iomem *base, unsigned int val, bool state)
> > +{
> > + unsigned int regval;
> > +
> > + regval = readl(base);
> > +
> > + if (state)
> > + regval |= val;
> > + else
> > + regval &= ~val;
> > +
> > + writel(regval, base);
> > +}
> > +
> > +static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev)
> > +{
> > + unsigned int val;
> > +
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> > + OWL_I2C_CTL_EN, false);
> > + mdelay(1);
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> > + OWL_I2C_CTL_EN, true);
> > +
> > + /* Reset FIFO */
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
> > + OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR,
> > + true);
> > +
> > + /* Wait until FIFO reset complete */
> > + do {
> > + val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL);
> > + if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR)))
> > + break;
> > + } while (1);
>
> No way. Get rid of infinite loop.
>
Okay. Can I change it to max of 50 retries with 1ms delay?
> > +
> > + /* Clear status registers */
> > + writel(0, i2c_dev->base + OWL_I2C_REG_STAT);
> > +}
> > +
> > +static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev)
> > +{
> > + unsigned int val;
> > +
> > + val = (i2c_dev->clk_rate + i2c_dev->bus_freq * 16 - 1) /
> > + (i2c_dev->bus_freq * 16);
> > +
> > + /* Set clock divider factor */
> > + writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV);
> > +}
> > +
> > +static void owl_i2c_hw_init(struct owl_i2c_dev *i2c_dev)
> > +{
> > + /* Reset I2C controller */
> > + owl_i2c_reset(i2c_dev);
> > +
> > + /* Set bus frequency */
> > + owl_i2c_set_freq(i2c_dev);
> > +}
> > +
> > +static irqreturn_t owl_i2c_interrupt(int irq, void *_dev)
> > +{
> > + struct owl_i2c_dev *i2c_dev = _dev;
> > + struct i2c_msg *msg = i2c_dev->msg;
> > + unsigned int stat, fifostat;
> > +
> > + fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT);
> > + if (fifostat & OWL_I2C_FIFOSTAT_RNB) {
>
> > + dev_warn(&i2c_dev->adap.dev, "received NACK from device");
>
> And if it happens hundreds times in a row?
>
Should I change it to dev_dbg?
> > + owl_i2c_reset(i2c_dev);
> > + goto stop;
> > + }
> > +
> > + stat = readl(i2c_dev->base + OWL_I2C_REG_STAT);
> > + if (stat & OWL_I2C_STAT_BEB) {
>
> > + dev_warn(&i2c_dev->adap.dev, "bus error");
>
> Ditto.
>
Same as above?
> > + owl_i2c_reset(i2c_dev);
> > + goto stop;
> > + }
> > +
> > + /* Handle FIFO read */
> > + if (msg->flags & I2C_M_RD) {
> > + while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
> > + OWL_I2C_FIFOSTAT_RFE) &&
> > + (i2c_dev->msg_ptr < msg->len)) {
> > + msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base +
> > + OWL_I2C_REG_RXDAT);
> > + }
> > + } else {
> > + /* Handle the remaining bytes which were not sent */
> > + while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
> > + OWL_I2C_FIFOSTAT_TFF) &&
> > + i2c_dev->msg_ptr < msg->len) {
> > + writel(msg->buf[i2c_dev->msg_ptr++], i2c_dev->base +
> > + OWL_I2C_REG_TXDAT);
> > + }
> > + }
> > +
> > +stop:
> > + /* Clear pending interrupts */
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
> > + OWL_I2C_STAT_IRQP, true);
> > +
> > + complete_all(&i2c_dev->msg_complete);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +static u32 owl_i2c_func(struct i2c_adapter *adap)
> > +{
> > + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
> > +}
> > +
> > +static int owl_i2c_check_bus_busy(struct i2c_adapter *adap)
> > +{
> > + struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
> > + unsigned long timeout;
> > + unsigned int val;
> > +
> > + timeout = jiffies + OWL_I2C_TIMEOUT;
>
> > + while (1) {
>
> Red flag!
>
> Use
>
> do {
> ...
> } while (time_after(...));
>
> instead.
>
Okay, will change it.
> > + val = readl(i2c_dev->base + OWL_I2C_REG_STAT);
> > +
> > + /* Check for Arbitration lost */
> > + if (val & OWL_I2C_STAT_LAB) {
> > + val &= ~OWL_I2C_STAT_LAB;
> > + writel(val, i2c_dev->base + OWL_I2C_REG_STAT);
> > + return -EAGAIN;
> > + }
> > +
> > + /* Check for Bus busy */
> > + if (!(val & OWL_I2C_STAT_BBB))
> > + break;
> > +
> > + if (time_after(jiffies, timeout)) {
> > + dev_err(&adap->dev, "Bus busy timeout");
> > + return -ETIMEDOUT;
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
> > + int num)
> > +{
> > + struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
> > + struct i2c_msg *msg;
> > + unsigned long time_left;
> > + unsigned int i2c_cmd;
> > + unsigned int addr;
> > + int ret = 0, idx;
> > +
> > + owl_i2c_hw_init(i2c_dev);
> > +
> > + ret = owl_i2c_check_bus_busy(adap);
> > + if (ret)
> > + return ret;
> > +
> > + reinit_completion(&i2c_dev->msg_complete);
> > +
> > + /* Enable I2C controller interrupt */
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> > + OWL_I2C_CTL_IRQE, true);
> > +
> > + /*
> > + * Select: FIFO enable, Master mode, Stop enable, Data count enable,
> > + * Send start bit
> > + */
> > + i2c_cmd = (OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE
> > + | OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE);
> > +
> > + addr = (msgs[0].addr & 0x7f) << 1;
> > +
> > + /* Handle repeated start condition */
> > + if (num > 1) {
> > + /* Set internal address length and enable repeated start */
> > + i2c_cmd |= (OWL_I2C_CMD_AS(msgs[0].len + 1)
> > + | OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE);
> > +
> > + /* Write slave address */
> > + writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
> > +
> > + /* Write internal register address */
> > + for (idx = 0; idx < msgs[0].len; idx++)
> > + writel(msgs[0].buf[idx], i2c_dev->base +
> > + OWL_I2C_REG_TXDAT);
> > +
> > + msg = &msgs[1];
> > + } else {
> > + /* Set address length */
> > + i2c_cmd |= OWL_I2C_CMD_AS(1);
> > + msg = &msgs[0];
> > + }
> > +
> > + i2c_dev->msg = msg;
> > + i2c_dev->msg_ptr = 0;
> > +
> > + /* Set data count for the message */
> > + writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT);
> > +
>
> > + if (msg->flags & I2C_M_RD) {
> > + writel((addr | 1), i2c_dev->base + OWL_I2C_REG_TXDAT);
> > + } else {
> > + writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
>
> Don't we have a helper to construct 8-bit address?
>
Okay, will use i2c_8bit_addr_from_msg for constructing the address
> > +
> > + /* Write data to FIFO */
> > + for (idx = 0; idx < msg->len; idx++) {
> > + /* Check for FIFO full */
> > + if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT)
> > + & OWL_I2C_FIFOSTAT_TFF)
> > + break;
> > +
> > + writel(msg->buf[idx],
> > + i2c_dev->base + OWL_I2C_REG_TXDAT);
> > + }
> > +
> > + i2c_dev->msg_ptr = idx;
> > + }
> > +
> > + /* Ingore the NACK if needed */
> > + if (msg->flags & I2C_M_IGNORE_NAK)
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
> > + OWL_I2C_FIFOCTL_NIB, true);
> > + else
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
> > + OWL_I2C_FIFOCTL_NIB, false);
> > +
> > + /* Start the transfer */
> > + writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD);
> > +
> > + time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
> > + adap->timeout);
> > + if (time_left == 0) {
> > + dev_err(&adap->dev, "Transaction timed out");
> > + /* Send stop condition and release the bus */
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> > + OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB, true);
> > + ret = -ETIMEDOUT;
> > + }
> > +
> > + /* Disable I2C controller */
> > + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
> > + OWL_I2C_CTL_EN, false);
> > +
> > + return i2c_dev->msg_ptr;
> > +}
> > +
> > +static const struct i2c_algorithm owl_i2c_algorithm = {
> > + .master_xfer = owl_i2c_master_xfer,
> > + .functionality = owl_i2c_func
> > +};
> > +
> > +static const struct i2c_adapter_quirks owl_i2c_quirks = {
> > + .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST,
> > + .max_read_len = 240,
> > + .max_write_len = 240,
> > + .max_comb_1st_msg_len = 6,
> > + .max_comb_2nd_msg_len = 240
> > +};
> > +
> > +static int owl_i2c_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct owl_i2c_dev *i2c_dev;
> > + struct resource *res;
> > + int ret, irq;
> > +
> > + i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL);
> > + if (!i2c_dev)
> > + return -ENOMEM;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + i2c_dev->base = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(i2c_dev->base))
> > + return PTR_ERR(i2c_dev->base);
> > +
> > + irq = platform_get_irq(pdev, 0);
> > + if (irq < 0) {
> > + dev_err(dev, "failed to get IRQ number\n");
> > + return irq;
> > + }
> > +
> > + if (of_property_read_u32(dev->of_node, "clock-frequency",
> > + &i2c_dev->bus_freq))
> > + i2c_dev->bus_freq = OWL_I2C_DEFAULT_SPEED;
> > +
> > + /* We support only frequencies of 100k and 400k for now */
> > + if (i2c_dev->bus_freq != OWL_I2C_DEFAULT_SPEED &&
> > + i2c_dev->bus_freq > OWL_I2C_MAX_SPEED) {
> > + dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq);
> > + return -EINVAL;
> > + }
> > +
> > + i2c_dev->clk = devm_clk_get(dev, NULL);
> > + if (IS_ERR(i2c_dev->clk)) {
> > + dev_err(dev, "failed to get clock\n");
> > + return PTR_ERR(i2c_dev->clk);
> > + }
> > +
> > + ret = clk_prepare_enable(i2c_dev->clk);
> > + if (ret)
> > + return ret;
> > +
> > + i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk);
> > + if (!i2c_dev->clk_rate) {
> > + dev_err(dev, "input clock rate should not be zero\n");
> > + ret = -EINVAL;
> > + goto disable_clk;
> > + }
> > +
> > + init_completion(&i2c_dev->msg_complete);
> > + i2c_dev->adap.owner = THIS_MODULE;
> > + i2c_dev->adap.algo = &owl_i2c_algorithm;
> > + i2c_dev->adap.timeout = OWL_I2C_TIMEOUT;
> > + i2c_dev->adap.quirks = &owl_i2c_quirks;
> > + i2c_dev->adap.dev.parent = dev;
> > + i2c_dev->adap.dev.of_node = dev->of_node;
> > + snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
> > + "%s", "OWL I2C adapter");
> > + i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
> > +
> > + platform_set_drvdata(pdev, i2c_dev);
> > +
> > + ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name,
> > + i2c_dev);
> > + if (ret) {
> > + dev_err(dev, "failed to request irq %d\n", irq);
> > + goto disable_clk;
> > + }
> > +
>
> > + ret = i2c_add_adapter(&i2c_dev->adap);
> > +disable_clk:
> > + if (ret)
> > + clk_disable_unprepare(i2c_dev->clk);
> > +
> > + return ret;
>
>
> Can't we go with more usual patter, i.e.
>
> ret = ...;
> if (ret)
> goto err_handling;
>
> return 0;
>
> err_handling:
> ...
> return ret;
>
> ?
>
Ack.
Thanks,
Mani
> > +}
> > +
> > +static const struct of_device_id owl_i2c_of_match[] = {
> > + {.compatible = "actions,s900-i2c"},
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, owl_i2c_of_match);
> > +
> > +static struct platform_driver owl_i2c_driver = {
> > + .probe = owl_i2c_probe,
> > + .driver = {
> > + .name = "owl-i2c",
> > + .of_match_table = of_match_ptr(owl_i2c_of_match),
> > + },
> > +};
> > +module_platform_driver(owl_i2c_driver);
> > +
> > +MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>");
> > +MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
> > +MODULE_DESCRIPTION("Actions Semi OWL SoCs I2C driver");
> > +MODULE_LICENSE("GPL");
> > --
> > 2.17.1
> >
>
>
>
> --
> With Best Regards,
> Andy Shevchenko
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 5/5] i2c: Add Actions Semi OWL family S900 I2C driver
2018-06-26 17:01 ` Manivannan Sadhasivam
@ 2018-06-26 17:18 ` Andy Shevchenko
-1 siblings, 0 replies; 18+ messages in thread
From: Andy Shevchenko @ 2018-06-26 17:18 UTC (permalink / raw
To: Manivannan Sadhasivam
Cc: Wolfram Sang, Rob Herring, Andreas Färber, Linus Walleij,
linux-i2c, 刘炜, mp-cs, 96boards, devicetree,
Daniel Thompson, amit.kucheria, linux-arm Mailing List,
open list:GPIO SUBSYSTEM, Linux Kernel Mailing List, hzhang,
bdong, Mani Sadhasivam, Thomas Liau, jeff.chen
On Tue, Jun 26, 2018 at 8:01 PM, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
> On Mon, Jun 25, 2018 at 12:38:50PM +0300, Andy Shevchenko wrote:
>> On Sat, Jun 23, 2018 at 7:11 PM, Manivannan Sadhasivam
>> <manivannan.sadhasivam@linaro.org> wrote:
>> > +#define OWL_I2C_REG_CTL (0x0000)
>> > +#define OWL_I2C_REG_CLKDIV (0x0004)
>> > +#define OWL_I2C_REG_STAT (0x0008)
>> > +#define OWL_I2C_REG_ADDR (0x000C)
>> > +#define OWL_I2C_REG_TXDAT (0x0010)
>> > +#define OWL_I2C_REG_RXDAT (0x0014)
>> > +#define OWL_I2C_REG_CMD (0x0018)
>> > +#define OWL_I2C_REG_FIFOCTL (0x001C)
>> > +#define OWL_I2C_REG_FIFOSTAT (0x0020)
>> > +#define OWL_I2C_REG_DATCNT (0x0024)
>> > +#define OWL_I2C_REG_RCNT (0x0028)
>>
>> I don't understand why these have parents?
>>
>
> I'm not sure what you mean here! Can you please elaborate?
One has to read 'parens'. Sorry for confusion.
>> > +#define OWL_I2C_TIMEOUT (msecs_to_jiffies(4 * 1000))
>>
>> Ditto.
> Same as above
Ditto.
>> > + /* Wait until FIFO reset complete */
>> > + do {
>> > + val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL);
>> > + if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR)))
>> > + break;
>> > + } while (1);
>>
>> No way. Get rid of infinite loop.
> Okay. Can I change it to max of 50 retries with 1ms delay?
Whatever suitable for HW. Rely on datasheet or other source of
information about this timeouts.
>> > +static irqreturn_t owl_i2c_interrupt(int irq, void *_dev)
>> > + dev_warn(&i2c_dev->adap.dev, "received NACK from device");
>>
>> And if it happens hundreds times in a row?
> Should I change it to dev_dbg?
>> > + dev_warn(&i2c_dev->adap.dev, "bus error");
> Same as above?
ratelimit, another level, tracepoints, getting rid of them completely
— your call.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 5/5] i2c: Add Actions Semi OWL family S900 I2C driver
@ 2018-06-26 17:18 ` Andy Shevchenko
0 siblings, 0 replies; 18+ messages in thread
From: Andy Shevchenko @ 2018-06-26 17:18 UTC (permalink / raw
To: linux-arm-kernel
On Tue, Jun 26, 2018 at 8:01 PM, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
> On Mon, Jun 25, 2018 at 12:38:50PM +0300, Andy Shevchenko wrote:
>> On Sat, Jun 23, 2018 at 7:11 PM, Manivannan Sadhasivam
>> <manivannan.sadhasivam@linaro.org> wrote:
>> > +#define OWL_I2C_REG_CTL (0x0000)
>> > +#define OWL_I2C_REG_CLKDIV (0x0004)
>> > +#define OWL_I2C_REG_STAT (0x0008)
>> > +#define OWL_I2C_REG_ADDR (0x000C)
>> > +#define OWL_I2C_REG_TXDAT (0x0010)
>> > +#define OWL_I2C_REG_RXDAT (0x0014)
>> > +#define OWL_I2C_REG_CMD (0x0018)
>> > +#define OWL_I2C_REG_FIFOCTL (0x001C)
>> > +#define OWL_I2C_REG_FIFOSTAT (0x0020)
>> > +#define OWL_I2C_REG_DATCNT (0x0024)
>> > +#define OWL_I2C_REG_RCNT (0x0028)
>>
>> I don't understand why these have parents?
>>
>
> I'm not sure what you mean here! Can you please elaborate?
One has to read 'parens'. Sorry for confusion.
>> > +#define OWL_I2C_TIMEOUT (msecs_to_jiffies(4 * 1000))
>>
>> Ditto.
> Same as above
Ditto.
>> > + /* Wait until FIFO reset complete */
>> > + do {
>> > + val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL);
>> > + if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR)))
>> > + break;
>> > + } while (1);
>>
>> No way. Get rid of infinite loop.
> Okay. Can I change it to max of 50 retries with 1ms delay?
Whatever suitable for HW. Rely on datasheet or other source of
information about this timeouts.
>> > +static irqreturn_t owl_i2c_interrupt(int irq, void *_dev)
>> > + dev_warn(&i2c_dev->adap.dev, "received NACK from device");
>>
>> And if it happens hundreds times in a row?
> Should I change it to dev_dbg?
>> > + dev_warn(&i2c_dev->adap.dev, "bus error");
> Same as above?
ratelimit, another level, tracepoints, getting rid of them completely
? your call.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2018-06-26 17:18 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-06-23 16:11 [PATCH 0/5] Add Actions Semi S900 I2C support Manivannan Sadhasivam
2018-06-23 16:11 ` Manivannan Sadhasivam
2018-06-23 16:11 ` [PATCH 1/5] dt-bindings: i2c: Add binding for Actions Semi OWL I2C controller Manivannan Sadhasivam
2018-06-23 16:11 ` Manivannan Sadhasivam
2018-06-23 16:11 ` [PATCH 2/5] arm64: dts: actions: Add Actions Semi S900 I2C controller nodes Manivannan Sadhasivam
2018-06-23 16:11 ` Manivannan Sadhasivam
2018-06-23 16:11 ` [PATCH 3/5] arm64: dts: actions: Add pinctrl definition for S900 I2C controller Manivannan Sadhasivam
2018-06-23 16:11 ` Manivannan Sadhasivam
2018-06-23 16:11 ` [PATCH 4/5] arm64: dts: actions: Enable I2C1 and I2C2 in Bubblegum-96 board Manivannan Sadhasivam
2018-06-23 16:11 ` Manivannan Sadhasivam
2018-06-23 16:11 ` [PATCH 5/5] i2c: Add Actions Semi OWL family S900 I2C driver Manivannan Sadhasivam
2018-06-23 16:11 ` Manivannan Sadhasivam
2018-06-25 9:38 ` Andy Shevchenko
2018-06-25 9:38 ` Andy Shevchenko
2018-06-26 17:01 ` Manivannan Sadhasivam
2018-06-26 17:01 ` Manivannan Sadhasivam
2018-06-26 17:18 ` Andy Shevchenko
2018-06-26 17:18 ` Andy Shevchenko
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