From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54584) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Za1A4-0004ud-QT for qemu-devel@nongnu.org; Thu, 10 Sep 2015 08:41:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Za1A0-0004AS-0y for qemu-devel@nongnu.org; Thu, 10 Sep 2015 08:41:08 -0400 Received: from mail-ob0-x22b.google.com ([2607:f8b0:4003:c01::22b]:33183) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Za19z-0004AF-Iz for qemu-devel@nongnu.org; Thu, 10 Sep 2015 08:41:03 -0400 Received: by obbbh8 with SMTP id bh8so33197797obb.0 for ; Thu, 10 Sep 2015 05:41:02 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1441797654-15350-5-git-send-email-kraxel@redhat.com> References: <1441797654-15350-1-git-send-email-kraxel@redhat.com> <1441797654-15350-5-git-send-email-kraxel@redhat.com> Date: Thu, 10 Sep 2015 14:41:02 +0200 Message-ID: From: =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 4/9] virtio-gpu: update headers for virgl/3d List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gerd Hoffmann Cc: QEMU On Wed, Sep 9, 2015 at 1:20 PM, Gerd Hoffmann wrote: > Sync with linux kernel headers with virgl/3d patches applied. > > Signed-off-by: Gerd Hoffmann > --- > include/standard-headers/linux/virtio_gpu.h | 112 ++++++++++++++++++++++= +++++- > 1 file changed, 111 insertions(+), 1 deletion(-) > > diff --git a/include/standard-headers/linux/virtio_gpu.h b/include/standa= rd-headers/linux/virtio_gpu.h > index 72ef815..76e5e52 100644 > --- a/include/standard-headers/linux/virtio_gpu.h > +++ b/include/standard-headers/linux/virtio_gpu.h > @@ -40,6 +40,8 @@ > > #include "standard-headers/linux/types.h" > > +#define VIRTIO_GPU_FEATURE_VIRGL 0 > + > enum virtio_gpu_ctrl_type { > VIRTIO_GPU_UNDEFINED =3D 0, > > @@ -52,6 +54,18 @@ enum virtio_gpu_ctrl_type { > VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D, > VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING, > VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING, > + VIRTIO_GPU_CMD_GET_CAPSET_INFO, > + VIRTIO_GPU_CMD_GET_CAPSET, > + > + /* 3d commands */ > + VIRTIO_GPU_CMD_CTX_CREATE =3D 0x0200, > + VIRTIO_GPU_CMD_CTX_DESTROY, > + VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, > + VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE, > + VIRTIO_GPU_CMD_RESOURCE_CREATE_3D, > + VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, > + VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D, > + VIRTIO_GPU_CMD_SUBMIT_3D, > > /* cursor commands */ > VIRTIO_GPU_CMD_UPDATE_CURSOR =3D 0x0300, > @@ -60,6 +74,8 @@ enum virtio_gpu_ctrl_type { > /* success responses */ > VIRTIO_GPU_RESP_OK_NODATA =3D 0x1100, > VIRTIO_GPU_RESP_OK_DISPLAY_INFO, > + VIRTIO_GPU_RESP_OK_CAPSET_INFO, > + VIRTIO_GPU_RESP_OK_CAPSET, > > /* error responses */ > VIRTIO_GPU_RESP_ERR_UNSPEC =3D 0x1200, > @@ -180,13 +196,107 @@ struct virtio_gpu_resp_display_info { > } pmodes[VIRTIO_GPU_MAX_SCANOUTS]; > }; > > +/* data passed in the control vq, 3d related */ > + > +struct virtio_gpu_box { > + uint32_t x, y, z; > + uint32_t w, h, d; > +}; > + > +/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST= _3D */ > +struct virtio_gpu_transfer_host_3d { > + struct virtio_gpu_ctrl_hdr hdr; > + struct virtio_gpu_box box; > + uint64_t offset; > + uint32_t resource_id; > + uint32_t level; > + uint32_t stride; > + uint32_t layer_stride; > +}; > + > +/* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */ > +#define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0) > +struct virtio_gpu_resource_create_3d { > + struct virtio_gpu_ctrl_hdr hdr; > + uint32_t resource_id; > + uint32_t target; > + uint32_t format; > + uint32_t bind; > + uint32_t width; > + uint32_t height; > + uint32_t depth; > + uint32_t array_size; > + uint32_t last_level; > + uint32_t nr_samples; > + uint32_t flags; > + uint32_t padding; > +}; > + > +/* VIRTIO_GPU_CMD_CTX_CREATE */ > +struct virtio_gpu_ctx_create { > + struct virtio_gpu_ctrl_hdr hdr; > + uint32_t nlen; > + uint32_t padding; > + char debug_name[64]; > +}; > + > +/* VIRTIO_GPU_CMD_CTX_DESTROY */ > +struct virtio_gpu_ctx_destroy { > + struct virtio_gpu_ctrl_hdr hdr; > +}; > + > +/* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURC= E */ > +struct virtio_gpu_ctx_resource { > + struct virtio_gpu_ctrl_hdr hdr; > + uint32_t resource_id; > + uint32_t padding; > +}; > + > +/* VIRTIO_GPU_CMD_SUBMIT_3D */ > +struct virtio_gpu_cmd_submit { > + struct virtio_gpu_ctrl_hdr hdr; > + uint32_t size; > + uint32_t padding; > +}; > + > +#define VIRTIO_GPU_CAPSET_VIRGL 1 > + > +/* VIRTIO_GPU_CMD_GET_CAPSET_INFO */ > +struct virtio_gpu_get_capset_info { > + struct virtio_gpu_ctrl_hdr hdr; > + uint32_t capset_index; > + uint32_t padding; > +}; > + > +/* VIRTIO_GPU_RESP_OK_CAPSET_INFO */ > +struct virtio_gpu_resp_capset_info { > + struct virtio_gpu_ctrl_hdr hdr; > + uint32_t capset_id; > + uint32_t capset_max_version; > + uint32_t capset_max_size; > + uint32_t padding; > +}; > + > +/* VIRTIO_GPU_CMD_GET_CAPSET */ > +struct virtio_gpu_get_capset { > + struct virtio_gpu_ctrl_hdr hdr; > + uint32_t capset_id; > + uint32_t capset_version; > +}; > + > +/* VIRTIO_GPU_RESP_OK_CAPSET */ > +struct virtio_gpu_resp_capset { > + struct virtio_gpu_ctrl_hdr hdr; > + uint8_t capset_data[]; > +}; > + > #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0) > > struct virtio_gpu_config { > uint32_t events_read; > uint32_t events_clear; > uint32_t num_scanouts; > - uint32_t reserved; > + uint32_t num_capsets; > }; > > /* simple formats for fbcon/X use */ > -- > 1.8.3.1 > > Reviewed-by: Marc-Andr=C3=A9 Lureau --=20 Marc-Andr=C3=A9 Lureau