From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AEC0C433ED for ; Wed, 19 May 2021 05:50:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1E6B761355 for ; Wed, 19 May 2021 05:50:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244408AbhESFvo (ORCPT ); Wed, 19 May 2021 01:51:44 -0400 Received: from mail.kernel.org ([198.145.29.99]:41030 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344733AbhESFvP (ORCPT ); Wed, 19 May 2021 01:51:15 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id C2AF0613AE; Wed, 19 May 2021 05:48:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621403316; bh=1M/78skAnJ0O2EA7jNQp+kPITl517U87tfk5kFLTNwo=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=lncOtVDAEu7HiiRH4NkTlbuFCw039Zi8FHl47j/D8o8b6429d7pMItzt92Zuqn/md 1k+rbV+ujbbDaXukjm0H+1NkPpRruxJUxHosKCKcTPnfO6GNB2cIPjYaZNGrcS4NaE GHVDbor7fM1s6Abpb3MI0t36fipqE5D8L9qat0/El/+e3kqejTkZ/+k+/nWPZ1mAzc PuHDXrty+uIaYvgimxcHDmatLZfVnBz1m9NmKx/pMsYHPhhU/LaDAkRTimQGn8DGza QJUH2Wr6BcISqxxFuI7L3y/p6NxUoWyT+xqpmuXHfj3/CzbkZ80qIsBFio5u6tyKDc Ze99bV9iojkDQ== Received: by mail-lf1-f51.google.com with SMTP id i22so17125635lfl.10; Tue, 18 May 2021 22:48:36 -0700 (PDT) X-Gm-Message-State: AOAM530Z5YNbPBOQZEcshdj85YLKgo1Nb7sIpeoJsQEYczyW3I7rN9zJ BKJGf3XYyHCzjNxazYpSZpVx6h/+dLBbx7A6Y6w= X-Google-Smtp-Source: ABdhPJyZmJGTwo2722UUz7WdRiEPE80dASqU/bVhjb4FY4dMa4G28pS/d7JsiaV39IWXLH9tUctL90X9qaaj9JfV8T0= X-Received: by 2002:ac2:5493:: with SMTP id t19mr7208809lfk.346.1621403315041; Tue, 18 May 2021 22:48:35 -0700 (PDT) MIME-Version: 1.0 References: <1621400656-25678-1-git-send-email-guoren@kernel.org> <20210519052048.GA24853@lst.de> In-Reply-To: <20210519052048.GA24853@lst.de> From: Guo Ren Date: Wed, 19 May 2021 13:48:23 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support To: Christoph Hellwig Cc: Anup Patel , Palmer Dabbelt , drew@beagleboard.org, wefu@redhat.com, lazyparser@gmail.com, linux-riscv , Linux Kernel Mailing List , linux-arch , linux-sunxi@lists.linux.dev, Guo Ren Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 19, 2021 at 1:20 PM Christoph Hellwig wrote: > > On Wed, May 19, 2021 at 05:04:13AM +0000, guoren@kernel.org wrote: > > From: Guo Ren > > > > The RISC-V ISA doesn't yet specify how to query or modify PMAs, so let > > vendors define the custom properties of memory regions in PTE. > > Err, hell no. The ISA needs to gets this fixed first. Then we can > talk about alternatives patching things in or trapping in the SBI. > But if the RISC-V ISA can't get these basic done after years we can't > support it in Linux at all. The patchset just leaves a configuration chance for vendors. Before RISC-V ISA fixes it, we should give the chance to let vendor solve their real chip issues. -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19657C433ED for ; Wed, 19 May 2021 05:49:03 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D35C361355 for ; Wed, 19 May 2021 05:49:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D35C361355 Authentication-Results: mail.kernel.org; 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Tue, 18 May 2021 22:48:35 -0700 (PDT) MIME-Version: 1.0 References: <1621400656-25678-1-git-send-email-guoren@kernel.org> <20210519052048.GA24853@lst.de> In-Reply-To: <20210519052048.GA24853@lst.de> From: Guo Ren Date: Wed, 19 May 2021 13:48:23 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support To: Christoph Hellwig Cc: Anup Patel , Palmer Dabbelt , drew@beagleboard.org, wefu@redhat.com, lazyparser@gmail.com, linux-riscv , Linux Kernel Mailing List , linux-arch , linux-sunxi@lists.linux.dev, Guo Ren X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210518_224837_408291_6049A27B X-CRM114-Status: GOOD ( 12.00 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, May 19, 2021 at 1:20 PM Christoph Hellwig wrote: > > On Wed, May 19, 2021 at 05:04:13AM +0000, guoren@kernel.org wrote: > > From: Guo Ren > > > > The RISC-V ISA doesn't yet specify how to query or modify PMAs, so let > > vendors define the custom properties of memory regions in PTE. > > Err, hell no. The ISA needs to gets this fixed first. Then we can > talk about alternatives patching things in or trapping in the SBI. > But if the RISC-V ISA can't get these basic done after years we can't > support it in Linux at all. The patchset just leaves a configuration chance for vendors. Before RISC-V ISA fixes it, we should give the chance to let vendor solve their real chip issues. -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv