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charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Apr 11, 2024 at 2:23=E2=80=AFPM Sean Christopherson wrote: > > On Fri, Jan 26, 2024, Xiong Zhang wrote: > > From: Mingwei Zhang > > > > Intercept full-width GP counter MSRs in passthrough PMU if guest does n= ot > > have the capability to write in full-width. In addition, opportunistica= lly > > add a warning if non-full-width counter MSRs are also intercepted, in w= hich > > case it is a clear mistake. > > > > Co-developed-by: Xiong Zhang > > Signed-off-by: Xiong Zhang > > Signed-off-by: Mingwei Zhang > > --- > > arch/x86/kvm/vmx/pmu_intel.c | 10 +++++++++- > > 1 file changed, 9 insertions(+), 1 deletion(-) > > > > diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.= c > > index 7f6cabb2c378..49df154fbb5b 100644 > > --- a/arch/x86/kvm/vmx/pmu_intel.c > > +++ b/arch/x86/kvm/vmx/pmu_intel.c > > @@ -429,6 +429,13 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu= , struct msr_data *msr_info) > > default: > > if ((pmc =3D get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || > > (pmc =3D get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) { > > + if (is_passthrough_pmu_enabled(vcpu) && > > + !(msr & MSR_PMC_FULL_WIDTH_BIT) && > > + !msr_info->host_initiated) { > > + pr_warn_once("passthrough PMU never inter= cepts non-full-width PMU counters\n"); > > + return 1; > > This is broken, KVM must be prepared to handle WRMSR (and RDMSR and RDPMC= ) that > come in through the emulator. Don't tell me that we are still supporting CPUs that don't have "unrestricted guest"! Sigh.