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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Hi Martin, On Mon, 28 Jun 2021 at 01:55, Martin Blumenstingl wrote: > > Hi Anand, > > On Sun, Jun 27, 2021 at 10:07 PM Anand Moon wrote: > [...] > > Sorry for the delay. > > We could switch the reset logic to > > *devm_reset_control_get_optional_exclusive* as below > > to fix the reset line, since both the dwc2 c90c0000.usb and c9040000.usb > > will have their own context to reset control register, it means the > > reset line is not share > > between two USB PHY nodes. > This is something I don't understand. > As discussed in our previous mails reset_control_reset in case of the > USB PHY driver (which uses the RESET_USB_OTG reset line for *both* > PHYs) is equivalent to the following code in the vendor kernel: > aml_cbus_update_bits(0x1102, 0x1<<2, 0x1<<2) > > We have two PHYs but only one reset line. So in my own words I > describe the reset line as being shared. > > > > > - priv->reset = devm_reset_control_get_optional_shared(&pdev->dev, NULL); > > + priv->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, > > + "reset"); > Have you boot-tested this? > Without any .dts changes this will return NULL because there's no > reset-names = "reset"; in the .dts(i). > If you replace "reset" with NULL then I assume that the second PHY > will fail to obtain the reset line because it's shared between two > devices but we're trying to obtain it exclusively for both (PHYs). > Thanks for your review comments. I have always tested with both the phy enable and with proper DTS changes. Yes, it gives false-positive results while initialization of the USB PHY. Odroid C2 it will pass but on Odroid C1 it will fail kid off. But it seems to me that the order of the PHY reset is kind of a problem. Thanks for looking into my changes. > > Best regards, > Martin Thanks -Anand _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FDBFC07E98 for ; Fri, 2 Jul 2021 19:13:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 516B261421 for ; Fri, 2 Jul 2021 19:13:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230353AbhGBTQF (ORCPT ); Fri, 2 Jul 2021 15:16:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230222AbhGBTQE (ORCPT ); Fri, 2 Jul 2021 15:16:04 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 160C5C061762 for ; Fri, 2 Jul 2021 12:13:32 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id c17so17720722ejk.13 for ; Fri, 02 Jul 2021 12:13:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=LiyPmQuAW3XlG5gYx+V9yk5pkVvqy7w5OWOrUXZV0n4=; b=UqPAdZftWYY/hk0t9QGH80VUUUp/cKIvZzpInyllIdYALv7pGWNN6EYb9DX8rcEMfg zBT7n0f90YpRpe4pm+sZHhKKiNbjvLF2Nq/+J+hvaxE5/A95hfGWA+eeDj5jVgoO/m/R 74L7X1Gw0RgCrJthw0yHiT07xHc8pevXDS70DIK35llk81VFruoaOTMo7fCMeCer2Lpf i6uzHmj2HWfaG07TPSFMpbjssHiFUmzNMNWgSvuY34IgN0kLn+4ldpmVceLG+M7b27Gq Aq1oAHDLJvyN1O3j/YqXAvULs0h9d8I/HOHuhYMzU892zHesxICaEtGgmqNO2si9HoIp BfiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=LiyPmQuAW3XlG5gYx+V9yk5pkVvqy7w5OWOrUXZV0n4=; b=sYH7CNGNY7x+0vN4wMkErxvh8bKzGO/2eChXNqqhCuPz/YHowE9TaldDwMUaUouoX5 b3sokH7gcZV/IXPDRLE9RU6XkJYC42kOeBZJYHcp0soHw/TmKSoFgz8SW72Q/D8p5n17 1DfH/QlhP+QkBhkptL75tHzH66ivm9hmaOIz9gYpe5fblX0tZcnlVgYkwMyktxZajvYZ RzFxA1vhxAXrWboD7lI62QYoO9CYHxFcjSYnFkB2JMG8OjDlqLa8lHA4Yg1jQrsbcX1u cMOtrX/Us7Udr7Vi5vtw04JEsNLk3i1OWru3lg5QFgfYSdveG6htr+a7QpETi0zELQTP B1ug== X-Gm-Message-State: AOAM530tEepBwdld7LRQvEfgu5DWsJYc7X1N7JaX31rqfWcN0+Ipcpdh 8QM7tjbVPv3niGk/3NJWvNFcG2W96zTMLmsBbvE= X-Google-Smtp-Source: ABdhPJx6rCEfImxf0/oDRg3iTiYeiezG2pXiv9sBVa07dhGxSS/k1eVBygBfRjdpHHRbL45t/o9PphKHpVMb00DyKjQ= X-Received: by 2002:a17:906:2dd5:: with SMTP id h21mr1325571eji.522.1625253210735; Fri, 02 Jul 2021 12:13:30 -0700 (PDT) MIME-Version: 1.0 References: <20210617194154.2397-1-linux.amoon@gmail.com> <20210617194154.2397-7-linux.amoon@gmail.com> In-Reply-To: From: Anand Moon Date: Sat, 3 Jul 2021 00:43:19 +0530 Message-ID: Subject: Re: [RFCv1 6/8] phy: amlogic: meson8b-usb2: Use phy reset callback function To: Martin Blumenstingl Cc: Kishon Vijay Abraham I , Vinod Koul , Neil Armstrong , Kevin Hilman , Jerome Brunet , Philipp Zabel , linux-phy@lists.infradead.org, linux-arm-kernel , linux-amlogic@lists.infradead.org, Linux Kernel Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Martin, On Mon, 28 Jun 2021 at 01:55, Martin Blumenstingl wrote: > > Hi Anand, > > On Sun, Jun 27, 2021 at 10:07 PM Anand Moon wrote: > [...] > > Sorry for the delay. > > We could switch the reset logic to > > *devm_reset_control_get_optional_exclusive* as below > > to fix the reset line, since both the dwc2 c90c0000.usb and c9040000.usb > > will have their own context to reset control register, it means the > > reset line is not share > > between two USB PHY nodes. > This is something I don't understand. > As discussed in our previous mails reset_control_reset in case of the > USB PHY driver (which uses the RESET_USB_OTG reset line for *both* > PHYs) is equivalent to the following code in the vendor kernel: > aml_cbus_update_bits(0x1102, 0x1<<2, 0x1<<2) > > We have two PHYs but only one reset line. So in my own words I > describe the reset line as being shared. > > > > > - priv->reset = devm_reset_control_get_optional_shared(&pdev->dev, NULL); > > + priv->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, > > + "reset"); > Have you boot-tested this? > Without any .dts changes this will return NULL because there's no > reset-names = "reset"; in the .dts(i). > If you replace "reset" with NULL then I assume that the second PHY > will fail to obtain the reset line because it's shared between two > devices but we're trying to obtain it exclusively for both (PHYs). > Thanks for your review comments. I have always tested with both the phy enable and with proper DTS changes. Yes, it gives false-positive results while initialization of the USB PHY. Odroid C2 it will pass but on Odroid C1 it will fail kid off. But it seems to me that the order of the PHY reset is kind of a problem. Thanks for looking into my changes. > > Best regards, > Martin Thanks -Anand From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.7 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C86D7C07E97 for ; Fri, 2 Jul 2021 19:13:35 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8061161416 for ; Fri, 2 Jul 2021 19:13:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8061161416 Authentication-Results: mail.kernel.org; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Hi Martin, On Mon, 28 Jun 2021 at 01:55, Martin Blumenstingl wrote: > > Hi Anand, > > On Sun, Jun 27, 2021 at 10:07 PM Anand Moon wrote: > [...] > > Sorry for the delay. > > We could switch the reset logic to > > *devm_reset_control_get_optional_exclusive* as below > > to fix the reset line, since both the dwc2 c90c0000.usb and c9040000.usb > > will have their own context to reset control register, it means the > > reset line is not share > > between two USB PHY nodes. > This is something I don't understand. > As discussed in our previous mails reset_control_reset in case of the > USB PHY driver (which uses the RESET_USB_OTG reset line for *both* > PHYs) is equivalent to the following code in the vendor kernel: > aml_cbus_update_bits(0x1102, 0x1<<2, 0x1<<2) > > We have two PHYs but only one reset line. So in my own words I > describe the reset line as being shared. > > > > > - priv->reset = devm_reset_control_get_optional_shared(&pdev->dev, NULL); > > + priv->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, > > + "reset"); > Have you boot-tested this? > Without any .dts changes this will return NULL because there's no > reset-names = "reset"; in the .dts(i). > If you replace "reset" with NULL then I assume that the second PHY > will fail to obtain the reset line because it's shared between two > devices but we're trying to obtain it exclusively for both (PHYs). > Thanks for your review comments. I have always tested with both the phy enable and with proper DTS changes. Yes, it gives false-positive results while initialization of the USB PHY. Odroid C2 it will pass but on Odroid C1 it will fail kid off. But it seems to me that the order of the PHY reset is kind of a problem. Thanks for looking into my changes. > > Best regards, > Martin Thanks -Anand -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.7 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06056C07E95 for ; Fri, 2 Jul 2021 19:15:27 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B81A661411 for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Martin, On Mon, 28 Jun 2021 at 01:55, Martin Blumenstingl wrote: > > Hi Anand, > > On Sun, Jun 27, 2021 at 10:07 PM Anand Moon wrote: > [...] > > Sorry for the delay. > > We could switch the reset logic to > > *devm_reset_control_get_optional_exclusive* as below > > to fix the reset line, since both the dwc2 c90c0000.usb and c9040000.usb > > will have their own context to reset control register, it means the > > reset line is not share > > between two USB PHY nodes. > This is something I don't understand. > As discussed in our previous mails reset_control_reset in case of the > USB PHY driver (which uses the RESET_USB_OTG reset line for *both* > PHYs) is equivalent to the following code in the vendor kernel: > aml_cbus_update_bits(0x1102, 0x1<<2, 0x1<<2) > > We have two PHYs but only one reset line. So in my own words I > describe the reset line as being shared. > > > > > - priv->reset = devm_reset_control_get_optional_shared(&pdev->dev, NULL); > > + priv->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, > > + "reset"); > Have you boot-tested this? > Without any .dts changes this will return NULL because there's no > reset-names = "reset"; in the .dts(i). > If you replace "reset" with NULL then I assume that the second PHY > will fail to obtain the reset line because it's shared between two > devices but we're trying to obtain it exclusively for both (PHYs). > Thanks for your review comments. I have always tested with both the phy enable and with proper DTS changes. Yes, it gives false-positive results while initialization of the USB PHY. Odroid C2 it will pass but on Odroid C1 it will fail kid off. But it seems to me that the order of the PHY reset is kind of a problem. Thanks for looking into my changes. > > Best regards, > Martin Thanks -Anand _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel